JPS6349829U - - Google Patents

Info

Publication number
JPS6349829U
JPS6349829U JP14342786U JP14342786U JPS6349829U JP S6349829 U JPS6349829 U JP S6349829U JP 14342786 U JP14342786 U JP 14342786U JP 14342786 U JP14342786 U JP 14342786U JP S6349829 U JPS6349829 U JP S6349829U
Authority
JP
Japan
Prior art keywords
power supply
latch
supply terminal
resistor
cmos device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14342786U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14342786U priority Critical patent/JPS6349829U/ja
Publication of JPS6349829U publication Critical patent/JPS6349829U/ja
Pending legal-status Critical Current

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  • Power Sources (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の基本構成図、第2図は本考案
の一実施例を示す構成図である。 図中、1は電源ライン、2はCMOSデバイス
、Rは小抵抗、SWは抵抗Rの動作を等価的に示
すスイツチである。
FIG. 1 is a basic configuration diagram of the present invention, and FIG. 2 is a configuration diagram showing an embodiment of the present invention. In the figure, 1 is a power supply line, 2 is a CMOS device, R is a small resistor, and SW is a switch equivalently showing the operation of resistor R.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電源ラインとCMOSデバイスの電源端子との
間に小抵抗を挿入し、該抵抗にラツチアツプ電流
が流れて該電源端子の電圧が低下することで該デ
バイス内のラツチアツプした素子をリセツトする
ようにしてなることを特徴とするCMOSデバイ
スのラツチアツプ解除回路。
A small resistor is inserted between the power supply line and the power supply terminal of the CMOS device, and a latch-up current flows through the resistor and the voltage at the power supply terminal decreases, thereby resetting the latch-up element in the device. A latch-up release circuit for a CMOS device, characterized by the following.
JP14342786U 1986-09-18 1986-09-18 Pending JPS6349829U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14342786U JPS6349829U (en) 1986-09-18 1986-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14342786U JPS6349829U (en) 1986-09-18 1986-09-18

Publications (1)

Publication Number Publication Date
JPS6349829U true JPS6349829U (en) 1988-04-04

Family

ID=31053103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14342786U Pending JPS6349829U (en) 1986-09-18 1986-09-18

Country Status (1)

Country Link
JP (1) JPS6349829U (en)

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