JPS6347968A - Memory capable of executing logical inversion - Google Patents

Abstract

PURPOSE:To obtain a memory which does not erase information even after a long time keeping and can simultaneously invert parallel pieces of information simply by an external control by providing specific control means in the memory having an electron beam source, electron beam detecting means and driving means for driving the source for transmitting and receiving an electron beam in a unit time. CONSTITUTION:An electron beam source E, electron beam detecting means D, and driving means T for driving the source E by a signal of the means D are made one unit, and an electron beam is transmitted and received between two or more units U. Control means is provided between the means D and the source E contained in one unit U so that, when the beam is incident to the means D at the time of logical calculation, the beam is not emitted from the source E, and when the beam is not incident to the means D, the beam is not emitted from the source E. For example, two or more memory units MU having a plurality of the units U are oppositely disposed, and means SE for deflecting the beam emitted from the source E to be incident to the means D contained in the same unit U is provided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a method for performing logic inversion operations using a solid-state electron beam source that can hold arranged logic information and perform logic inversion operations in parallel. It is related to storage devices.

[Prior Art] Conventionally, memory elements using electron beams, for example (G, W
, Ellis et al., Applied Physics L
etters, Vol, 24°NO, 9, 1974, 4
Page 19) Natonori BEAMO5,! : What is called is known. This is MOS (Metal Oxid
In this method, a writing electron beam is made incident on a capacitor having a Sem1conductor structure to accumulate holes in an insulating layer, and a part of the accumulated holes are erased by a reading electron beam, thereby reading information.

When reading such information, a portion of the information is destroyed, so it is impossible to read the information many times. Therefore, since rewriting is required in order to perform multiple readings, it takes a long time to obtain the necessary information, and there is also the disadvantage that information may be lost if left unused for a long time.

In addition, in such a storage device, when performing logical inversion of the information that has been enriched, the information is sequentially read out and input to an inverting circuit constituted by an electric circuit, and the output is again sequentially transferred to the memory element. This requires a complicated method such as writing to a file, which requires a very long calculation time.

On the other hand, in the field of image processing that has been researched or put into practical use in recent years, it is necessary to perform an operation to invert all pixels of pixel information arranged two-dimensionally in parallel; Because information is sequentially read from the image memory, passed through an inversion circuit, and then written back to the image memory, there is a need for an arithmetic device that can invert all pixels at high speed and in parallel, with a long calculation time. .

[Object of the Invention] The object of the present invention is to develop a logic in which information does not disappear even when left unused for a long time in a storage device using electron beams, and which allows parallel information to be easily inverted all at once by external control. Notes on possible inversion operations! The goal is to provide equipment.

[Summary of the Invention] The gist of the present invention for achieving the above-mentioned object is to combine an electron beam source, an electron beam detection means, and a driving means for driving the electron beam source with a signal from the electron beam detection means into one unit. , a storage device that transmits and receives electron beams between at least two units,
An electron beam is not emitted from the electron beam source when the electron beam is incident on the electron beam detection means during a logical operation, and an electron beam is emitted from the electron beam source when the electron beam is not incident on the electron beam detection means. The storage device is characterized in that a control means is provided between the electron beam detection means and the electron beam source included in the one unit so that the storage device can perform a logic inversion operation.

[Embodiments of the invention] The present invention will be explained in detail based on illustrated embodiments.

FIG. 1 is a schematic diagram of the configuration, in which a plurality of units U each consisting of an electron beam detection means, a drive means T, and an electron beam source E are arranged.MUI and MU2 are installed facing each other. ing. In FIG. 1, to simplify the explanation, memory units MUI and MU2 are expressed as units U111, [121, υ131, [2+1.0221,
u231 and unit 0112, U122, U! 32, U2
Although it is displayed as a matrix of 2 rows and 3 columns consisting of 12, U222, and U232, each unit U can be created by semiconductor technology such as epitaxial growth or phosphorography, so it can be formed at a very high density. It becomes possible. Also, memory unit MU! A power supply VA is provided between and MU2.

Furthermore, a deflection electrode SEI as an electromagnetic field generating means is arranged above the memory units MUI and MU2, a deflection electrode SE2 is arranged below the memory units MUI and MU2, and the deflection electrode SEI is arranged below the memory units MUI and MU2. A power supply vI] is provided between and SE2.

Here, units Ull to U232 arranged in memory units MUI and MU2 will be explained with reference to FIGS. 2 and 3. FIG. 2 shows a cross-sectional view of one unit U, which consists of an electron beam detection means consisting of a pn junction, a driving means T, and an electron beam source E, and includes a substrate SS formed of a p-type semiconductor. An insulating layer INS is formed on the surface, and an insulating layer I
Various electrodes are attached to the top of the NS. Substrate S
The electron beam detection means formed by npn junction from the back side in S is attached with an electrode ON for giving a reference voltage, an electrode 0 for giving a positive bias, and an electrode OP for giving a reverse bias. A ground electrode GN is attached to SS through an opening in an insulating layer INS.

Next to the electron beam detection means is an np'' from the back side in the board SS.
A drive means T formed by n'' junction is provided, and electrodes TB, TE, and TG are attached to this drive means T.Furthermore, next to the drive means T, there is a back side in the substrate SS. An electron beam source E is arranged, which is formed by connecting np"pn" to the electron beam source.The electron beam source E is as shown in FIG. A preferred example is a solid-state electron beam source disclosed in Japanese Patent Application Laid-open No. 56-15529, Japanese Patent Application Laid-Open No. 57-38528, etc.
An extraction electrode EC is provided which generates electrons by the avalanche effect by applying a positive potential to the electrode EP, that is, by applying a reverse bias, and by applying a positive voltage, extracts the electrons from the opening into the vacuum. ing. Further, as a solid-state electron beam source using such a pn junction, a negative work function type that operates with forward bias, other so-called field emission type, thermionic emission type, etc. can be used.

FIG. 3 is a block circuit diagram for driving each of the above-mentioned elements. A switch SWI is connected to M and a pole [11 of the electron beam detection means, a switch SWN is connected to the electrode DN, a switch SWP is connected to the electrode UP, a switch SWB is connected to the electrode TB of the driving means T, and a switch SWE is connected to the electrode TO. is connected. The writing mode in which the electron beam EB is incident on the electron beam detection means is W mode, the mode in which information is read from the electron beam detection means is R mode, and the electron beam EB is emitted from the electron beam source E in accordance with this information. Set the line emission mode to G mode, switch SWI, switch S-N
, the switch S is connected to the writing and electron beam output terminal W/
G and a read terminal R are provided facing each other, and a voltage VW is applied to the terminal W/G corresponding to the switch SWI.
However, voltage VR is applied to terminal R, terminal W/G corresponding to switch SWN is connected to ground electrode GN, and terminal R
is open. Further, a negative potential 17B is applied to the terminal W/G corresponding to the switch SWP, and the terminal R is connected to a capacitor C for temporarily saving information, so that part of the information can be saved. Further, the switch SWB and the switch SWE of the driving means T are provided with write and read terminals W/R and an electron beam emission switch G facing each other, and the terminal W/R corresponding to the switch SWB is connected to the switch SWP. A negative potential VB is applied to the terminal W/G corresponding to the switch swp.
It is connected to a terminal R corresponding to , and information from the outside is inputted through an input terminal IN. The terminal W/R corresponding to the switch SWE is connected to the ground electrode GN, and the voltage VE is applied to the terminal G. Furthermore, '?' of the driving means T? The tL pole TC is connected to the electrode EN of the electron beam source E via a resistor, and information can be taken out from the electrode TE of the driving means T through an output terminal OUT. The extraction electrode EG is connected to a power source VG through a resistor RV, and the electrode EP is connected to a ground electrode ON.

First, considering the W mode of writing, switches SWI, SWN, and SWP are each connected to the terminal W/G side, and switches SWB and SWW are each connected to the terminal W/R side, so the electron beam In the detection means, a positive voltage VW is applied as a bias to the electrode aDI using the electrode DN as a reference voltage, and a reverse bias voltage VB is applied to the electrode DP. In addition, the electrode O
No current flows between N and DP due to reverse bias. Here, the electron beam EB passes through the electrode DI and generates an electron-0-hole pair within the insulating layer INS, and the holes are accumulated in the insulation +31Ns near the interface between the insulating layer INS and the n-layer. The charges accumulated as holes are stored relatively stably even when the electron beam EB is not emitted. At this time, in the driving means T, since the reverse bias voltage VB is applied to the electrode TB via the switch SWB as well as to the electrode DP, the electrode is in a cut-off state and the electron beam source E does not operate.

In addition, in the R mode of reading, the switch SWI
, 5WFI, and S buttocks P are each connected to the terminal R side, and S and F edges S buttocks B and SWE are each connected to terminal 1L.
It is connected to the llR side. At this time, a method for detecting the state of the electron beam detection means is a phenomenon in which the breakdown voltage when a reverse voltage is applied between the electrodes DI and DP differs depending on the presence or absence of charges accumulated in the insulating layer INS. One preferable method is to use That is, the electrode DI
at a higher positive voltage than when writing to the insulating layer I.
Reading is performed by applying a voltage VR that does not break down when no charge is accumulated in the NS, but breaks down and causes a current to flow when the charge is accumulated in the insulating layer INS above a threshold value. . By utilizing such a breakdown effect, a highly sensitive electron beam detection means can be obtained.

If we consider a case where the electron beam detection means breaks down due to the charge M accumulated on the insulating layer INS to a value greater than a threshold value, a current flows from the electrode DI to DP, and the capacitor C is charged through the switch SwP. If the electron beam detection means does not break down, no current flows from the electrode DI to the DP, and the capacitor C is not charged.

Next, in G mode of electron beam emission, switch S
R, S, and SWP are respectively on the terminal W/G side.
Switches SWB and SWE are each connected to the terminal G side. If the capacitor C is charged, this electric charge flows forward from the electrode TB to the electrode TE through the switch SWB, so that the driving means T is turned on, but the voltage VE is bypassed from the electrode TC of the driving means T to the electrode TE. If no voltage is applied to the electrode EN of the electron beam source E and the electron beam EB is not emitted from the electron beam source E, and if the capacitor C is not charged, no current flows from the electrode 7B to the drive means T. remains in the off state, so that the voltage VE is at the electrode E
Since it is applied to X, the electron beam source E is driven and the electron beam EB is emitted. That is, when the electron beam EB enters the electron beam detection means in the W mode, the electron beam EB is not emitted from the electron beam source E in the G mode following the R mode, and the electron beam EB enters the electron beam detection means in the W mode. When no EB is incident, the electron beam EB is emitted from the electron beam source E in the G mode following the R mode.

The amount of current of the electron beam EB emitted from the electron beam source E can be controlled by a variable resistor RV inserted between the electron beam source E and the power supply VC.

In addition, there is a completely destructive readout RD mode in which almost all of the charge accumulated in the electron beam detection means is discharged to the outside during the readout R mode, and a completely destructive readout RD mode in which only a part of the accumulated voltage is readout. , an RN mode for partially destructive readout that leaves a charge amount greater than a threshold value can be set. This RD
Selection between the mode and the RN mode can be easily achieved by, for example, reading out data in a time sufficient for the accumulated charges to be discharged in the RD mode, and reading out in a relatively short time in the RN mode. Further, in FIG. 3, in the G mode, the presence or absence of information can be electrically read from the output terminal OUT, and information can be written by forcibly applying a voltage to the input terminal IN.

The operation of the embodiment using the above-mentioned memory unit U will be explained again using FIG. 1 and FIGS. 4 to 7. In this embodiment, the memory unit MUI
1 unit above and memory 22 placed opposite it)
One unit on MU2, a total of two units □, handles 1 bit of information. This information is a Boolean value and is referred to here as '
1'' and rQJ, and one cycle is formed by the W mode, R mode, and G mode of memory unit 2 MU1 and the following W mode, R mode, and G mode of memory unit MU2. This l cycle consists of a NOP cycle that holds the logic value at the end of the previous cycle, and a NO cycle that inverts the logic.
One of two T cycles is selectable.

FIG. 4 shows the NOP cycle of the embodiment of FIG.
Figure (a) shows a state in which the memory unit (MUI) is in G mode and the memory unit Xυ2 is in W mode. Memory 2) From the MUI, for example, electron beam source E121. Electron beam EB is emitted from E131 and E211. No voltage is applied to the deflection electrodes SEI and SE2, and the electron beam EB is accelerated by the acceleration electric field in the direction from the memory unit MU1 to MU2 due to the acceleration voltage VAI, and the electron beam detection means [1122, D132,
D212 is reached. Figure 4 (b) 1± (a) followed by memory unit] - MU2 is in G mode, memory unit MU
This shows a state in which l is in W mode. As mentioned above, in units 0111, [112, ..., when electron beam EB is incident in W mode, electron beam EB is not emitted in G mode following R mode, and electron beam EB is incident in W mode. If not, use electron beam EB in G mode following R mode.
is emitted. Therefore, in Fig. 4(b), the electron beam @j
The electron beams EB emitted from El 12, E222, and E232 are accelerated by an accelerating electric field from the memory unit MU2 toward the MUI due to the accelerating voltage VA2, and are detected by the electron beam detection means ottt.

The 0th order cycle that enters 0221 and 0231 is MOP
If it is a cycle, it will return to Figure 4 (a) again, so NOP
As long as the cycle continues, the state shown in FIG. 4 is maintained.

A set of two units of elements that handle one bit emits an electron beam EB from the MUI side, and generates a memory! -The state in which it is not emitted from the MU2 side, and the memory unit,
)The electron beam EB is emitted from the MU2 side and the memory 22),
From the MUI side, it takes one of two states: a state in which it does not emit data. Therefore, for example, the group in which the electron beam EB is being emitted from the memory unit MU1 side has the logical value "
1”, memory 22) Electron beam E from Mt12 side
If we decide that the set that is in the state of emitting B represents the logical value "0", then in the example of FIG.
,0112), (0121,0122), ([131,
0132), ([211, υ212), (υ221.0
222), ([231,0232) in the order of “Oll, 1
．． This means that the information "1.0.0" is held.

FIG. 5 shows a NOT cycle in the embodiment of FIG. 1. In FIG. 5(a), Ul in the memory unit is in the G mode, and electron beam source E121. Electron beam EB is emitted from E131 and E211. At this time, reverse acceleration voltage VRI is applied between memory units MUI and MU2, and memory unit MU
A reverse accelerating electric field is formed from 2 to MUI. Further, a deflection voltage VDI is applied between the deflection electrodes SEI and SF3, and a deflection electric field is formed in the direction from the electrode SEI to SF3. If the electric field induced by these voltages is suitably controlled, the electron beam EB emitted from the electron beam source E in each unit U of the MUI can be detected by the electron beam detection means in the same unit U of the MUI. It is possible to deflect the light so that it is incident on the opposite direction. That is, electron beam sources E121, E1
31. The electron beams EB emitted from the electron beams E211 can be respectively made incident on the electron beam detection means D121.0131.0211. As mentioned above, memory unit M
In each unit U of U, in the G mode, the electron beam detection means is in the same state as in the W mode, so that the incident electron beam EB causes charges to be accumulated in the electron beam detection means again.

FIG. 5(b) continues from FIG. 5(a) and shows the memory unit M.
This shows the state when U2 is in G mode. 5(a) by making the reverse acceleration voltage VR2 applied between MUI and MU2 and the deflection voltage VD2 applied between deflection electrodes SEI and SF3 have opposite polarities to those in FIG. 5(a). Similarly to (a), the electron beams EB emitted from the electron beam sources E112, E222, and E232 of the memory unit MU2 are detected by the electron beam detection means D11 of the same unit U, respectively.
2, it will be incident on D222 and D232.

FIG. 6 shows a NOP cycle following the NOT cycle shown in FIG. In FIG. 6(a), memory unit M
When U1 enters the G mode, the electron beam source El11. of unit U to which no electron beam EB was incident in the previous cycle. E221
．． The electron beam EB is emitted from E231, and is not emitted from other units U. Therefore, in the MOP cycle of FIG. 6, the logical information held is 1 as before.
Group 2 unit elements (Ull, U112), (0121,
U122), (U131,0132), (0211,0
212), (U221.0222), (0231,02
32) (7) "rl, Olo, O1■, 1" at No. 11, and by going through the NOT cycle of FIG. 5 for the state of FIG. 4, all the logical values are inverted.

Figure 7 shows the memory values when each cycle from Figures 4 to 6 is executed continuously.MUI, W, R of MU2
, G mode, acceleration voltage, and deflection voltage timing diagram. By combining and executing such timing diagrams, it becomes possible to perform storage and inversion operations of logical value information arranged two-dimensionally in parallel in parallel at high speed.

In the explanation of the embodiment, an example was shown in which the electron beam EB is reversely accelerated and deflected by an electric field to perform a logical inversion operation, but the electron beam EB can also be deflected by a magnetic field, and the electron beam EB emitted from the electron beam source E can be deflected by a magnetic field. The electron beam EB can be made incident on the electron beam detection means of the same unit U.

In addition, in the explanation of the embodiment, one cycle is defined as including the G mode of the memory unit MU1 and the subsequent G mode of the memory unit MU2. Therefore, in the NOT cycle shown in FIG. 5, the memory as shown in FIG. 22) MU2
Although we have shown an example of the operation in which the electron beam EB is emitted from the
Logic inversion can be performed by executing only FIG. 5(a) as a NOT cycle and moving to the next NOP cycle.

Furthermore, in the description of the embodiment, the memory units MUI and NU2
However, such an arrangement is not a wooden one, but uses an electromagnetic field or other means to create an electron beam EB between the corresponding units U of MUI and MtJ2.
and the electron beam EB emitted from the electron beam source E by external control is in the same unit U as this electron beam source E.
It is clear that any configuration in which the electron beam can be deflected so as to be incident on the electron beam detecting means in the present invention does not depart from the spirit of the present invention.

[Effects of the Invention] As explained above, the storage device capable of logical inversion operations according to the present invention retains information arranged two-dimensionally in a storage device using electron beams, or stores all information in parallel and It is suitable for image processing operations because it can perform logic inversion at high speed.

[Brief explanation of the drawing]

The drawings show an embodiment of a storage device capable of performing logical inversion operations according to the present invention, and FIG. 1 is a schematic perspective view thereof, and FIG.
The figure is an explanatory diagram of the electron beam detection means, driving means, and electron beam source, Figure 3 is a block circuit diagram, Figures 4 to 6 are explanatory diagrams of various operations, and Figure 7 is a timing diagram of these operations. be. (Symbols are electron beam detection means, T is drive means, E is electron beam source, EB is electron beam, MUI, MU2 is memory unit)
, SEI, SE2 are deflection electrodes. Patent applicant Canon Co., Ltd. ＋＋１□! 1? Figure 1 Figure 2 Figure 3 IN 0LIT Figure 4 W, Figure 4 (b) Figure 5 Figure 5 (b) Figure 6 (a> Figure 6 (b) Figure 7

Claims (1)

[Claims] 1. An electron beam source, an electron beam detection means, and a driving means for driving the electron beam source according to a signal from the electron beam detection means are defined as one unit, and an electron beam is transmitted and received between at least two units. The storage device is configured to store the electrons when the electron beam is not emitted from the electron beam source when the electron beam is incident on the electron beam detection means during a logical operation, and when the electron beam is not incident on the electron beam detection means. A storage device capable of logical inversion operations, characterized in that a control means is provided between the electron beam detection means included in one unit and the electron beam source so that an electron beam is emitted from the radiation source. 2. A storage device capable of performing a logic inversion operation according to claim 1, wherein at least two memory units each having a plurality of said units are arranged facing each other. 3. A storage device capable of logic inversion operation according to claim 2, wherein a reverse electric field is alternately applied between the opposed memory units. 4. Claim 1, further comprising means for deflecting the electron beam emitted from the electron beam source so that it enters the electron beam detection means included in the same unit as the electron beam source. A storage device capable of logical inversion operations. 5. A storage device capable of performing logic inversion operations according to claim 4, wherein the means for deflecting the electron beam is an electric field or a magnetic field.