JPS6347292B2 - - Google Patents

Info

Publication number
JPS6347292B2
JPS6347292B2 JP57035596A JP3559682A JPS6347292B2 JP S6347292 B2 JPS6347292 B2 JP S6347292B2 JP 57035596 A JP57035596 A JP 57035596A JP 3559682 A JP3559682 A JP 3559682A JP S6347292 B2 JPS6347292 B2 JP S6347292B2
Authority
JP
Japan
Prior art keywords
detection circuit
voltage
detection
circuit means
pin diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57035596A
Other languages
Japanese (ja)
Other versions
JPS58153422A (en
Inventor
Atsushi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57035596A priority Critical patent/JPS58153422A/en
Publication of JPS58153422A publication Critical patent/JPS58153422A/en
Publication of JPS6347292B2 publication Critical patent/JPS6347292B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02Transmitters
    • H04B1/04Circuits
    • H04B1/0466Fault detection or indication

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transmitters (AREA)
  • Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)

Description

【発明の詳細な説明】 本発明は、誤送信を防止するための、動作範囲
の広い電力検出回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power detection circuit with a wide operating range to prevent erroneous transmission.

従来のこの種の回路を第1図に示す。第1図に
おいて1は送信出力が印加される端子、2は送信
出力端子、3は結合コンデンサ、4および5は検
波ダイオード、6は平滑用コンデンサ、7は検波
出力端子、8は検波回路用の負荷抵抗である。
A conventional circuit of this type is shown in FIG. In Figure 1, 1 is the terminal to which the transmission output is applied, 2 is the transmission output terminal, 3 is the coupling capacitor, 4 and 5 are the detection diodes, 6 is the smoothing capacitor, 7 is the detection output terminal, and 8 is the detection circuit. It is load resistance.

この回路では端子1より2に通過する高周波電
力を検出するため、検波ダイオード4および5コ
ンデンサ3および6より成る倍電圧検波回路が、
微少容量の結合コンデンサ3を介して送信出力回
路に結合されている。従来、この結合コンデンサ
3による結合度は検波ダイオード保護のため、お
よび検波器で発生する高調波ひずみ成分を送信出
力に混入させることのないように充分疎結合にし
ておく必要があつた。一方、誤送信は、たとえば
正規出力レベルより20ないし60デシベル低いレベ
ルで送出される場合があり、このような低レベル
の出力を検知するためには前記結合度を密にする
必要がある。したがつて結合度の設定が非常に困
難で、低レベル誤送信の検出ができなくなるなど
の欠点があつた。
In this circuit, in order to detect the high frequency power passing from terminal 1 to terminal 2, a voltage doubler detection circuit consisting of detection diodes 4 and 5 and capacitors 3 and 6 is used.
It is coupled to a transmission output circuit via a coupling capacitor 3 with a minute capacitance. Conventionally, the degree of coupling by the coupling capacitor 3 has been required to be sufficiently loose to protect the detection diode and to prevent harmonic distortion components generated by the detector from being mixed into the transmission output. On the other hand, erroneous transmission may be transmitted at a level that is 20 to 60 decibels lower than the normal output level, and in order to detect such a low level output, it is necessary to make the coupling degree dense. Therefore, it is very difficult to set the degree of coupling, and there are drawbacks such as the inability to detect low-level erroneous transmissions.

本発明は、これらの欠点を除去し、正規の送信
出力レベルよりも充分に低いレベルの誤送信出力
レベルの検知を可能にするとともに、検出用ダイ
オードを破壊することのないよう保護することを
可能にすることを目的としたものである。第2図
は、本発明の一実施例による基本的な誤送信防止
用検出回路の構成を示す図である。第2図におい
て、1Aは送信出力を印加する端子、2Aは送信
出力端子、9は結合回路手段、10は電圧または
電流可変抵抗素子、11は検波回路、12は検波
電圧が一定値を越えたことを検出するための電圧
検知回路。13は可変抵抗素子10を駆動するた
めの駆動回路である。
The present invention eliminates these drawbacks, makes it possible to detect an erroneous transmission output level that is sufficiently lower than the normal transmission output level, and protects the detection diode from being destroyed. The purpose is to FIG. 2 is a diagram showing the configuration of a basic detection circuit for preventing erroneous transmission according to an embodiment of the present invention. In Fig. 2, 1A is a terminal for applying a transmission output, 2A is a transmission output terminal, 9 is a coupling circuit means, 10 is a voltage or current variable resistance element, 11 is a detection circuit, and 12 is a terminal when the detection voltage exceeds a certain value. A voltage detection circuit to detect this. 13 is a drive circuit for driving the variable resistance element 10.

この実施例は送信出力回路部と検波回路部との
間に可変抵抗素子を介在させて、送信出力に応じ
て前記結合度を可変させようとするものである。
In this embodiment, a variable resistance element is interposed between the transmission output circuit section and the detection circuit section, and the degree of coupling is varied in accordance with the transmission output.

第3図は上記した実施例のより具体的な回路構
成を示すものである。第3図において、第1図と
同じ機能部は同一の符号で示す。14は結合コン
デンサ、15は電流制御型可変抵抗素子(PINダ
イオード)である。17,21はバイパス用コン
デンサ、18,19は端子20より印加された直
流電圧を分圧して、PINダイオード15に逆バイ
アスを印加するための分圧抵抗である。16は
PINダイオード15に順バイアスを印加するため
のチヨークコイルで、このインダクタンス値は
PINダイオード15の遮断時の残留容量による信
号の漏洩を並列共振により打消するように選定さ
れる。ここは、定電圧ダイオード(ツエナーダイ
オード)で、検波出力電圧端子7の出力電圧が一
定値を越えると導通して、チヨークコイル16、
PINダイオード15、分圧用抵抗19を通して、
PINダイオード15に順方向電流を供給する。
FIG. 3 shows a more specific circuit configuration of the above-described embodiment. In FIG. 3, the same functional parts as in FIG. 1 are indicated by the same reference numerals. 14 is a coupling capacitor, and 15 is a current controlled variable resistance element (PIN diode). 17 and 21 are bypass capacitors, and 18 and 19 are voltage dividing resistors for dividing the DC voltage applied from the terminal 20 and applying a reverse bias to the PIN diode 15. 16 is
This is a chiyoke coil for applying forward bias to the PIN diode 15, and the inductance value is
It is selected so that signal leakage due to residual capacitance when the PIN diode 15 is cut off is canceled by parallel resonance. This is a constant voltage diode (Zener diode), which becomes conductive when the output voltage of the detection output voltage terminal 7 exceeds a certain value, and the
Through the PIN diode 15 and voltage dividing resistor 19,
A forward current is supplied to the PIN diode 15.

次にこの実施例の動作について説明する。端子
1A,2Aの間を通過する送信電圧が微少値のと
き当然、端子7に現われる検波出力電圧は小さ
い。したがつてツエナーダイオード22は導通せ
ず、PINダイオード15のアノード側の電位は、
抵抗23により接地電位となる。一方、PINダイ
オード15のカソード側には、端子20より印加
され、抵抗18,19により分圧された正電圧が
常時印加されているのでPINダイオード15は逆
バイアス状態となり非導通となる。また、このと
きPINダイオード15の非導通時残留容量により
高周波信号がPINダイオード15を介してアース
側に漏洩し、検波部への高周波入力信号が減少し
て、検出感度が低下することを防止するため、使
用帯域において前記残留容量と並列共振するよう
にコイル16、コンデンサ17が、PINダイオー
ド15と並列に挿入されている。
Next, the operation of this embodiment will be explained. Naturally, when the transmission voltage passing between terminals 1A and 2A is a very small value, the detected output voltage appearing at terminal 7 is small. Therefore, the Zener diode 22 is not conductive, and the potential on the anode side of the PIN diode 15 is
The resistor 23 provides a ground potential. On the other hand, since a positive voltage applied from the terminal 20 and divided by the resistors 18 and 19 is always applied to the cathode side of the PIN diode 15, the PIN diode 15 becomes in a reverse bias state and becomes non-conductive. Also, at this time, due to the residual capacitance of the PIN diode 15 when it is non-conducting, high frequency signals are prevented from leaking to the ground side via the PIN diode 15, reducing the high frequency input signal to the detection section and reducing the detection sensitivity. Therefore, a coil 16 and a capacitor 17 are inserted in parallel with the PIN diode 15 so as to resonate in parallel with the residual capacitance in the usage band.

また送信電力が一定以上の値になると、検波出
力端子7の電圧が上昇して、ツエナーダイオード
22が導通する。従つて検波出力電圧がツエナー
ダイオード22、チヨークコイル16を介して
PINダイオード15のアノード側に供給され、ツ
エナーダイオード22のツエナー電圧値、および
抵抗18,19により定まる逆バイアス電圧値な
どにより決定される電圧値を越えるとPINダイオ
ード15が導通する。PINダイオード15は順方
向電流値が増すほど高周波抵抗値が減少するの
で、検波ダイオード4および5には一定値以上の
高周波電力が加わらず、検波ダイオードの劣化お
よび破損を防止できる。
Further, when the transmission power reaches a certain value or more, the voltage at the detection output terminal 7 increases and the Zener diode 22 becomes conductive. Therefore, the detection output voltage is
The voltage is supplied to the anode side of the PIN diode 15, and when the voltage exceeds a voltage value determined by the Zener voltage value of the Zener diode 22, the reverse bias voltage value determined by the resistors 18 and 19, etc., the PIN diode 15 becomes conductive. Since the high frequency resistance value of the PIN diode 15 decreases as the forward current value increases, high frequency power exceeding a certain value is not applied to the detection diodes 4 and 5, thereby preventing deterioration and damage of the detection diodes.

第4図は、本発明の回路の入出力特性を示すも
ので、横軸が入力電圧で、縦軸は検波出力端子電
圧である。図中、点線で示しているのは第1図に
示すような従来回路の入出力特性であり、実線で
示したのは、上記実施例の入出力特性である。本
実施例においては検波部に対して、一定値以上の
高周波電力しか加わつていないことが図より明ら
かである。
FIG. 4 shows the input/output characteristics of the circuit of the present invention, where the horizontal axis is the input voltage and the vertical axis is the detection output terminal voltage. In the figure, the dotted line indicates the input/output characteristic of the conventional circuit as shown in FIG. 1, and the solid line indicates the input/output characteristic of the above embodiment. It is clear from the figure that in this embodiment, only high frequency power above a certain value is applied to the detection section.

第5図は他の具体的な実施例を示すものであ
る。第5図において第3図と同一の機能部は同一
の符号で示してある。第5図では、PINダイオー
ド29が検波部に直列に前置されている点が第3
図と異なつている。第5図中23は直流阻止用コ
ンデンサで、チヨークコイル24はPINダイオー
ド29の非導通時残留容量を打消す並列共振コイ
ルとして働く。25,30は高周波チヨークコイ
ル、26はPINダイオードへの順方向バイアス印
加端子、27,28は分圧抵抗である。
FIG. 5 shows another specific embodiment. In FIG. 5, the same functional parts as in FIG. 3 are indicated by the same reference numerals. In Figure 5, the third point is that the PIN diode 29 is placed in series in front of the detection section.
It is different from the illustration. Reference numeral 23 in FIG. 5 is a DC blocking capacitor, and the chiyoke coil 24 functions as a parallel resonant coil that cancels out the residual capacitance of the PIN diode 29 when it is non-conducting. 25 and 30 are high frequency choke coils, 26 is a forward bias application terminal to the PIN diode, and 27 and 28 are voltage dividing resistors.

この実施例では第3図の場合と異なり、PINダ
イオード29は、高周波出力電力が微少値のとき
導通し、一定値を越えると次第に逆バイアスが掛
かつて非導通状態となる点に特徴がある。
This embodiment is different from the case shown in FIG. 3 in that the PIN diode 29 is conductive when the high-frequency output power is a very small value, and when it exceeds a certain value, it is gradually reverse biased and becomes non-conductive.

以上説明したように、本発明によれば、従来、
動作範囲の狭かつた誤送信検出回路の動作範囲を
広げることができるので、大出力の送信機の送信
停止時に、誤まつて微少電力が送出された場合の
検出が可能となる。また、本発明は、従来の回路
に、能力素子を追加することなく、少数の受動素
子を追加するのみで実現できるから、安価で信頼
性も高く工業上の利用価値は大きい。
As explained above, according to the present invention, conventionally,
Since the operating range of the erroneous transmission detection circuit, which has a narrow operating range, can be expanded, it becomes possible to detect a case where a small amount of power is erroneously sent out when a high-output transmitter stops transmitting. Further, since the present invention can be realized by adding only a small number of passive elements to a conventional circuit without adding any performance elements, it is inexpensive, highly reliable, and has great industrial utility value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の誤送信検出回路の結線図、第2
図は本発明の一実施例による誤送信検出回路のブ
ロツク図、第3図はその具体的な回路構成を示す
結線図、第4図は同特性図、第5図は他の具体的
な回路構成を示す結線図である。 10……可変抵抗素子、11……検波回路、1
2……電圧検知回路。
Figure 1 is a wiring diagram of a conventional erroneous transmission detection circuit;
The figure is a block diagram of an erroneous transmission detection circuit according to an embodiment of the present invention, FIG. 3 is a wiring diagram showing its specific circuit configuration, FIG. 4 is a characteristic diagram of the same, and FIG. 5 is another specific circuit. FIG. 3 is a wiring diagram showing the configuration. 10... Variable resistance element, 11... Detection circuit, 1
2... Voltage detection circuit.

Claims (1)

【特許請求の範囲】 1 電流可変抵抗素子と、この電流可変抵抗素子
を介して、送信出力回路に疎結合された検波回路
手段と、この検波回路手段の出力電圧が一定値を
越えたことを検知するための電圧検知回路手段と
を備え、前記電流可変抵抗素子を、前記電圧検知
回路手段により制御することを特徴とする誤送信
検出回路。 2 電流可変抵抗素子として、PINダイオードを
用い、検波回路手段としてシヨツトキーダイオー
ドを用い、電圧検知回路手段としてツエナーダイ
オードを用いたことを特徴とする特許請求の範囲
第1項記載の誤送信検出回路。
[Claims] 1. A variable current resistance element, a detection circuit means loosely coupled to a transmission output circuit via the variable current resistance element, and a detection circuit means for detecting when the output voltage of the detection circuit means exceeds a certain value. What is claimed is: 1. An erroneous transmission detection circuit, comprising: voltage detection circuit means for detecting a false transmission, wherein said current variable resistance element is controlled by said voltage detection circuit means. 2. Erroneous transmission detection according to claim 1, characterized in that a PIN diode is used as the current variable resistance element, a Schottky diode is used as the detection circuit means, and a Zener diode is used as the voltage detection circuit means. circuit.
JP57035596A 1982-03-05 1982-03-05 Detecting circuit of error transmission Granted JPS58153422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57035596A JPS58153422A (en) 1982-03-05 1982-03-05 Detecting circuit of error transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57035596A JPS58153422A (en) 1982-03-05 1982-03-05 Detecting circuit of error transmission

Publications (2)

Publication Number Publication Date
JPS58153422A JPS58153422A (en) 1983-09-12
JPS6347292B2 true JPS6347292B2 (en) 1988-09-21

Family

ID=12446179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57035596A Granted JPS58153422A (en) 1982-03-05 1982-03-05 Detecting circuit of error transmission

Country Status (1)

Country Link
JP (1) JPS58153422A (en)

Also Published As

Publication number Publication date
JPS58153422A (en) 1983-09-12

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