JPS634676B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit for an electronic watch that performs digital display using an electro-optical display device such as a liquid crystal display device, and in particular to a display device with a different number of display digits using one type of integrated circuit. The purpose is to make it usable.

In recent years, electronic watches that display digital information using liquid crystal display devices, in addition to displaying hours, minutes, and seconds, also display the month,
Multifunctionality is progressing, such as day and weekday display, alarm, chronograph, dual time, and switching between 12/24 hour systems. On the other hand, display devices are now capable of displaying not only numbers but also alphanumeric characters, flags, marks, and the like.

However, in the past, even if the functions of electronic watches were almost the same, when the display methods of the display devices were different, for example, in the case of a 4-digit display and a 6-digit display, each display device required a completely different integrated circuit ( (hereinafter referred to as LSI)
However, there was the inconvenience that LSIs had to be designed and manufactured individually even though their functions were the same.

The present invention has been made in view of the above points, and provides an LSI for electronic watches that can drive display devices with different display digits with one LSI for electronic watches by providing a display digit switching terminal. It is. The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is an oscillation circuit that generates a reference frequency using an externally attached crystal resonator, and 2 is an oscillation circuit that generates a reference frequency from the reference frequency.
A frequency divider circuit that obtains a Hz signal, 3 is an input gate circuit,
4 to 11 are second, minute, hour, day, month, day, alarm minute, and alarm time counters, respectively; 12 is a sending circuit that sends the output of each counter to the data line DB; and 13 is a signal sent to the data line. A decoder converts data into segment signals, 14 is a storage circuit that holds each segment signal, 15 is a drive circuit that drives the display device, and 16 is a key input to which key switches SW ₁ , SW ₂ and SW ₃ are connected. 17 is an AND-OR ROM that determines the functions of the key switches SW ₁ , SW ₂ , and SW ₃ ; 18 is a mode control circuit that specifies the mode; 19 is a timing control circuit that controls each part; 20 is for switching the display digits. This is the display digit number switching terminal provided for this purpose.

Seconds, minutes, hours, days, months counters 4, 5, 6, 7,
8 are continuously connected to each other via an input gate circuit 3, and a 1 Hz signal generated by the frequency divider circuit 2 is applied to a second counter 4 via the input gate circuit 3 and counted. Further, the day counter 9 is a heptadary counter, and like the day counter 7, the carry signal of the hour counter 6 is applied via the input gate circuit 3.
The alarm minute and alarm hour counters 10 and 11 are set with an alarm time. The input gate circuit 3 is controlled by the mode control circuit 18, and in the alarm setting and modification state, a modification signal output from the timing control circuit 19 is applied to the counter to be set or modified. The key input circuit 16 includes connected key switches SW ₁ , SW ₂ and
It consists of a chattering prevention circuit for SW ₃ , a differentiation circuit, a timer circuit for counting the closing time of the key switch, etc., and its output is applied to the AND-OR ROM 17. The AND-OR ROM 17 receives the output of the mode control circuit 18 and the signal 4/6SL of the display digit number switching terminal 20, and determines the functions of the key switches SW ₁ , SW ₂ and SW ₃ according to these conditions.
A predetermined mode is set in the mode control circuit 18. Mode control circuit 18 is AND-OR ROM 17
The input gate circuit 3 and the timing control circuit 19 are controlled depending on the output of the flip-flop. The timing control circuit 19 is applied with the frequency division output of the frequency divider circuit 2, the output of the key input circuit 16, the signal 4/6SL of the display digit number switching terminal 20, and the output of the mode control circuit 18. It generates signals and correction signals for controlling the circuit 12 and memory circuit 14, and outputs control signals for each circuit. The sending circuit 12 controlled by the timing control circuit 19 sequentially sends the count contents of the counter to be displayed to the data line DB consisting of 4 bits in a time series manner, and the sent data is sent to the decoder 13. The signal is converted into a segment signal and held in the storage circuit 14 controlled by the timing control circuit 19. This memory circuit 14 is composed of latch circuits equal to the maximum number of segments and flags of the display device, and the segment signal is held in the latch circuit designated by the output of the timing control circuit 19. The contents held in this latch circuit are applied to the display device by the drive circuit 15 and displayed.

Figures 2a and 2b are examples of display patterns of a liquid crystal display device used in the electronic watch integrated circuit shown in Figure 1. Figure 2a is a four-digit time display;
Figure b shows a six-digit time display. The days of the week are both displayed by flags, and the morning and afternoon indications are displayed in alphabets AM and PM.

In the case of the four-digit display shown in FIG. 2a, in the normal display state, the hours are displayed in the first and second digits 21 and 22, and the minutes are displayed in the third and fourth digits 23 and 24. When key switch SW ₁ is pressed, the display switches to month and day, with the month in the first and second digits 21 and 22, and the month in the third and fourth digits 2.
The day is displayed at 3 and 24, and a mark DATE indicating that the month and day are displayed is also displayed. If you press key switch SW ₁ again, the display will switch to seconds.
Seconds are displayed in the third and fourth digits 23 and 24. When key switch SW ₂ is pressed, the hour and minute display mode changes to the alarm time display mode, and the hour of the alarm time is displayed in the first and second digits 21 and 22, and the minute is displayed in the third and fourth digits 23 and 24. The mark ALM will be displayed indicating that it is alarm time. The key switch SW ₃ is a switch for entering the alarm correction mode and the time correction mode. In each correction mode, the key switch SW ₂ selects a correction element, and the key switch SW ₁ executes the correction. In correction mode, the hour and month are 1st and 2nd digits 2
1 and 22, and the minutes, seconds, and day are displayed in the third and fourth digits 23 and 24.

On the other hand, in the case of the 6-digit display shown in Figure 2b, in the normal display state, the first and second digits 25 and 26 are the hours, the third and fourth digits 27 and 28 are the minutes, and the fifth and sixth digits 29 and 30.
seconds are displayed. The seconds displayed in the fifth and sixth digits 29, 30 can indicate the day by pressing key switch _SW1 . At this time, the mark DATE indicating that the date is displayed is also displayed. In this time display mode, the key switch
When SW ₂ is pressed, the hour of the alarm time is displayed in the 1st and 2nd digits 25 and 26, the minutes are displayed in the 3rd and 4th digits 27 and 28, and the character AL indicating that the alarm time is displayed is displayed in the 5th digit. and displayed in the 6th digit 29, 30. The key switch SW ₃ is a switch that enters the alarm correction mode and the time correction mode, and in each correction mode, the key switch SW ₂ is a switch that selects a correction element, and the key switch SW ₁ is a switch that executes correction. In this correction mode, the hours are in the first and second digits 25 and 26, the minutes and month are in the third and fourth digits 27 and 28, and the seconds, day and alarm mark AL are in the fifth and sixth digits 29, 30.

In this way, the seconds, month, and day display digits and the functions of the key switch SW ₁ are different between the 4-digit display and the 6-digit display, and these are determined by the potential applied to the display digit number switching terminal 20 shown in Figure 1. It is switched depending on.

Figure 3 shows the AND-OR ROM1 shown in Figure 1.
7 and a part of the logic circuit of the mode control circuit 18.
AND-OR The AND input of the ROM 17 receives the output from the key input circuit 16, that is, the key switch SW ₁ ,
Signals SW ₁ ON, SW ₂ ON, SW ₃ ON indicating that SW ₂ or SW ₃ are closed, and signals indicating that key switches SW ₁ , SW ₂ , SW ₃ are open.
A signal indicating that a predetermined period of time has elapsed since SWoff and key switches SW ₁ , SW ₂ , and SW ₃ were opened.
TIMER is input, and outputs M ₁ , ₁ , M ₂ , ₂ , S ₁ , ₁ , S ₂ , ₂ and S ₁ +S ₂ from the mode control circuit 18 are also input. Furthermore, the switching signal 4/6SL from the display digit number switching terminal 20 and its inverted signal are input. On the other hand, the OR output is the signal MD ₁ , MD ₂ ,
MD ₃ , SD ₁ , SD ₂ and Sφ are provided,
AND of input signals marked with ○ in the AND section
Only when it is obtained, the output is output to the OR section,
The output signal marked with a circle is output from the OR section.

The mode control circuit 18 controls the display mode.
- Type flip-flops 31, 32 and T-type flip-flops 33 and D-type controlling the modification mode.
The flip-flops 31, 32, 33 are input with corresponding OR outputs MD ₁ , MD ₂ , MD ₃ , and their outputs are M ₁ , M ₂ and M ₃ ; On the other hand, the flip-flops 34 and 35 have corresponding OR outputs SD ₁ ,
SD ₂ is input, and its output is output as S ₁ and S ₂ . The signal Sφ is input to the AND gate 36 and controls the frequency-divided output φ10 from the frequency divider circuit 2, which is used as a clock for the flip-flops 31, 32, 34, and 35. flipflop 31,
The display mode determined by 32 and 33 is set as shown in Figure 9a, and when both M ₁ and M ₂ are "0", the day, hour, and minute display is in the normal display state, with 6 digits. In the case of display, when M ₃ is “0”, the day, hour, minute, and second are displayed; when M ₃ is “1”, the day,
Displays hours, minutes, and days. M ₁ is “1”, M ₂ is “0”
When , the alarm time is displayed, and _M1 is “0”,
When M ₂ is "1", the day, month, and day of the day are displayed in a 4-digit display, and when M ₁ and M ₂ are both "1", seconds are displayed in a 4-digit display. _The correction mode determined by _the flip-flops ₃₄ and 35 is as shown in _FIG . ” when M ₁ , M ₂
If both are “1”, the seconds will be corrected in 4 digits; if M ₁ and M ₂ are both “0”, the seconds will be corrected in 6 digits; if M ₁ is “0” and M ₂ is “1”, the day will be corrected. , when S ₁ is “0” and S ₂ is “1”, if M _{1 and} M ₂ are both “0”, the hour is adjusted; if M ₁ is “1” and M ₂ is “0”, it is the alarm time. Modified, M ₁ is “0” and M ₂ is “1”
In this case, the month will be corrected, and both S ₁ and S ₂ will be “1”.
When M ₁ and M ₂ are both “0”, the minute is corrected,
If _M1 is "1" _{and M2} is "0", the alarm time is adjusted by the minute, and if _M1 is "0" _{and M2} is "1", the alarm time is adjusted by the day.

A flip-flop 31 that determines this mode;
32, 33, 34, 35 are AND-OR ROM17
It is set based on the functions of key switches SW ₁ , SW ₂ and SW ₃ determined by . Key switch SW ₁ ,
The functions of SW ₂ and SW ₃ are set to a to u shown in Figure 3, and those marked with 6 are functions that only display 6 digits, those marked 4 are functions that only display 4 digits, Functions with no markings are common to 4-digit and 6-digit displays.

In FIG. 3, when a voltage is applied to the display digit number switching terminal 20 to select 6 digits, the switching signal 4/6SL becomes "1". In the normal display state, the signals M ₁ , M ₂ , M ₃ , S ₁ and S ₂ are "0", and the day, hour, minute, and second are displayed. Therefore, when key switch SW ₁ is closed, SW ₁ ON becomes "1", and the logical product is performed only in function (a).
SW ₁ ON・₁・₂・₁・₂・4/6SL=1. Therefore, as for the OR output, MD ₃ and Sφ become "1", the flip-flop 33 is set, and the output M ₃ becomes "1", so that hours, minutes, and days are displayed.
The flip-flops 31, 32, 34, and 35 continue to store "0", and the normal display state is maintained. Furthermore, when the key switch _SW1 is closed, _MD3 and Sφ become "1" again, the flip-flop 33 is inverted, and _M3 becomes "0".
The minutes and seconds will be displayed. One side switching signal 4/6SL
When set to "0" and displayed in 4 digits, if key switch SW ₁ is closed, the logical product will be displayed only in function (c).
SW ₁ ON・₁・₂・₁・₂・46=1, and MD ₂ and Sφ become “1”. As a result, the flip-flop 32 is set and the output _M2 becomes "1".
The month and day will be displayed. When key switch SW ₁ is closed in this state, logical product SW ₁ ON・₁・M ₂・₁・₂ = 1 only in function (d),
MD ₁ , MD ₂ and Sφ become "1", flip-flops 31 and 32 are set, outputs M ₁ and M ₂ become "1", and seconds are displayed. Furthermore, if the key switch SW ₁ is closed in this state, the logical product SW ₁ ON・M ₁・M ₂・₁・₂ = 1 only in function (e), and only Sφ is “1”, so the flip-flops 31, 32 is reset and returns to normal display state. Also, set the month/day display state and press the key switch.
When a certain period of time has passed after opening SW ₁ , the timer output TIMER and SWoff become “1” and function (f)
In the logical product SWoff・TIMER・₁・M ₂・
S ₁ · ₂ =1, only Sφ is output, flip-flops 31 and 32 are reset, and the normal display state is restored. On the other hand, for functions common to 4-digit display and 6-digit display, display digit number switching signal 4/6
SL and 46 are not included in the conjunction. For example, for function (b), the logical product SW ₂ ON・₁・₂・
When the key switch SW ₂ is closed by setting S ₁ and S ₂ , MD ₁ and Sφ become "1", the flip-flop 31 is set, and the normal display mode changes to the alarm time display mode.

In this way, in the AND section of the AND-OR ROM 17, the mode control circuit 1 indicates the mode at that time.
The key switch is activated depending on the logical product of the output signals of 8.
The functions of SW ₁ , SW _2, and SW ₃ are determined, and if the function is for only 4-digit display or only 6-digit display, the function is determined by incorporating the display digit number switching signal 4/6SL or 46 into the logical product. mode control circuit 1 by selecting the output signal from the OR section to have the determined function.
8, a predetermined mode is set.

As mentioned above, the display form differs depending on the 4-digit display and the 6-digit display and the mode, but a circuit for performing the display determined by the mode control circuit 18 will be shown and explained below.

FIG. 4 shows the input gate circuit shown in FIG.
1 is a detailed block diagram of second, minute, hour, day, month, day of the month, alarm minute, alarm time counters 4 to 11 and a sending circuit 12. FIG. A control gate 37 included in the input gate circuit 3 is connected to the input of each counter 4 to 11.
-43 are provided, and control gates 37-41
is the carry signal from the previous stage counter and the correction pulse SP output from the timing control circuit 19.
are input, and signals SP ₁ to _{SP 5} that further control the control gates 37 to 41 are output from the mode control circuit 18.
It is generated and applied by the input gate circuit 3 based on M ₁ , M ₂ , S ₁ , and S ₂ . On the other hand, control gates 42, 43
A correction pulse SP and signals SP ₆ and SP ₇ generated in the input gate circuit 3 are respectively applied to . The control gates 37 to 41 serve to apply a carry signal from the previous counter to the subsequent counter in modes other than the correction mode, but in the correction mode they prohibit the carry signal and apply a correction pulse SP to the subsequent counter. These operations are controlled by signals SP ₁ to SP ₅ . On the other hand, the control gates 42 and 43 are controlled by the signals SP ₆ and SP ⁷ in the alarm time correction mode, and apply a correction pulse SP to the alarm minute counter 10 or the alarm time counter 11.

The 4-bit binary output for each digit of each counter 4 to 11 is sent to the sending gate 44 that constitutes the sending circuit 12.
-58 respectively, and the outputs of the sending gates 44-58 are data lines DB1-4 consisting of 4 bits.
connected to. Further, transmission gates 59, 60, and 61 are connected to the data lines DB1 to DB4.
The sending gate 59 has an alarm mark signal ALS for lighting up the alarm mark when an alarm is set, an ALM signal for displaying the characters "ALM" when the alarm time is displayed in the case of a 4-digit display, and an AM and AM signal from the hour counter 6. AM and PM signals indicating the afternoon and a DATE signal indicating the day are applied.
On the other hand, the sending gates 60 and 61 have pattern generators 62 and 63 for displaying "L" in the 6th digit and "A" in the 5th digit of the display device when the alarm time is displayed in a 6-digit display. is connected.

Control signals CT1 to CT18 are applied from the timing control circuit 19 to these sending gates 44 to 61, respectively, to control the opening and closing of the gates, and when the gates are opened, the binary output of the counter is sent to the data lines DB1 to DB4. . data line DB
1 to 4 are applied to the input of the decoder 13.

FIG. 5 is a block diagram of the decoder 13 and memory circuit 14 shown in FIG. Data lines DB1 to DB4 are inputted to the decoder 13, which converts the 4-bit binary code into seven segment signals a to g, as is well known. Further, a control line DB5 is applied to the decoder 13. This control line DB5 is a signal that becomes "1" when blinking the element to be corrected or when erasing a predetermined display in the correction mode, and during the period when the control line DB5 is "1", the data lines DB1 to DB4 are Even if data is sent out, all segment signals a to g become "0".

The memory circuit 13 includes a latch circuit 64 corresponding to seven flags indicating the day of the week, a latch circuit 65 corresponding to the first digit segments 1a to 1g, and a second latch circuit 64 corresponding to the seven flags indicating the day of the week.
A latch circuit 66 corresponding to digit segments 2a to 2g, a latch circuit 67 corresponding to third digit segments 3a to 3g, and a fourth digit segment 4a to 4g.
A latch circuit 68 corresponding to 4g, a latch circuit 69 corresponding to segments 5a to 5g of the fifth digit,
It consists of a latch circuit 70 corresponding to the sixth digit segments 6a to 6g, and a latch circuit 71 corresponding to the letters AM, PM, DATE, ALM and the ALM mark. In addition, each latch circuit 64 to 71
The outputs a to g of the corresponding decoders 13 are applied to the latch inputs L of the latch circuits 6 and 6.
Predetermined control signals Lφ ₁ to Lφ ₈ are applied to clock terminals φ 4 to 71, respectively. The control signals Lφ ₁ to Lφ ₈ are generated by the timing control circuit 19 and are pulses that sequentially become “1” from Lφ ₁ to Lφ ₈ at predetermined timings. In each latch circuit 64 to 71, the control signal Lφ ₁ to Lφ ₈ applied to the clock terminal φ is “1”.
It stores and holds the signals a to g output from the decoder 13 when the control signal Lφ ₁
~Lφ ₂ ...Lφ ₈ order, that is, latch circuits 70, 69,
Memory retention is repeated in the order of 68, 67, 66, 65, 71, and 64, and the stored contents are always output from output Q.

FIG. 6 shows the control signals Lφ ₁ to Lφ ₈ shown in FIG.
FIG. 2 is a partial circuit diagram of a timing control circuit 19 that creates a timing control circuit 19. First, before generating the control signals Lφ ₁ to Lφ ₈ , the timing signals T ₁ to T ₃ and T4A, T4B are divided into the frequency dividing circuit 2.
NOR gate 72 using the divided output φ ₈ ~ _{φ 10} from
~Made according to 76. Output T ₁ of NOR gate 72
is the logical product ₉ · ₁₀ , the output T ₂ of the NOR gate 73 is the logical product _φ9 · ₁₀ , the output T ₃ of the NOR gate 74 is the logical product ₉ · _φ10 , and the output T4A of the NOR gate 75 is the logical product ₈ · _φ9・φ ₁₀ , output T4B of NOR gate 76
are timing signals that result in the logical products φ ₈ , φ ₉ , and φ ₁₀ . These timing signals T ₁ , T ₂ , T ₃ , T4A,
T4B each has a predetermined voltage via an inverter 77.
Applied to NOR gates 78-85. Also NOR
The gates 78, 80, 82 are provided with a timing signal T ₁
~ _φ8 , which is half the pulse width of _T3 , is applied,
₈ is applied to NOR gates 79, 81, and 83. That is, timing signals T ₁ , T ₂ , and T ₃ are distributed to NOR gates 78 and 79, NOR gates 80 and 81, and NOR gates 82 and 83, respectively, according to φ ₈ . On the other hand, the frequency divided output φ ₅ from the frequency dividing circuit 2 is applied to the clock terminal φ, and the L input of a flip-flop 86 receives the frequency divided outputs φ ₆ and φ ₇ as inputs.
A latch clock pulse LCL is generated by applying the output of the gate 87 and further using a NOR gate 88 having the L input and the output as inputs. This pulse LCL
is connected to NAND gate 78 through inverter 89
85 is input.

FIG. 7 is a timing diagram of the circuit shown in FIG. Frequency division output φ ₅ to _{φ 10} of frequency divider circuit 2 is sequentially 1/2
This is a pulse whose frequency is divided by 1. timing signal
T ₁ , T ₂ , T ₃ , T4A, and T4B are signals in which pulses are sequentially output in time series during one period of the divided output φ ₁₀ , and the pulse widths of the timing signals T ₁ , T ₂ , and T ₃ are It is the same as one period of the frequency divided output _φ8 , while the timing signals T4A and T4B are the timing signals
The pulse width is 1/2 of the pulse width of T ₁ , T ₂ , and T ₃ . The latch clock LCL has a period equal to the divided output φ ₇ and a pulse width equal to the divided output _{φ 5} .
pulses are being output. Control signal Lφ ₁ ~
_Lφ8 is the latch clock LCL and the timing signal T1 _~
Latch clock sequentially in chronological order in synchronization with T4B
A pulse equal to the pulse width of LCL is output, and during the pulse period of timing signal T ₁ , control signal Lφ ₁ and
Lφ ₂ , control signals Lφ ₃ and Lφ ₄ during the pulse period of timing signal T ₂ , control signals Lφ ₅ and Lφ ₆ during the pulse period of timing signal T ₃ , control signal Lφ ₇ during the pulse period of timing signal T4A, timing signal T
The control signal _Lφ8 is output during the 4B pulse period. That is, during the pulse period of the timing signal _T1 , the contents displayed in the sixth and fifth digits of the display device are stored in the latch circuits 70 and 69 shown in _FIG . ,
The content displayed in the third digit is latch circuit 68, 67
In the pulse period of the timing signal _T3 , the second,
The content displayed in the first digit is latch circuit 66, 65
In addition, the display contents of marks and characters are stored in the latch circuit 71 during the pulse period of the timing signal T4A, and the display contents of the day of the week are stored in the latch circuit 64 during the pulse period of the timing signal T4B.
Therefore, each timing signal T ₁ , T ₂ , T ₃ , T4A,
By transmitting the counted contents of the counter shown in FIG. 4 or various data lines DB1 to DB4 in synchronization with T4B, the display is displayed at a predetermined location. The data is sent by the control signal CT1 which controls the sending gates 44 to 58 as described above.
~This control signal is performed by CT18.
CT1 to CT18 are timing signals T ₁ , T ₂ , T ₃ ,
In addition, the mode control circuit 18 is synchronized with T4A and T4B.
It is controlled by the outputs M ₁ , M ₂ , S ₁ , S ₂ and the display digit number switching signal 4/6SL.

FIG. 8 is a partial circuit diagram of the timing control circuit 19 shown in FIG. 1, and shows the control signals CT1 to CT1.
This is a circuit that creates 8. First, control signals CT1 to CT1
In order to make 8, second sending timing signal sec, minute sending timing signal min, hour sending timing signal
hour, day transmission timing signal day, month transmission timing signal month, day transmission timing signal week,
Mark sending timing signal mark, “AL” character sending timing signal AL, alarm minute sending timing signal ALmin, alarm sending timing signal
ALhour with timing signals T ₁ , T ₂ , T ₃ , T4A,
T4B and the outputs of the mode control circuit 18 M ₁ , M ₂ ,
M ₃ , S ₁ , S ₂ and their inverted signals and display digit number switching signals 4/6SL and 46 are connected to the gate circuit 9
Create according to 0. The gate circuit 90 receives the output contents of the mode control circuit 18 and the display digit number switching signal 4/
Timing signals T ₁ , T ₂ , T ₃ , T4 depending on 6SL
This is to select which transmission timing signal A and T4B should be output. The sending timing signal (week and
(excluding mark) is the sixth
The timing signals T ₁ , T ₂ , and T ₃ shown in the figure are switched and output at the same timing by a frequency division output φ ₈ that divides each of them into 1/2. These outputs are control signals CT1 to CT10 and CT13 to CT18. CT11 and CT12 are timing signals T4A.
and T4B are used, so the day sending timing signal week and the mark sending timing signal mark are output as they are as CT11 and CT12. Further, the gate circuit 90 outputs a control line DB5 that controls the decoder 13 and causes the display to blink and turn off.

Next, the operation and function of the gate circuit 90 will be explained with reference to FIGS. 9a and 9b. FIG. 9a shows the display contents in the states of the outputs M ₁ , M ₂ , and M ₃ of the mode control circuit 18, and the timing signal T in each case of 4-digit display and 6-digit display to obtain the display contents. ₁ , _T2 ,
Control signals CT1 to 1 at T ₃ , T4A, and T4B
This shows how to output 8. Further, FIG. 9b shows the functions of the mode control circuit 18 in the states of outputs S ₁ and S ₂ .

When M ₁ , M ₂ and M ₃ are “0”, the AND gate 94 to which the timing signal T ₁ is applied becomes logical product M ₁ , M ₂・M ₃・T ₁ = 1, so the timing of T ₁ , control signals CT1 and CT2 are output, and AND gate 9 to which ₁ and ₂ are applied
In 5 and 96, the AND of each timing signal T ₂ and T ₃ becomes "1", and CT 3 and 4 become "1" at the timing of T ₂ and CT 4 at the timing of T ₃ .
CT5 and CT6 are output. However, in the case of a 4-digit display, the output terminals that drive the 5th and 6th digits are not connected to the display device, so the segment drive signals for the 5th and 6th digits are sent from the output terminals at the timing of _T1 . Although it is not displayed even if it is output, there is a timing signal _T1 to prevent unnecessary output signals from being output, and 46 indicating that it is a 4-digit display.
The AND gate 97 performs a logical product with the AND gate 97, and depending on the output, the control line DB5 is opened by opening the gate 98 at the timing of _T1 in all modes.
Set to “1”. As DB5 becomes "1", the segment outputs a to g of the decoder 13 shown in FIG. ” is memorized. Also take the logical product of ₁・T4B and
CT11 at timing T4B due to gate 99
is output, and CT12 is output at the timing of T4A. Therefore, the control signals CT1, CT2, CT3,
The ones digit and tens digit of the second counter 4, the ones digit and ten digit of the minute counter 5, and the ones digit of the hour counter 6 are shown in the timing order of CT4, CT5, CT6, CT12, and CT11 in FIG. , tens mark signals and the contents of the day counter 9 are sent to data lines DB1 to DB4, and are sent to latch circuits 70, 69, 68, 67, 66, respectively via the decoder 13 shown in FIG.
By being stored in 65, 71, and 64, normal display, that is, time display is performed.

On the other hand, in the case of a 6-digit display, if M ₁ and M ₂ are "0" and M ₃ is "1", the timing signal T ₁
Logical product of AND gate 94 ₁・₂・₃・T ₁ = 0
Therefore, CT1 and 2 are no longer output at the timing of T ₁ , but since the logical product ₁・₂・M ₃・T ₁ = 1 in the AND gate 100, CT7 and 8 are output at the timing of T ₁ . be done. Therefore, the date is displayed in the 5th and 6th digits, and the mark
A signal indicating DATE is sent out from the sending gate 59 shown in FIG. 4 at timing T4A.

When M ₁ becomes “1” and M ₂ becomes “0” mode,
AND gate 10 with logical product M ₁・₂・T ₁ = 1
CT13, 14 at the timing of _T1 depending on the output of
_{However , CT15 ,}
16, CT1 at the timing of T ₃ depending on the output of the AND gate 103 where the logical product M ₁・₂・T ₃ = 1.
7 and 18 are output, and then at the timing of T4A
CT12 is output, but at the timing of T4B
Logical product ₁・T4B=0 in AND gate 99
Therefore, CT11 is not output. On the other hand, since T4B·M ₁ =1 in the AND gate 104, the gate 98 is opened at the timing of T4B, and the control line DB5 becomes "1". Therefore, the 1st and 2nd digits display the alarm time, and the 3rd and 4th digits display the alarm minute. In the case of a 4-digit display, the ALM character is displayed, and in the case of a 6-digit display, the 5th and 6th digits display "AL". ” will be displayed, but the day of the week will no longer be displayed.

Next, in the mode where M ₁ is “0” and M ₂ is “1”,
The AND gate 105 receives the timing signal T ₂ when the display is 4 digits, and the timing signal T ₁ when the display is 6 digits.
is switched and applied according to the display digit number switching signal 46, while a timing signal T ₃ is applied to the AND gate 106 when a 4-digit display is performed, and a timing signal T ₂ is applied when a 6-digit display is performed. Therefore, in the case of a 4-digit display, CT7 and CT8 are output at the timing _T2 when the AND gate 105 becomes AND ₁・M ₂・T ₂ = 1, and the AND gate 106 outputs AND ₁・M Timings CT9 and CT10 of _T3 where ₂ · _T3 =1 are output. When displaying 6 digits, AND gate 105 performs logical product ₁ , M ₂ ,
CT7 and CT8 are output at the timing of T1 when _T1 = ₁ , and the AND gate 106 outputs the logical product ₁ .
CT9, 1 at the timing of T ₂ when M ₂・T ₂ = 1
0 is output. Also, both 4-digit and 6-digit display are T4
CT11 is output at timing B, and CT12 is output at timing T4B. Therefore, in the case of a 4-digit display, the month is displayed in the 1st and 2nd digits, and the day is displayed in the 3rd and 4th digits, and in the case of a 6-digit display, the month is displayed in the 3rd and 4th digits, and the day is displayed in the 5th and 6th digits. The day is displayed. In addition, in the case of 6-digit display
At the timing of T ₃ , the AND gate 107 has a logical product of ₁ , M ₂ , T ₃ , and 4/6 SL = 1, so the gate 98 is opened and "1" is output to the control line DB5, and the first and second digits are is not displayed.

If M ₁ is "1" and M ₂ is "1", it is a seconds display in a 4-digit display, and at the timing of T ₂ , the AND gate 108 performs the logical product M ₁・M ₂・T ₂ = 1 Therefore, CT1 and CT2 are output. Also, at the timing of T ₃ , the AND gate 109 performs the logical product T ₃・
M ₁ ·M ₂ =1, the gate 98 is opened, and "1" is output to the control line DB5. Therefore, the third and fourth
Seconds are displayed in the digits.

AND gates 110-117 are connected to gate 1 in order to blink the element being modified in the modification state.
18 to 125 to output "1" to the control line DB5 at regular intervals in synchronization with the timing of displaying the element to be corrected.
A frequency-divided output φ15 of 1 Hz is applied to the AND gates 110 to 117, which determines the blinking period.

When the outputs S ₁ and S ₂ of the mode control circuit 18 are both “0”, it is a non-corrected state, and the AND gate 1
All outputs from 10 to 117 are "0". When S ₁ becomes “1” and S ₂ becomes “0”, it is second correction or day of day correction, so S ₁ and ₂ are AND gates 110 and 115.
is applied to Furthermore, _M2 is applied to the AND gate 115 so that it is output only when the day of the week is being corrected.
When S ₁ is “0” and S ₂ is “1”, it is hour correction or month correction, so AND gates 112, 114, 11
₁ and _S2 are applied to 7, and when _S1 and _S2 are "1", it is minute correction or day correction, so AND gate 11
S ₁ and S ₂ are applied to 1,113,116. Accordingly, the display blinks by outputting "1" to the control line DB5 at a constant cycle in synchronization with the sending timing signal for displaying the element to be corrected.

Therefore, based on the timing signals T ₁ , T ₂ , T ₃ , T4A, and Q4B generated by the circuit shown in FIG. 6, the gate circuit 90 in FIG. Display digit switching signal 4/6SL
The number of displayed digits can be switched by outputting control signals CT1 to CT18 in synchronization with predetermined timing signals T ₁ , T ₂ , T ₃ , T4A, and T4B.

As described above, according to the present invention, a terminal for switching the number of display digits is provided, and depending on whether this terminal is externally connected to the ground level or power supply level by bonding or the like, the function of the key switch can be changed to AND-OR ROM.
By further switching the display timing in the timing control circuit,
The number of display digits and display format are switched.
In addition, if multiple display digit number switching terminals are provided, 3
It is also possible to switch the number of digits beyond the type. Therefore 1
An electronic clock with 4 digit display and 6 electronic clock chips.
Since it can be commonly used in many types of electronic watches, such as electronic watches with digit display, it has the advantage of reducing the design and manufacturing costs of integrated circuits for electronic watches.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2a and b are display pattern diagrams of a liquid crystal display device, FIG. 3 is a partial circuit diagram shown in FIG. 1, and FIG. Figure 1 is a detailed block diagram of the input gate circuit, each counter, and the sending circuit shown in Figure 1. Figure 5 is a detailed block diagram of the decoder and storage circuit shown in Figure 1.
The figure is a partial circuit diagram of the timing control circuit shown in FIG. 1, FIG. 7 is a timing diagram of the circuit shown in FIG. 6, FIG. 8 is a partial circuit diagram of the timing control circuit, and FIG. 9 is a partial circuit diagram of the timing control circuit shown in FIG. a and b are tables showing each mode. Explanation of main figure numbers, 1...Oscillation circuit, 2...Divider circuit, 3...Input gate circuit, 4-11...Seconds,
Minute, hour, day, month, day, alarm minute, alarm time counters, 12... Sending circuit, 13... Decoder, 14... Memory circuit, 15... Drive circuit, 16
...Key input circuit, 17...AND-OR ROM,
18...Mode control circuit, 19...Timing control circuit, 20...Display digit number switching terminal.

Claims (1)

[Claims] 1. A frequency dividing circuit that divides the reference frequency from the oscillation circuit, a time counting counter that counts the second signal generated by the frequency dividing circuit, and the count contents of the time counting counter in chronological order. A sending circuit and a data line for sending data, a decoder for converting the data sent to the data line into a segment signal, and a decoder for holding data corresponding to a display element of a display device connected to the outside. A memory circuit for storing outputs, a key input circuit to which a key switch is connected, a mode control circuit for setting modes such as display and time correction, and a mode control circuit for setting modes such as display and time correction, based on the output of the key input circuit and the output of the mode control circuit a logic gate circuit that outputs a mode setting signal to the mode control circuit; a timing control circuit that generates a timing signal that controls the sending circuit and the storage circuit based on the output of the mode control circuit;
and a display digit number switching terminal for switching the functions of the logic gate circuit and the timing control circuit, and a signal applied to the display digit number switching terminal controls the timing of the sending circuit and the storage circuit according to the display digit number. An integrated circuit for an electronic watch is characterized in that it can drive a display device with a different number of display digits.