JPS6346090A - Television receiver - Google Patents

Abstract

PURPOSE:To improve the accuracy of detection of movement by using information of speed ot movement for detecting information of movement in addition to detection in frequency domain, and making scanning line interpolation suitable for the property of a picture image. CONSTITUTION:Video signals of base band obtained from an video detector circuit or video signals already made to base band enter an A/D converter and a synchronizing signal separator circuit. In a YC,L,YH separator circuit, both existing television signals, compatible high precision television signals are separated into a luminance signal low band component YL adapted to movement, a chrominance signal C and a high precision signals YH. In such a case, the presence of movement is detected by a movement detector circuit. In an interpolating circuit, scanning lines omitted in the field by interlace scanning in existing television system are interpolated by interpolation signals YTp, ITp, QTp and displayed in a form of 60-frame successive scanning.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a television receiver, and in particular, the present invention relates to a television receiver.
The present invention relates to a television receiver suitable for receiving signals of C television system and compatible high-definition preview system.

[Conventional technology]

The signal bandwidth, color signal superimposition, etc. are exactly the same as the current television system, and as a new television system that transmits and receives images with higher resolution than the current television system, it is completely identical to the current television standard. There is, for example, Japanese Patent Application No. 58-044238, which is related to a high-definition television system that is compatible with the above. The above system and the current television system both reproduce high quality images, for example,
Examples include those described in No.-209942.

[Problem that the invention seeks to solve]

In the television receiver described above (Japanese Patent Application No. 60-209942), the low frequency component Y of the luminance signal. .

(4.2 MHz or less), color signal C1 and luminance signal high frequency component Y. (components above 4.2 MHz) are frequency shifted to produce low frequency components Y. '(4,2MHz), motion-adaptive Y t, , C
, Y ) (' Signal separation and image display using 60 frames and sequential scanning by scanning line interpolation are performed to achieve high image quality and high definition.

However, since the signal processing described above is performed to adapt to motion, the detection accuracy of motion information is low, so there are problems such as failure to detect certain kinds of motion, resulting in deterioration of image quality. Ta.

The purpose of the present invention is to improve the accuracy of motion detection,
The object of the present invention is to provide a television receiver that can receive high-quality images of signals of the compatible television system described above as well as signals of the current television system.

[Means for solving problems]

The above purpose is to detect motion information in the frequency domain, which is well known in the past, such as by detecting motion using interframe difference signals, and to use motion speed information in combination to improve detection accuracy. This can be achieved by, for example, performing scan line interpolation appropriate to the nature of the image.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows a block configuration of an embodiment of a television receiver according to the present invention. In the figure, the area surrounded by dotted lines is the signal processing unit that converts broadcast waves into baseband video signals, such as a high frequency circuit (tuner), video intermediate frequency amplification circuit, and video detection circuit, which is conventionally implemented optically. (hereinafter,
Since it can be realized with a configuration similar to that of a current television receiver (abbreviated as "current"), the explanation will be omitted.

On the other hand, the area surrounded by a solid line is the configuration of the main signal processing section of the present invention. The baseband video signal obtained from the video detection circuit, or the video signal already in baseband indicated by the dotted line, enters the A/D converter and the synchronization signal separation circuit.

In the synchronization signal separation circuit, the color subcarrier fb (-, +horizontal synchronization signal HD, vertical synchronization signal VD,
In addition, clocks such as 4f+, +c, and 8f+qc are extracted. Furthermore, the control signal generation circuit generates signals necessary for each block based on the nine various signals obtained from the synchronization signal separation circuit.

The A/Dr converter samples the signal at a sampling frequency of 4fqc, for example, and converts it into a digital signal. In this case,
Color difference signal 1. Demodulation of the color signal C can be easily realized by performing sampling with a sampling phase corresponding to the Q axis.

Next, the Y, , C, Y)l' separation circuit separates the luminance signal into a low frequency component, a color signal C1, and a high-definition signal Y8'. In this case, the presence or absence of movement is determined in the motion detection circuit. The separated high-definition signal Yo' is demodulated into the original luminance signal high-frequency component Y) (by the demodulation circuit.Then, it is added to Y11 times the signal delayed by the demodulation circuit in the delay circuit to produce a wide-range luminance signal. On the other hand, the color signal C is demodulated into, for example, a color difference signal 1.Q by a demodulation circuit.

Next, the interpolation circuit generates interpolation signals YT, p, ■□, for scanning lines missing in the field due to interlaced scanning in the current television system.

Interpolate using QTP. and Y, I, Q signals and interpolated signal Y. R, G, B, and R, p by matrix operation for pIITPIQTP.

Convert to G, P, B, signals. Then, in the time axis conversion circuit, the scanning frequency is converted into a progressive scanning signal with 525 scanning lines and 60 frames, twice that of current televisions. These signals are converted to analog R' in the D/A converter.
, G', B' times signal conversion and display in 6o frames with sequential scanning.

On the other hand, the deflection circuit has 525 trees and 60 frames.

Generates various signals necessary for sequential scanning display.

Hereinafter, the configuration of each of the above blocks will be explained in detail using an example. In addition, an A/D conversion section, a synchronization signal separation circuit, a control signal generation circuit 9, a demodulation circuit for the Buddhist monk code C, an RGB conversion circuit,
Regarding the time axis conversion circuit, D/A conversion section, and deflection circuit,
Since the structure is the same as that described in the above-mentioned Japanese Patent Application No. 60-209942, the explanation will be omitted.

First, an example of the Y,...,C,Y,' separation circuit and motion detection circuit will be explained.To make it easier to understand, first, in Fig. The phase relationship of the color signal C1, high-definition signal Y8', etc. in the time and vertical domain of the high-definition television system will be explained.

In FIG. 2(c), the circles correspond to scanning lines.

Both current television systems and compatible high-definition television systems use interlaced scanning for transmission, so scanning lines are alternately interpolated for each field. Now, in the current television system, the phase of the carrier color signal C is inverted for each scanning line and each frame.
In addition, points of the same phase have a relationship (realization of connecting 0's) that increases as shown in the figure for each field.

On the other hand, even in compatible high-definition television systems, the relationship between carrier color signals C is exactly the same as in current televisions. Furthermore, a high-definition signal Y. The phase of ' is inverted for each scanning line and frame, and the points of the same phase are multiplexed in such a manner that they fall for each field.

Therefore, the signal of the scanning line Xo in the figure is y, , +c+
y, l', then at the points X one scanning line before, X4 after one scanning line, and X-5° one frame before 5. X5□5 after one frame, Y T, -C- Y,' becomes.

Also, X-26□ before and after 262 scanning lines.

Yl at X26°, +C-Y)T', Y at X 2 R31X 2 R3 before and after 263 scanning lines,...
-C+ Y )('. Also, X- two frames before
At 1o5o, it becomes y,,+c+yH'. Therefore, by calculating the signal of the scanning line of Xo and the signal of the scanning line before or after this scanning line, Y, -, C, Y)
,' are separated. In addition, Fig. 2 (a) and (b)
denote the horizontal frequency characteristics of the signals of the current television system and the compatible television system, respectively.

FIG. 3 shows Y, 8. The configuration of an embodiment of the C, Y,' separation circuit is shown. 262 line delay circuit 1, 1 line delay circuit 2.261 line delay circuit 3.525 line delay circuit 4
By the combination of

XI or X −1(X +

Xi generates signals for Xo (scanning lines before and after i scanning lines). Note that these delay circuits can be easily constructed using, for example, RAM (random access memory), and therefore their explanation will be omitted.

By the combination of Xo, X□, ,X, color signals and high-definition information are separated as described below.

First, xn, and X5°5. The signal of the scanning line X-5□5 is processed by the arithmetic circuit 5 as 1/2Xo-1/4 (
XR25+X-5°5) is performed, and the C&YH' signal components are extracted as signal a by so-called interframe separation. For this signal and the signals S and C delayed by the 262-line delay circuit 1, one arithmetic circuit 5 generates a signal Y8' by calculating 1/2b-1/4(a+c).

Moreover, in the other arithmetic circuit 5, 1/2b+1/4(a+c
), the signal CFM is generated.

Next, for the scanning line signals of Xo and X2R31X-2R3, the calculation circuit 5 calculates 1/2xn-1/4
The calculation (X2 RA+X-2p q) is performed to extract the signal a' by so-called field separation. This signal and the signal b't delayed by the 262-line delay circuit l
c', the arithmetic circuit 5 calculates 1/2 b' +
1/4 (a' + c')? By calculation, signal C □. generate.

Furthermore, the arithmetic circuit 5 calculates 1/2Xn 1/4(X++X
+), the signal C0 due to the so-called line-to-line separation
, is extracted.

Furthermore, with respect to
Extract as B.

The selection circuit 8 normally outputs the CL signal, but when a high vertical frequency component is detected by the vertical edge detection circuit 7, the signal OR is selected to separate color signals with low cross luminance. Realize. Note that the vertical edge detection circuit 7 performs an addition operation with the signal C0 and a signal obtained by delaying this signal by one line, and when the absolute value of the operation result exceeds a threshold value ΔH, it is detected as a component with a high vertical frequency, that is, a vertical edge detection circuit 7. Detected as an edge.

At this time, for a pixel detected as a vertical edge, neighboring pixels (for example, several pixels before and after) are also processed as pixels that include a vertical edge, or appropriate weighting is applied to CL and OR. It is desirable to reduce the occurrence of deterioration caused by switching, such as by continuously switching from C1 to CR.

The output signal of the selection circuit 8 is outputted by the delay circuit 9 to CF M
* CF I-, l') and generates signals C1 and □NF.

CC Yu9. C Yu1. T-)+C1, the TNF signal is converted into a motion coefficient by a multiplication circuit 10, 2. are weighted, and these results are added in an arithmetic circuit 5 to produce a signal c' (i.e., klcFM, 2CF 1. y
), k 3CL 7 N y). This signal and the signal C" passed through the BPF 6 are sent to the selection circuit 8 to
The T signal selects the C' signal for a still image and the C'' signal for a moving image. Then, the output of the selection circuit 8 of i becomes the separated color signal C. 281
0 is 1. For example, this can be easily realized using a table lookup method using ROM (read only memory).

On the other hand, from the separated Y8' signal, the BPF 6 extracts horizontal components of 2 to 4.2 MHz, and the multiplication circuit 10 weights the motion coefficients by kY'. Signal Y. '.

In addition, the signal on the X-2R□ scanning line is subjected to delay adjustment with the C, Y, `` signal by the delay circuit 9, and separated by subtracting the C, Y, `` signal from this signal in the arithmetic circuit 5. A low-frequency component Y of the luminance signal is generated.

Note that the motion coefficients, 3*kv+ky', and the BPCT signal are generated by the motion detection circuit 11 described below.

FIG. 4 shows Y14. 1 shows an embodiment of a motion detection circuit for C, Y,' signal separation.

First, detection of motion information will be explained.

Here, the following three types of motion information in the frequency domain are used.

First, the arithmetic circuit 5 performs the calculation of Xo-X-5°5 on the signals of the scanning lines Xn, XF, □5, and the LP
A signal in the 0 to 2 MHz band is extracted by F12. This signal is converted into an absolute value and quantized by the absolute value circuit 13 to generate motion information FMDI. An example of the characteristics of this absolute value circuit 13 is shown in FIG. 5(a).

This circuit can be easily constructed using a ROM or the like. That is, the input signal is made to correspond to the address of the ROM,
It is sufficient to output the output signal corresponding to the input signal as, for example, a 4-bit signal by table lookup).

Note that the FMDI motion information is a horizontal frequency μ.

In the three-dimensional frequency domain of vertical frequency and 9 temporal frequency f,
The shaded area shown in FIG. 5(b)(1) is detected as movement.

Next・X2 R31X2 B 2+ X 2 R2・
From the signal of the scanning line of X-26, , the arithmetic circuit 5
3-X-262+X262-X-263 is calculated, and the absolute value circuit 13 generates motion information FMD2. This motion information detects the diagonally shaded area shown in FIG. 5(b)(2) as motion.

Furthermore, XFI s 51 X-! 12 FIT Xn
For the scanning line signal of +X-1°5o, the arithmetic circuit 5 calculates X rs 26 X -Fl 2 FI
After calculating IXn-x and o50 and performing absolute value conversion and quantization in the absolute value circuit 13, the maximum value selection circuit 14 selects the one with the larger absolute value to generate motion information FMD3. . This information is shown in Figure 5(b)(3)
The shaded area shown in is detected as movement. Note that the same figure also shows the spectra of the C signal and 'y)V' signal in the still image.

Among the three types of motion information mentioned above, FMD I.

FMD2 can be used for certain types of images, even if they are still images.
Movement information may be generated. For example, in an image containing a C signal with a high vertical frequency component or a YM' signal, FMD2 is used, a C signal with a horizontal frequency μ of around 2 MHz, and a YM' signal.
In an image containing an H' signal, motion information is generated in FMDI. Therefore, even if it is a still image, FMDI, FM
D2 may erroneously detect motion. Therefore, large-area static and motion determination described below is used in conjunction with this method to prevent this type of false detection.

First, the large area static motion determination circuit 15
For example, in a large area of several tens of pixels, a determination is made as to whether it is a static 1F or a moving image. As a result, if it is determined that the motor is stationary, the arithmetic circuit 5 performs an addition operation on FMD1 and FMD2. On the other hand, if it is determined that it is a moving image, the arithmetic circuit 5 performs an addition operation of FMD 3, FMDl, and FMD2.

As described above, since the motion information of FMD1 and FMD2 is used only when moving images, the above-mentioned false detection can be prevented.

The reason for determining static motion in a large area is that FMD
This is to prevent the signal No. 3 from having a zero point at the time frequency f''15 Hz, which may cause detection failure for certain types of movement.

Next, an example of the configuration of the large-area static-motion determination circuit 15 is shown in FIG. The signal of the FMD 3 is converted by a threshold circuit 25 into a binary signal of 1 if it exceeds the threshold value ΔTH, and 0 otherwise. The measuring circuit 26 measures the number of 1's for the signal A obtained in this manner within a measurement period of, for example, 488 pixels, and this is determined to be a specific value (for example, 3
), a signal corresponding to the signal port shown in the figure is output, such as 1 for a moving image area, and 0 for a still image area when it is less than a specific value. Then, the area enlargement circuit 27 enlarges the moving image area by changing the still image area sandwiched between the moving image areas to a moving image area, and performs still IF and moving image judgment using a large area area as shown in signal C. Create a signal.

Three types of motion information FMD1 to FMD3 as described above
The signal FMI obtained from 261 line delay circuit 3.
and 1-line delay circuit 2, spatial smoothing is performed in the smoothing circuit 16, and the signal CV
Generate v. FIG. 7 shows an embodiment of the smoothing circuit 16. The output signals α, β, and γ of the one-line delay circuit are weighted by 1/2 and 1.1/2, respectively, in the multiplier circuit 1o, and then added and calculated in the arithmetic circuit 5 to perform vertical smoothing. . This signal is transmitted to the 1-pixel delay circuit 2.
8, and each delayed signal is multiplied by 1/4 by a multiplier circuit 10.
Weighting is performed by 1/2, 1.1/2.1/4, and addition is performed in an arithmetic circuit 5 to generate a signal Cw that is also smoothed in the horizontal direction.

The C weight generation circuit 17 generates signals, for example, as shown in FIG.
b) A motion coefficient of .about.3 and a BPCT signal are generated. This function is shown in the same figure (c
), it can be easily realized using, for example, a ROM.

This concludes the explanation of the detection of motion information for the C signal.
Next, return to Figure 4 and select Y. Detection of motion information for signals will be explained.

For the Yo' signal, velocity information is also used to provide motion information. Therefore, X(
7F polarity quantization circuit 1 for the 1-X-4n5n signal
8. In the negative bar quantization step m19, 0.1 binarization is performed with the characteristics shown in FIG.

With this operation, the 1 region of the binarized signal is
Since this corresponds to an area that moves during the period of and X-1o5o, that is, two frames, the speed can be detected depending on the length of this area. Therefore, line 1 measurement circuit 2
0, the signal RLI becomes 1 when there are four or more 1s in a row, and 0 when there are less than 4 1s in a row, and 6
A signal RL2 is generated which becomes 1 when there are more than 1 in succession, and becomes 0 when less than that. As a result, the RLI signal corresponds to detecting a movement at a speed of 4 pixels or more between two frames, and the RL2 signal corresponds to detecting a movement at a speed of 6 pixels or more.

An OR circuit 21 performs an OR operation on the RLI and RL2 signals. The binarization circuit 22 binarizes the FMD3° FMD2 signal into 1 when it exceeds a specific value ΔT', and 0 when it is less than that. However, when the RLI' and RL2' signals are O, that is, when the motor is stationary or moving at an extremely slow speed, the output is set to O. This output signal is subjected to an OR operation in an OR circuit 21, and a speed coefficient generation circuit 23 generates a speed coefficient eMV according to the line (2). An example of this characteristic is shown in FIG.

The velocity coefficient MV is delayed by a 261-line delay circuit 3 and a 1-line near-value circuit 2, smoothed in the horizontal and vertical directions by a smoothing circuit 16 (configuration similar to that in FIG. 7), and is converted into a signal YH.
Generate w.

The weight generation circuit 24 generates motion coefficients f(kY, kY') for the high-definition signal ¥8' in response to YHw. An example of the characteristics of these kY, kY' is shown in FIG. , this can be easily realized using a ROM or the like.

Note that the mode determination circuit 29 identifies whether it is a current television signal or a compatible high-definition television signal using, for example, phase information of subcarrier μ0 corresponding to the high-definition signal. In the case of 0, the coefficient kY of the 711 weight generation circuit 24 is always set to 0.

With the above-mentioned functions, it can be used for both current television signals and compatible high-definition television signals.
It is possible to realize y, ..., c, y, □' times signal separation that is adaptive to motion.

This completes the explanation of the YL and C2YH' separation, and then the demodulation circuit for the Y)(' signal will be explained.

FIG. 12 shows an embodiment of this demodulation circuit.

The YH' signal is passed through the multiplication circuit 10 to μ. Based on the subcarrier phase ψ regenerated at a 4fFIc clock cycle by the phase regeneration circuit 31, multiplication by cos(p) is performed to perform synchronous detection. Note that this circuit can be easily realized using, for example, a ROM. Furthermore, in the polarity control circuit 30,
For example, in the case of an even field, the polarity is reversed. This is μ. The phase reproduced by the phase reproducing circuit 31 has a relationship in which points of the same phase rise in each field, similar to the color side story transmission wave fsc, so that the Y8' signal which falls in each field as shown in FIG. This is to match the phase relationship of . Note that the even field detection circuit 32 detects the even field using the horizontal synchronizing signal HD and the vertical synchronizing signal VD.
It can be detected by comparing the phase relationship between the two. Then, by extracting the upper sideband component with the BPF 6, the original luminance signal high frequency component Y is obtained. demodulates to.

Next, μ. An embodiment of the phase recovery circuit 31 is shown in FIG. fFIc and μ0 have a phase relationship as shown in the figure. Therefore, μ0 is defined as points a, b, and
Sample at points c, d, and e, and when these sample values reach the maximum at point a, μ. By setting the phase of π/2+3Nπ/10, phase reproduction of μ0 can be realized.

The latch circuit 33 has μ. f8(, period a, b.

Sample at the point c + d + c. The maximum value detection circuit 34 detects when the signal a reaches the maximum value. Since the maximum value of the signal a occurs every 5 cycles of the fFl+': clock, the protection circuit 35 detects whether the detected maximum value occurs in this cycle and detects it at the correct cycle. is being performed, a control signal is generated to set the phase of the ψ phase generating circuit 36 to π/2. By this operation, it is possible to prevent 1F from malfunctioning when maximum value detection is erroneous due to the influence of noise or the like. In the ψ phase generation circuit 36=20-, π/2+3Nπ/1 in 4fqc20 clock period
0 (N=0.1.2...19) is periodically generated, and the control signal of the protection circuit 35 initializes N=O.

This concludes the explanation of the YH' signal demodulation circuit, and then the interpolation circuit will be explained.

FIG. 14 shows an embodiment of the interpolation circuit. Demodulated color difference signal 1. With this configuration, Q constitutes color difference signals I/Q that are time-division multiplexed alternately every 4 fsc clocks.
The circuit can be simplified compared to performing I and Q independently. By a combination of 262 line delay circuit 1 and 1 line delay circuit 2.

Create various signals necessary for interpolation. Scan line X. As an interpolation signal corresponding to 0, one arithmetic circuit 5 uses 1/2 (Xc
-2e2+Xcze3), an interpolation signal D08 corresponding to the still image is generated. In the other arithmetic circuit 5, the signals Xc and X(, o of the scanning line after one line are 1/
2(X,.

An interpolation signal corresponding to the moving image is generated by calculating 1x c t ). , generates. These signals are delayed by one line in a one-line delay circuit 2, and then a multiplication circuit 10 performs a weighting operation of 1- on the coefficients corresponding to the respective movements.
The arithmetic circuit 5 adds the two to generate an interpolated scanning line signal.

On the other hand, 11! IJ! ! '2 color difference signal I also for signal Y
Similarly to 10, a signal necessary for interpolation is generated by a combination of a 262-line delay circuit 1, a 1-line delay circuit 2, and a 263-line delay circuit 40. Then, in one arithmetic circuit 5,
Y2 B 3. From the signal of Xy 2 B□, 1 /
2 (X, -□RA+XY-26□) is performed to generate an interpolation signal DY8 corresponding to the still image.

The other calculation amount i! 85 is 1/2 (X z7n+
By calculating the interpolation signal D corresponding to the moving image
Generate YM. These signals are added to the coefficient corresponding to the movement by 1- in the multiplication circuit 1°, and then sent to the calculation circuit 5.
, the two are added together to generate an interpolated scanning line signal of the luminance signal.

On the other hand, in the motion detection circuit 11, the luminance signals X7° and D
YR, D aya is used to generate the motion coefficient k.

Note that for the signals of the main scanning lines (scanning lines on which no interpolation is performed), signals whose delay amounts are adjusted by the delay circuit 9 are used.

Next, FIG. 15 shows an embodiment of a motion detection circuit for scanning line interpolation. This operation will be explained below.

First, the arithmetic circuit 5 selects Xvo Xv-525 or
Y21'i, -x, -2B□ are calculated, the absolute value circuit 13 performs absolute value quantization with the characteristics shown in FIG. 5(a), and the maximum value selection circuit 14 selects the larger of the two values. is selected to generate motion information MI.

In addition, the arithmetic circuit 5 calculates the difference between the interpolation signal DY8 for still images and the interpolation signal DYM for moving images, Dy, -DYM, and absolute value quantization is performed in the absolute value circuit 13 to generate the MDI signal. generate.

On the other hand, changes in the horizontal and vertical directions are detected from the X y O and X y 1 signals. First, the arithmetic circuit 5 calculates XYo-XY4, or XY,, -XY, using the signal XY delayed by one line in the one-line delay circuit 2, and the absolute value quantization is performed in the absolute value circuit 13, and the maximum value is The selection circuit 14 detects the maximum value of both as the vertical variation ΔY. Further, for the signals obtained by X y n and the one-pixel delay circuit 28, the arithmetic circuit 5 calculates a difference signal between adjacent pixels in the horizontal direction, and the absolute value quantization is performed by the absolute value circuit 13. The maximum value is taken out by the maximum value selection circuit 14,
It is detected as a horizontal change ΔX.

Based on these ΔY and ΔX signals, the image pattern recognition 5111 circuit 37 divides three types of areas 1. Classified into n and H. Region I corresponds to a vertical pattern, and has pattern information P1 and variation P W , =Δ
Let Y be the output. Area ■ corresponds to a diagonal pattern, and pattern information P2 and P W 2 = ΔX2 + ΔY
2 is the output. Furthermore, area (3) corresponds to a horizontal pattern, and outputs pattern information P3 and PW3''ΔX. These operations can be easily realized using a ROM or the like.

Now, in the normalization circuit 38, according to the information of P j +PW, the Ml and MDI signals are normalized with the characteristics shown in FIG. ) and (e) are characteristics for the signal MDI, and output Ml and MDI signals, respectively. Maximum value selection circuit 14
Now select the maximum value of both. This signal as well as the signal delayed by the 1-line delay circuit 2 are processed by the smoothing circuit 16 (
Smoothing is performed in the horizontal and vertical directions using a configuration similar to that shown in FIG. 7) to generate motion information MVI.

The motion coefficient generation circuit 39 generates a motion coefficient k for this motion information MVI with the characteristics shown in FIG.

Generate 1-k.

〔Effect of the invention〕

According to the present invention, it is possible to receive both current television signals and compatible high-definition television signals as high-definition, high-quality images, which has an extremely large effect on improving the quality of received images. There is.

In addition, in the embodiment of the present invention, Y, , C, Y, 'separation,
Although separate motion detection circuits are used for scanning line interpolation and scanning line interpolation, it is also possible to use them in common. Further, in the interpolation, the color difference signal is performed in a fixed DCM mode, thereby simplifying the circuit.

Further, although audio processing is not described in the present invention, conventional methods may be applied in this regard.

However, in the present invention, since the signal processing involves a delay of several frames, it is extremely important to also delay the audio so that it matches the reproduced image.

Furthermore, in the present invention, the configuration has been described in which the signal is converted to a digital signal by A/D conversion at the stage of conversion to baseband, but for example, the signal is converted to a digital signal by A/D conversion at the stage of video intermediate frequency, Needless to say, it is possible to implement the following using this digital signal.

[Brief explanation of the drawing]

Figure 1 is the block configuration of the present invention, Figure 2 is an explanatory diagram of a television signal, and Figures 3 to 11 are motion adaptive Y...
An example of C, Yl+' separation, Figures 12 and 13 are YH
'One embodiment of the signal demodulation circuit, FIGS. 14 to 18 are one embodiment of motion adaptive scanning line interpolation. 1...262 line delay circuit, 21 line delay circuit,
3...261 line delay circuit, 4525 line delay circuit, 5. Arithmetic circuit, 6. BPF, 7... Vertical edge detection circuit, 8... Selection circuit, 9... Delay circuit, 10
...Multiplication circuit, 11.Motion detection circuit, 12..LPF
, 13... Absolute value circuit, 14... Maximum value selection circuit, 1
5 large area static motion determination circuit, 16... smoothing circuit, 17.
・・C weight generation circuit, 18 ・Positive polarity quantization circuit, 19
...Negative polarity quantization circuit, 2o...Line 1 measurement circuit, 2
1...○R circuit, 22. Binarization circuit, 23.. Speed coefficient generation circuit, 24..Y) I weight generation circuit, 25.
・Threshold circuit, 26...Measurement circuit, 27...
Area expansion circuit, 281 pixel delay circuit, 29 - Mode determination circuit, 30 - Polarity control circuit, 31...μ. Phase regeneration circuit, 32. Even field detection circuit, 33. Latch circuit, 34. Maximum value detection circuit, 35. Protection circuit.
36 ψ phase generation circuit, 37 image pattern discrimination circuit,
38... Normalization circuit, 39... Motion coefficient generation circuit, 4
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Claims (1)

[Claims] In television receivers that receive television signals of both the current television system and the high-definition television system in which high-definition information is frequency-shifted and multiplexed within the current television signal band, motion information is obtained from the received signal. is detected from a combination of frequency domain and motion speed, and adaptively performs separation of luminance signals, color signals, high-definition information, and scanning line interpolation according to the motion information,
A television receiver characterized by displaying 60 frames in a sequential scanning format.