JPS6345915A - Noncyclic digital filter device for picture signal processing - Google Patents

Abstract

PURPOSE:To prevent the reduction in proper output picture element information in real time by providing an impulse response coefficient storage means and a coefficient control means, using two kinds of impulse response coefficients and supplementing the reduction in the output signal caused in passing the signal through a digital filter while giving the original signal as it is. CONSTITUTION:Input picture signals X(n) are inputted sequentially, but the signals X0-X2 are only written in a RAM 5. When the signal X(3) is inputted, an output signal SC3 of a coefficient control circuit 8 goes to an L level. A ROM 6 selects an impulse response coefficient h2(m) through the L level. In receiving the signal X(6), the output signal SC3 of the coefficient control circuit 8 goes to H and the ROM 6 selects the impulse response coefficient h1(m). In using the impulse response coefficient h2(m), (m-1)-set of signals are used as they are as output picture signals and in using the signal h1(m), the signal processed by the noncyclic digital filter is obtained to prevent the reduction in the output signal.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention performs arithmetic processing on digital image signals to produce various processed images (for example, images with pulse-like noise contained in the image signals suppressed, contour parts The present invention relates to an acyclic dinotal filter for image signal Σ processing that creates images (such as images with emphasis on the image).

(Prior art) When a digital image signal (for example, a digital television image signal obtained by A/D converting a television image signal) is input as an input signal to an acyclic digital filter and subjected to arithmetic processing, various image processing is possible. It is. Here, the acyclic digital filter is configured to obtain a desired filtered output signal by multiplying each time-series digital input signal by a certain coefficient and calculating the sum of the coefficients.
By selecting various coefficients and orders, various filter functions such as high pass, low pass 1ffi, band pass, and band rejection can be realized. Using these various filter functions, various types of image signal processing (suppression of pulse-like noise in images, contour enhancement, etc.) are possible. By the way, it is known that when a digital image signal is processed by an acyclic digital filter, appropriate pixel signals cannot be obtained at the beginning and end of a series of calculations. This is because pixel data necessary for the calculation is missing at the beginning and end of the series of calculations. For example, if a series of calculation processes is performed for each horizontal scan, inappropriate signals will be output to both the left and right ends, and if a series of calculation processes is performed for each frame, inappropriate signals will be output to both the left and right ends as well as to both the top and bottom ends. The pixels in which the inappropriate signals (, <) appear are determined by the order of the digital filter used; the greater the order, the more pixels in which inappropriate signals appear. Therefore, the number of correct outputs will be less than the number of input image signals.

That is, loss of signal) occurs. This effect becomes particularly large when the number of input image signals is small and the filter order is large.

(Problem to be solved by the invention) For this reason, when the number of input image signals is small, the influence on the image is large, so only acyclic digital filters with a small order can be used, and it is not always possible to obtain the desired filter performance. First, there was a problem in that it was not possible to achieve the desired image processing effect. In this case, in image processing using an acyclic digital filter, the above-mentioned inappropriate value will be outside the effective screen of the monitor screen, and if there is no substantial problem, it will be output as is, but if the usage is such that there is a problem, it will be output as is. In order not to cause any major disturbance to the output image signal, either a configuration is adopted in which this part is not output, or a specific image signal is prepared in advance for the input image signal that does not actually exist and is input to the digital filter. It was necessary to take a configuration to do so. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and provide an image signal processing device using an acyclic digital filter.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a dinotal signal processing device using an acyclic digital filter, which includes two types of impulse response coefficient storage means, One side describes the impulse response coefficient that allows the human signal to pass through as is.
The other one stores a predetermined impulse response coefficient, and includes coefficient control means for selecting one of the two types of impulse response coefficients, and according to the impulse response coefficient selected by the coefficient control means. It is characterized by arithmetic processing of human-powered digital signals.

(Function) By using two types of impulse response coefficients, the original signal is passed through and output as it is to supplement the reduced part of the output signal that occurs when passing through a digital filter, thereby reducing the output signal (reducing the appropriate output pixel information) ) can be prevented in real time.

(Example) An example of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an acyclic digital filter according to an embodiment of the present invention. In FIG. 1, 1 is the input terminal of the input image signal X (n), 2 is the input terminal of the clock signal GK synchronized with the input image signal, 3 is the coefficient control signal, and 4 is the output result Y of the acyclic digital filter. ”(n
=(m-1)/2) output terminal, 5 is RAM for storing input image signals, 6 is ROM for coefficients, 7 is ROM and RAM
8 is a coefficient control section, 9 is a multiplier/accumulator, and IO is a clock control circuit. The operation of the acyclic digital filter of this embodiment constructed as described above will be explained below with reference to FIGS. 2 and 3. In the following explanation, the digital input image signal (X(nT); n=0
．． 1, 2.3..., 1023), that is, 1024, and the order m of the acyclic digital filter is 7th order. CK, X (nT), Y shown in FIG.

((n-(N-1)/2)T) represents the timing relationship shown in FIG. 1, respectively. Figure 3 is the first
This shows the contents of the coefficient storage circuit ROM (6) in the figure. Here, the relationship between the output Y (nT) of the acyclic digital filter and the input signal X (nT) is expressed as m
It is generally expressed by the following formula.

Y (nT)-Σ + (mT) ・X ((n-m)
T)-414) Therefore, the output signal Y (nT) and the input signal X in the 7th-order acyclic digital filter
The relationship between (nT) is Y (nT)-Σh (mT)・X
((n-m)T)...(1-2).

Considering the delay time (m-1)/2·T, treat Y (nT) as Y' ((n-(m-1)/2)T). That is, Y' ((n-(m-1)/2)T) -Y (
nT)-Σh (mT)・X ((n-m)T)−・−
・・・－・・・－(1.3) From here on, T is omitted for simplicity, and Y
(nT) to Y (n), X (nT) to X (n),
Y'((n-(m-1)/2)T) to Y'(n-(
m-4)/2), h(mT) is written as h(m). As shown in FIG. 2, the image signal X (n) is input to RAM (5) in synchronization with CK. This CK is counted and written to RAM (51) from the address generator (7). When the writing is completed, the input image signal necessary for the acyclic digital filter is input from RAM (51) before the signal for which writing has been completed. The address output from the address generator (7) is input to the coefficient control circuit (8) and the coefficient storage ROM (61), and is input to the coefficient control signal S C (3) and the acyclic type. Outputs the coefficients of the digital filter. When these are completed, calculations are started in the multiplier/accumulator (9) and the results are output. Input image signals X (n) are input sequentially, but X (0) to Up to (2), the operation is only writing to RAM f5+.

When X (n) becomes X (3) (n・3) and the address at that time is output from the address generator (7), the output signal 5C (31) of the coefficient control circuit (8) outputs "L". .The ROM +61 selects the impulse response coefficient hz (m) shown in Fig. 3 based on the output "L" of this SC.At this time, the input-output relationship expressed by equation (l.3) is Y'
(0)・Y(3) = hz(0)・X (*) 10h z(1)・X(*
) 10hz(2)・X (*) 10hz(3)・X(0
)+h, (4)・X (1) + h 2(5)・X(
2) Ten, (6)・X(3) (However, X(*) indicates that the input image signal is undefined.) h 2 (0) = h 2 (1) = h 2 (2 ) = h
, (4)・h2(5)−h , (6) = 'i' from O (0) = h , (3)・×(0)hl(3
)・1, it can be expressed as Y' (0) = X (0). This means that the input signal X (n) is output as is from the digital filter. Similarly, when X(4) is input, the input/output relationship is Y'(1) - X(1). Similarly, when X(5) is input, Y'(2) = X(2). Become.

Next, when X (6) is output, the signals necessary for the 7th order acyclic digital filter are complete, and the coefficient control circuit (8) receives the address generated by the address generator (7). Set the output signal SC(3) to "H". SC
By setting (3) to "H", h, (m) of the impulse response coefficient h (m) shown in FIG. 3 is selected.

By selecting h + (m), the relationship between human output becomes (l・
3) From formula, Y”(3) = h, (0)・X(0)+h, (1
)・X(1)+hl(2)・X(2) 4 h, (4
)・X(4)+h+<5)・X(5)+h
, (6)·X(6), and a valid processing result is output from the digital filter.

Thereafter, this acyclic digital filter repeats the same operation until the input of X (1023) is completed.

When X (1023) is input, Y' (1020)
= h, (0)・X (1017)+h, (1)
・X (101B) +hl(2)・X (1019) + h, (3)
, X (1020)+h+(4)・X (1021
) 10h, (5)・X (1022) 10h+(6)
-X (1023) is output.

When X (1023) is input and Y' (1020) is output from the acyclic digital filter, the output 5C (3+ of the coefficient control circuit (8) returns to "■B" and Y'
(1021), Y' (1022), Y' (1023) as impulse response coefficient h2(m)
Calculate and output using . At this time, each value is Y
'(1021)=x (1021)Y''(1022)
・X (1022) Y' (1023)・X (1023) will be obtained. At this time, the clock signal CK is the clock pulse gravity 11
CK' for (ml)/2 samples from the generation circuit (10)
(11) is added.

As described above, by performing real-time processing on a series of finite digital image signals using an acyclic digital filter, the (m
The impulse response coefficient hZ(m
), it is possible to use (ml) input image signals as they are as output image signals, and by using hl(m), it is possible to obtain a signal processed by an acyclic digital filter. It is possible to obtain as many output results as a finite series of digital input images without limiting the order of the filter.

Furthermore, in this embodiment, the filter order is set to 7th order, but it is of course not limited to this.

(Effects of the Invention) By using two types of impulse response coefficients, the present invention prevents a decrease in the output signal that occurs when a periodic and finite number of digital input signals are passed through an acyclic digital filter, and By outputting the meaningless signal portions at both ends of the signal as original signals, it is possible to prevent the meaningless signals from appearing in real time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an acyclic digital filter according to an embodiment of the present invention, FIG. 2 is a diagram showing the processing method and timing relationship of the block diagram shown in FIG. 1, and FIG. 1 represents the contents of the coefficient storage ROM shown in FIG. (Explanation of symbols of main parts) 1.2 Input terminal 4 Output terminal 5
ROM 7 Address generator B Coefficient 1 control circuit 1] Multiplier/accumulator 10 This is an additional clock pulse generation circuit.

Claims (1)

[Claims] a plurality of types of impulse response coefficient storage means; a coefficient selection means for selectively selecting one of the plurality of types of impulse response coefficients stored in the storage means; and an impulse response coefficient selected by the coefficient selection means. In an acyclic digital filter consisting of a multiplication/accumulation means for multiplying/accumulating a digital input signal by means of a clock pulse addition generating circuit and one horizontal signal and/or one vertical signal of the input digital image signal, a detection means for detecting an initial stage and a final stage, and one of the plurality of types of impulse response coefficients stored in the storage means passes the input signal as it is, and the coefficient is determined by the output of the detection means. 1. An acyclic digital filter device for image signal processing, characterized in that it is configured to control selection means.