JPS6345075Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field The present invention relates to a display device for a PLL receiver having a preset function.

(B) Background Art In general, in a PLL receiver having a preset function, as shown in Fig. 1, in addition to a frequency display 1 for digitally (numerical) display of the reception frequency, a preset memory is used for writing and waiting. A display element 2 is provided to indicate the status of the preset memory, and this display element 2 lights up in response to the depression of a memory set switch 3 for setting the preset memory in a write standby state. Then, normally, the light is turned off by pressing any one of the preset switches 4 and writing information corresponding to the received frequency into the preset memory of the desired channel.

However, as shown in Figure 1, instead of using a digital (numerical) display to display the received frequency, a frequency display consisting of a plurality of display elements arranged in a row is used to display a dot or bar display. When performing this, the shape of the display element that indicates that the preset memory is in the write standby state is usually dot-shaped or bar-shaped, and is similar to the shape of the display element of a frequency display, so it is not necessary to If you just turn on this display element in standby mode, it will be difficult to see.
It is difficult to confirm that the device is on standby. Further, it is uneconomical to provide a display element indicating the standby state separately from the frequency display as in the conventional case.

(C) Purpose of the invention The present invention aims to reduce the number of elements and cost by using the display element of the frequency display as the display element that indicates that the preset memory is in a write standby state, and By blinking this display element in the write standby state, it is possible to indicate that the preset memory is in the write standby state.
The purpose is to make the user more clearly aware of this.

(D) Embodiment FIG. 2 is a block diagram of main parts showing an embodiment of the present invention, and 5 is a programmable circuit commonly used in PLL receivers to divide the output of a local oscillator (not shown). A divider, 6 is a channel selection counter for setting frequency division number data to the programmable divider 5, 7 is a display decoder for decoding the frequency division number data set to the programmable divider 5, and 8 is arranged in a line. 9 is a display drive circuit that drives the corresponding liquid crystal display element of the frequency display 8 in accordance with the output of the display decoder 7, or 10 11 is an extraction circuit consisting of an inverter 12, D flip-flops 13 and 14, and an AND gate 15; 16 is a blanking pulse φ ₂ of a predetermined cycle and a timer time. a timing pulse generation circuit that generates a timing pulse φ ₃ that gives T ₀ ;
17 and 18 are RS flip-flop and
The NAND gate 19 is an AND gate serving as an inhibit gate, which inputs the outputs of the display decoders at one end, inputs the output _G2 of the NAND gate 18 at the other end, and inputs the output to the display drive circuit 9.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

Therefore, first, when the memory set switch 10 is not pressed, the SR flip-flop 1
Since the Q output of 7 is at "L" level,
The output _G2 of the NAND gate 18 is at "H" level. Therefore, at this time, the output of the display decoder 7 is input to the display drive circuit 9 without being blocked by the AND gate 19 as a prohibition gate, so that the output of the display decoder 7 is input to the frequency display 8. In response, the corresponding liquid crystal display element lights up to display the reception frequency.

Therefore, for example, if the memory set switch 10 is pressed as shown in _FIG . Clock φ ₁ (D flip-flop 13 in synchronization with Fig. 3 A)
and 14 Q ₁ and ₂ outputs are both “H”
Only during the level period, the level becomes "H" as shown in FIG. 3C. For this reason, the RS flip-flop 17
is set, and its Q output goes to the "H" level as shown in FIG. 3D and is applied to the preset memory, so that the preset memory enters a write standby state. At the same time, the output of AND gate 15
_G1 temporarily resets the timing pulse generation circuit 16, and this reset is canceled immediately, so
A blanking pulse φ ₂ begins to be generated at a predetermined period as shown in FIG. 3(e). Since this blanking pulse φ ₂ and the “H” level Q output of the RS flip-flop 17 are input to the NAND gate 18, this output G ₂ is an inverted signal of the blanking pulse φ ₂ as shown in FIG. The "H" level and "L" level are alternately repeated. Since this output _G2 is applied to the AND gate 19 as a prohibition gate, the output of the display decoder 7 is this
It is intermittently blocked by AND gate 19. As a result, the m-th display element that was lit on the frequency display 8 will blink. Then, when one of the preset switches is pressed to write information corresponding to the received frequency into the preset memory of the desired channel, a signal P is generated, which resets the RS flip-flop 17 via the OR gate 20. Therefore, the Q output is inverted to "L" level. Therefore, the write standby state is released and the output G ₂ of the NAND gate 19 becomes "H" level, so the output of the display decoder 7 is
It is no longer blocked by the AND gate 19, and the mth display element stops blinking and lights up again. Furthermore, when writing to the preset memory is not performed, the signal P is not generated, but after the predetermined timer time _T0 has elapsed, the timing pulse _φ3 goes to the "H" level and resets the RS flip-flop 17. , as described above, the write standby state is released and the m-th display element stops blinking.

As described above, when the preset memory enters the write standby state by pressing the memory set switch 10, the display element of the frequency display 8 flashes during that state.

In the above description, the display decoder 7
We have explained the dot display in which only one m-th display element of the frequency display 8 lights up for a certain output, but for the same output of the display decoder 7, all of the The present invention can also be applied to a bar display in which the display elements are lit, and in this case, in the preset memory write standby state, all the display elements from the 1st to the mth display blink.

(E) Effect As described above, the display device of the PLL receiver according to the present invention indicates that the preset memory is in the write standby state by blinking the display element of the frequency display that displays the reception frequency. As a result, it is possible to reduce the number of elements and cost, which is very economical, and also allows the user to clearly recognize that the writing is in standby mode, thus preventing erroneous operations. can do.

[Brief explanation of drawings]

Fig. 1 is a front view showing the operation section and display section of a conventional PLL receiver, Fig. 2 is a block diagram of main parts showing an embodiment of the present invention, and Fig. 3 explains the operation of the embodiment of Fig. 2. This is a timing chart for Explanation of main figure numbers, 5...Programmable divider, 7...Display decoder, 8...Frequency display, 9...Display drive circuit, 10...Memory set switch, 11...Cutout circuit, 16... ...Timing pulse generation circuit, 17...RS flip-flop, 18...NAND gate, 19...AND
Gate.

Claims (1)

[Scope of utility model registration request] A frequency display comprising a plurality of display elements, a display decoder that decodes frequency division data set in a programmable divider, and a display drive circuit that drives the frequency display according to the output of the display decoder. Pulse generating means for generating a blanking pulse in response to operation of a memory set switch for setting a preset memory to a write standby state in a PLL receiver having a preset function and equipped with a reception frequency display circuit comprising: and a prohibition gate that intermittently cuts off the output of the display decoder using the blanking pulse, and a timer means that releases the write standby state when a predetermined period of time has elapsed after the operation of the memory set switch. Before operating the memory set switch, the display element of the frequency display is turned on to display the reception frequency, and the write waiting state of the preset memory is displayed by blinking the display element, A display device for a PLL receiver, characterized in that when the standby state is canceled by the timer means, the display element is turned on again.