JPS634421B2 - - Google Patents
Info
- Publication number
- JPS634421B2 JPS634421B2 JP11881581A JP11881581A JPS634421B2 JP S634421 B2 JPS634421 B2 JP S634421B2 JP 11881581 A JP11881581 A JP 11881581A JP 11881581 A JP11881581 A JP 11881581A JP S634421 B2 JPS634421 B2 JP S634421B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- eio
- power supply
- switching
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004804 winding Methods 0.000 claims description 21
- 238000001514 detection method Methods 0.000 claims description 10
- 238000009499 grossing Methods 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 6
- 230000002194 synthesizing effect Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 8
- 241000043482 Pomax Species 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33561—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having more than one ouput with independent control
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Description
【発明の詳細な説明】
本発明は、過電流保護機能を有する多出力スイ
ツチング電源に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-output switching power supply having an overcurrent protection function.
従来のこの種の多出力スイツチング電源の一例
を第１図に示す。この図において、出力トランス
１の一次巻線１Ａにはスイツチング回路２より矩
形波電圧が供給され、出力トランス１の二次側の
出力巻線１Ｂ，１Ｃに夫々ダイオードD1，D2及
びコンデンサC1，C2から成る整流平滑回路が設
けられている。そして、所定の直流出力が出力端
子P1，Ｎ間及び出力端子P2，Ｎ間に出力される
ようになつている。この場合、スイツチング回路
２内のスイツチング素子に過電流が流れて破損に
到らないように、出力端子Ｎに接続された共通帰
線３に直列に抵抗器Ｒを挿入し、この両端の電圧
Ｅより負荷電流の総和を知り、これによつてスイ
ツチング回路２内のスイツチング素子のオン期間
又はオフ期間あるいは動作周波数を制御してスイ
ツチング素子に流れる電流を制限するようにして
いる。 An example of a conventional multi-output switching power supply of this type is shown in FIG. In this figure, the primary winding 1A of the output transformer 1 is supplied with a rectangular wave voltage from the switching circuit 2, and the secondary output windings 1B and 1C of the output transformer 1 are supplied with diodes D 1 and D 2 and a capacitor C, respectively. A rectifying and smoothing circuit consisting of C1 and C2 is provided. A predetermined DC output is output between the output terminals P 1 and N and between the output terminals P 2 and N. In this case, a resistor R is inserted in series with the common return wire 3 connected to the output terminal N to prevent overcurrent from flowing into the switching elements in the switching circuit 2 and causing damage. The sum of the load currents is thus known, and the on-period or off-period or operating frequency of the switching elements in the switching circuit 2 is controlled based on this information to limit the current flowing through the switching elements.
しかし、単純に負荷電流の総和を検出していた
のでは、出力端子P1，Ｎ間の電圧値と出力端子
P2，Ｎ間の電圧値との差異が大きい場合には、
スイツチング素子に過電流が流れる恐れがある。
すなわち、電圧値の大きい方の負荷が重くなつた
ときは、同一負荷電流であつても出力電力は大き
くなり、スイツチング素子の電流も増加するから
である。 However, simply detecting the sum of the load currents would result in the voltage value between the output terminals P 1 and N
If the difference between the voltage value between P 2 and N is large,
There is a risk of overcurrent flowing to the switching element.
That is, when the load with a larger voltage value becomes heavier, the output power becomes larger even if the load current is the same, and the current of the switching element also increases.
本発明は、上記の点に鑑み、出力トランスの二
次側出力電力の総和に比例した合成検出電圧を利
用してスイツチング素子のオン期間又はオフ期間
あるいは動作周波数を可変制御することにより、
スイツチング素子の過電流を確実に防止し、しか
も過負荷とならない範囲の限界まで効果的に作動
させることが可能な多出力スイツチング電源を提
供しようとするものである。 In view of the above points, the present invention variably controls the on period or off period or operating frequency of the switching element using a composite detection voltage proportional to the sum of the secondary side output power of the output transformer.
It is an object of the present invention to provide a multi-output switching power supply that can reliably prevent overcurrent of a switching element and can operate effectively to the limit of the range that does not result in overload.
以下、本発明に係る多出力スイツチング電源の
実施例を図面に従つて説明する。 Embodiments of the multi-output switching power supply according to the present invention will be described below with reference to the drawings.
第２図は本発明の第１実施例を示す。この図に
おいて、出力トランス１０はタツプ付の一次巻線
１０Ａと、二次側に複数の出力巻線１０Ｂ，１０
Ｃとを有しており、スイツチングトランジスタＱ
のコレクタは一次巻線１０Ａの一端に接続されて
いる。また、一次巻線１０Ａの他端とトランジス
タＱのエミツタとの間にダイオードD3が接続さ
れる。入力端子Ｘ，Ｙ間には交流入力電圧が供給
され、これは全波整流器１１で整流され、コンデ
ンサC3で平滑された後、一次巻線１０Ａのタツ
プとトランジスタＱのエミツタとの間に給電さ
れ、トランジスタＱのスイツチング動作により断
続される。この結果、出力トランス１０の一次巻
線１０Ａは矩形波パルス電圧により励磁され、二
次側の出力巻線１０Ｂ，１０Ｃには所定の巻線比
に応じて矩形波パルス電圧が誘起される。出力巻
線１０ＢにはダイオードD4，D5、チヨークコイ
ルCH1及びコンデンサC4からなる整流平滑回路が
接続され、出力巻線１０ＣにはダイオードD6，
D7、チヨークコイルCH2及びコンデンサC5から
なる整流平滑回路が同様に設けられている。ここ
で、チヨークコイルCH1，CH2は相互に磁気的に
密結合されている。これは、一方の出力の負荷が
重く、他方が無負荷のような場合にも同じ割合で
電圧降下が生じるようにして、一方の出力の安定
化制御を行えば、他方もこれに準じて安定化され
るようにするためである。前記各整流平滑回路の
直流出力は夫々出力端子P1，N1間及びP2，N2間
に導出される。ただし、出力端子N1，N2に接続
される負側線路１２，１３には夫々抵抗器R1，
R2が挿入されている。この抵抗器R1，R2の一端
（非接地側）と誤差増幅器１４の一方の入力端と
の間に夫々抵抗器R1S，R2Sが接続される。誤差増
幅器１４の他方の入力端には基準電圧源１５が接
続されており、誤差増幅器１４の出力に応じて、
スイツチングトランジスタＱのオン期間又はオフ
期間あるいは動作周波数が可変制御されるように
なつている。なお、図示していないが、別の誤差
増幅器が直流出力の安定化のために設けられてお
り、例えば出力端子P1，N1間の定格出力電圧E1
が一定で、出力端子P2，N2間の定格出力電圧E2
もほぼ安定した状態に制御されるものとする。 FIG. 2 shows a first embodiment of the invention. In this figure, an output transformer 10 has a primary winding 10A with a tap, and a plurality of output windings 10B, 10 on the secondary side.
C, and a switching transistor Q
The collector of is connected to one end of the primary winding 10A. Further, a diode D3 is connected between the other end of the primary winding 10A and the emitter of the transistor Q. An AC input voltage is supplied between input terminals X and Y, and after being rectified by a full-wave rectifier 11 and smoothed by a capacitor C3 , power is supplied between the tap of the primary winding 10A and the emitter of the transistor Q. and is turned on and off by the switching operation of transistor Q. As a result, the primary winding 10A of the output transformer 10 is excited by the rectangular wave pulse voltage, and a rectangular pulse voltage is induced in the secondary output windings 10B and 10C according to a predetermined winding ratio. A rectifying and smoothing circuit consisting of diodes D 4 and D 5 , a choke coil CH 1 and a capacitor C 4 is connected to the output winding 10B, and a diode D 6 and a capacitor C 4 are connected to the output winding 10C.
A rectifying and smoothing circuit consisting of D 7 , a chiyoke coil CH 2 and a capacitor C 5 is similarly provided. Here, the chiyoke coils CH 1 and CH 2 are closely magnetically coupled to each other. This means that even if one output is heavily loaded and the other is unloaded, the voltage drop will occur at the same rate, and if one output is stabilized, the other will be stabilized accordingly. This is to ensure that the The DC output of each of the rectifying and smoothing circuits is led out between output terminals P 1 and N 1 and between output terminals P 2 and N 2 , respectively. However, the negative side lines 12 and 13 connected to the output terminals N 1 and N 2 have resistors R 1 and 13 , respectively.
R 2 is inserted. Resistors R 1S and R 2S are connected between one end (non-grounded side) of the resistors R 1 and R 2 and one input end of the error amplifier 14, respectively. A reference voltage source 15 is connected to the other input terminal of the error amplifier 14, and depending on the output of the error amplifier 14,
The on period, off period, or operating frequency of the switching transistor Q is variably controlled. Although not shown, another error amplifier is provided to stabilize the DC output, for example, the rated output voltage E 1 between the output terminals P 1 and N 1
is constant, and the rated output voltage E 2 between output terminals P 2 and N 2
is assumed to be controlled to a nearly stable state.
以上の構成において、出力トランス１０の二次
側の出力電力の総和P0は、抵抗器R1，R2に流れ
る電流をI1，I2としたとき次式で示される。 In the above configuration, the sum P 0 of output power on the secondary side of the output transformer 10 is expressed by the following equation, where the currents flowing through the resistors R 1 and R 2 are I 1 and I 2 .
E1I1＋E2I2＝P0 …(1)
また、アース電位を零としたとき、誤差増幅器
１４の一方の入力端の電位を−Eioとすると、
R1，R2≫R1S、R2Sなる条件下では
Eio＝R2SR1I1＋R1SR2I2／R1Ｓ＋R2S …(2)
が成立する。ここで、R1，R2，R1S，R2Sの抵抗
値をうまく設定すると、
P0∝Eio …(3)
なる関係を得ることができる。この(3)式の成立す
るための条件は次式で示される通りであり、
R2SR1／E1≒R1SR2／E2 …(4)
この(4)式を満足させれば、EioはP0に正比例した
合成検出電圧となる。この場合、E1，E2は設計
段階で既知であるから、R1，R2，R1S，R2Sの値
を(4)式が成立するように設定することは容易であ
る。 E 1 I 1 +E 2 I 2 =P 0 (1) Also, when the ground potential is zero, and the potential of one input terminal of the error amplifier 14 is -Eio,
Under the condition that R 1 , R 2 ≫ R 1S , R 2S , Eio=R 2S R 1 I 1 + R 1S R 2 I 2 /R 1 S+R 2S (2) holds true. Here, if the resistance values of R 1 , R 2 , R 1S , and R 2S are appropriately set, the following relationship can be obtained: P 0 ∝Eio (3). The conditions for formula (3) to hold are as shown in the following formula: R 2S R 1 /E 1 ≒R 1S R 2 /E 2 ...(4) If formula (4) is satisfied, , Eio becomes a composite detection voltage directly proportional to P 0 . In this case, since E 1 and E 2 are known at the design stage, it is easy to set the values of R 1 , R 2 , R 1S , and R 2S so that equation (4) holds true.
従つて、誤差増幅器１４の他方の入力端へ印加
される基準電圧源１５よりの基準電圧−EREFを、
取出し得る最大電力Pomaxのときの−Eioに一致
させれば、誤差増幅器１４は二次側出力電力の総
和P0が最大電力Pomaxを超えた時点で作動し、
トランジスタＱのオン期間を短く、又はオフ期間
を長く、又は動作周波数を高くする方向に制御
し、トランジスタＱの過電流を防止する。 Therefore, the reference voltage -E REF from the reference voltage source 15 applied to the other input terminal of the error amplifier 14 is
If it matches -Eio when the maximum extractable power Pomax is reached, the error amplifier 14 is activated when the sum P0 of the secondary side output power exceeds the maximum power Pomax,
Overcurrent of the transistor Q is prevented by controlling the on period of the transistor Q to be shortened, the off period to be lengthened, or the operating frequency to be increased.
前記(4)式において、さらにR1S≒R2Sに設定した
場合には
E1／R1≒E2／R2 …(5)
が得られる。この(5)式の条件によれば、各抵抗器
の値の設定を極めて容易に実行できる利点があ
る。 In the above equation (4), when R 1S ≈R 2S is further set, E 1 /R 1 ≈E 2 /R 2 (5) is obtained. According to the condition of equation (5), there is an advantage that the value of each resistor can be set extremely easily.
さらに、(4)式を満足させると共に、次式
R1I2 10R2I2 20 …(6)
（但し、I10はI1の最大定格電流、I20はI2の最大定
格電流）を満足させれば、最大定格動作時におけ
る抵抗器R1，R2の消費電力を同一にでき、抵抗
器R1，R2の電力容量を同じにできる。また、こ
の場合には各出力の効率を均一化できる利点もあ
る。 Furthermore, while satisfying formula (4), the following formula R 1 I 2 10 R 2 I 2 20 ...(6) (However, I 10 is the maximum rated current of I 1 , I 20 is the maximum rated current of I 2 ) If these are satisfied, the power consumption of the resistors R 1 and R 2 during maximum rated operation can be made the same, and the power capacities of the resistors R 1 and R 2 can be made the same. Further, in this case, there is an advantage that the efficiency of each output can be made uniform.
以上説明したように、上記第１実施例によれ
ば、誤差増幅器１４は、出力トランス１０の二次
側出力電力の総和P0が最大電力Pomaxを超えた
とき動作し、各出力に接続された負荷の軽、重に
は影響されないから、いかなる場合にも確実にス
イツチングトランジスタＱの過電流を防止し、こ
れの保護ができる。また、過負荷とならない範囲
の限界までトランジスタＱを効果的に動作させ得
る利点もある。 As explained above, according to the first embodiment, the error amplifier 14 operates when the sum P 0 of the secondary output power of the output transformer 10 exceeds the maximum power Pomax, and Since it is not affected by light or heavy loads, overcurrent of the switching transistor Q can be reliably prevented and protected in any case. Another advantage is that the transistor Q can be effectively operated to the limit without overloading.
第３図は本発明の第２実施例を示す。この図に
おいて、出力トランス１０の二次側の出力巻線１
０ＢにはダイオードD8及びコンデンサC6の整流
平滑回路が、出力巻線１０ＣにはダイオードD9
及びコンデンサC7の整流平滑回路が夫々接続さ
れている。出力巻線１０Ｂ側の整流出力は出力端
子P3，Ｎ間に導出されて負荷RL1に供給される。
ただし、出力端子P3に接続された正側線路２０
には抵抗器R3が挿入されている。出力巻線１０
Ｃ側の整流出力は出力端子P4，P3間に導出され、
この結果、負荷RL2には両方の整流出力の和が供
給される。ただし、出力巻線１０Ｃと出力端子
P3との間の負側線路２１には抵抗器R4が挿入さ
れている。そして、抵抗器R3の一端は誤差増幅
器１４の一方の入力端に直結され、抵抗器R4の
一端は基準電圧源１５を介して誤差増幅器１４の
他方の入力端に接続される。なお、出力トランス
１０の一次側の回路は第２図の場合と同様であ
る。 FIG. 3 shows a second embodiment of the invention. In this figure, the output winding 1 on the secondary side of the output transformer 10
0B has a rectifying and smoothing circuit consisting of diode D 8 and capacitor C 6 , and output winding 10C has a diode D 9.
and a rectifying and smoothing circuit of capacitor C7 are connected respectively. The rectified output on the output winding 10B side is led out between the output terminals P 3 and N and supplied to the load R L1 .
However, the positive side line 20 connected to the output terminal P3
A resistor R3 is inserted in. Output winding 10
The rectified output on the C side is derived between output terminals P 4 and P 3 ,
As a result, the sum of both rectified outputs is supplied to the load R L2 . However, output winding 10C and output terminal
A resistor R 4 is inserted in the negative line 21 between it and P 3 . One end of the resistor R 3 is directly connected to one input end of the error amplifier 14 , and one end of the resistor R 4 is connected to the other input end of the error amplifier 14 via the reference voltage source 15 . The circuit on the primary side of the output transformer 10 is the same as that shown in FIG.
以上の構成において、出力トランス１０の二次
側の出力電力の総和P0は、抵抗器R3、負荷RL1，
RL2に夫々流れる電流をI3，LL1，LL2、負荷RL1，
RL2の両端の電圧をE3，EL2としたとき、次式で
示される。 In the above configuration, the sum P 0 of the output power on the secondary side of the output transformer 10 is determined by the resistor R 3 , the load R L1 ,
The current flowing through R L2 is I 3 , L L1 , L L2 , load R L1 ,
When the voltages across R L2 are E 3 and E L2 , it is expressed by the following equation.
P0＝E3IL1＋EL2IL2＝E3I3＋E4IL2 …(7)
（但し、E4はP4，P3間の電圧）
また、基準電圧源１５の負側端と誤差増幅器１
４の一方の入力端との間の電位差−Eioは
Eio＝R3I3＋F4IL2 …(8)
となる。従つて、前述の(3)式のように合成検出電
圧としてのEioがP0に正比例する条件は
R3／E3≒R4／E4 …(9)
となる。従つて、基準電圧源１５の基準電圧−
EREFを、取出し得る最大電力Pomaxのときの−
Eioに一致させれば、誤差増幅器１４は二次側出
力電力の総和P0が最大電力Pomaxを越えた時点
で動作し、トランジスタＱに過電流が流れないよ
うに制御する。P 0 = E 3 I L1 + E L2 I L2 = E 3 I 3 + E 4 I L2 …(7) (However, E 4 is the voltage between P 4 and P 3 ) Also, the negative side end of the reference voltage source 15 and error amplifier 1
The potential difference −Eio between the input terminal and one of the input terminals of 4 is Eio=R 3 I 3 +F 4 I L2 (8). Therefore, the condition that Eio as the composite detection voltage is directly proportional to P 0 as in the above-mentioned equation (3) is R 3 /E 3 ≈R 4 /E 4 (9). Therefore, the reference voltage of the reference voltage source 15 -
- When E REF is the maximum power Pomax that can be extracted
If Eio is made to match Eio, the error amplifier 14 operates when the sum P 0 of the secondary side output power exceeds the maximum power Pomax, and controls the transistor Q so that no overcurrent flows.
以上説明したように、出力トランスの二次側の
各出力における出力電流を直列抵抗により検出
し、抵抗回路によつて前記出力電流に対応する検
出電圧を合成した合成検出電流Eioが、各出力電
圧におおよそ比例した係数と、各出力電流との積
の総和、すなわちEioΣKi・Ii（ただし、Ki
Ａ・Eiで、Kiは抵抗回路の伝達抵抗、Ａは定数、
Eiは各定格出力電圧、Iiは各出力電流）であるよ
うになし、この合成検出電圧Eioを用いてスイツ
チング素子を制御しているので、スイツチング素
子を過電流から確実に保護し、しかも過負荷とな
らない範囲の限界まで効果的に作動させることが
可能な多出力スイツチング電源を得ることができ
る。 As explained above, the output current at each output on the secondary side of the output transformer is detected by a series resistor, and the composite detection current Eio, which is obtained by synthesizing the detection voltages corresponding to the output currents using a resistor circuit, is calculated at each output voltage. The sum of the products of the coefficient roughly proportional to each output current, that is, EioΣKi・Ii (however, Ki
In A・Ei, Ki is the transmission resistance of the resistance circuit, A is a constant,
Ei is each rated output voltage, Ii is each output current), and this composite detection voltage Eio is used to control the switching elements, so the switching elements are reliably protected from overcurrents and are also protected against overloads. It is possible to obtain a multi-output switching power supply that can be effectively operated to the limit of the range in which it does not occur.
第１図は従来の多出力スイツチング電源の一例
を示す回路図、第２図は本発明に係る多出力スイ
ツチング電源の第１実施例を示す回路図、第３図
は第２実施例を示す回路図である。
１０…出力トランス、１０Ａ…一次巻線、１０
Ｂ，１０Ｃ…出力巻線、１４…誤差増幅器、１５
…基準電圧源、C1乃至C7…コンデンサ、D1乃至
D9…ダイオード、CH1，CH2…チヨークコイル、
Ｑ…トランジスタ、R1乃至R4，R1S，R2S…抵抗
器。
Fig. 1 is a circuit diagram showing an example of a conventional multi-output switching power supply, Fig. 2 is a circuit diagram showing a first embodiment of the multi-output switching power supply according to the present invention, and Fig. 3 is a circuit diagram showing a second embodiment. It is a diagram. 10...Output transformer, 10A...Primary winding, 10
B, 10C...Output winding, 14...Error amplifier, 15
…Reference voltage source, C 1 to C 7 … Capacitor, D 1 to
D 9 ...diode, CH 1 , CH 2 ...chiyoke coil,
Q...Transistor, R1 to R4 , R1S , R2S ...Resistor.
Claims (1)
を設けて該出力トランスをパルス電圧で励磁し、
該出力トランスの二次側の複数の出力巻線に誘起
された交流電圧を夫々整流、平滑して複数の安定
化出力を得る多出力スイツチング電源において、
前記複数の出力の各出力電流を直列抵抗により検
出して抵抗回路によつて前記各出力電流に対応す
る検出電圧を合成した合成検出電圧（Eio）が、
各出力電圧におおよそ比例した係数と、各出力電
流との積の総和であるようになし、前記合成検出
電圧（Eio）を検出して、前記スイツチング回路
のスイツチング素子の過電流保護をなすように、
当該スイツチング素子のオン期間又はオフ期間あ
るいは動作周波数を可変制御することを特徴とす
る多出力スイツチング電源。 ２ 前記複数の出力の各出力電力に略比例した抵
抗損失となる如く前記直列抵抗の値を設定した特
許請求の範囲第１項記載の多出力スイツチング電
源。 ３ 前記複数の出力の最大定格電流出力時に、前
記各直列抵抗の抵抗損失が、夫々略等しくなる如
く当該直列抵抗の値を設定した特許請求の範囲第
１項記載の多出力スイツチング電源。[Claims] 1. A switching circuit is provided in the primary winding of the output transformer to excite the output transformer with a pulse voltage,
In a multi-output switching power supply that obtains a plurality of stabilized outputs by rectifying and smoothing alternating current voltages induced in a plurality of output windings on the secondary side of the output transformer,
A composite detection voltage (Eio) is obtained by detecting each output current of the plurality of outputs using a series resistor and synthesizing the detection voltages corresponding to each of the output currents using a resistor circuit.
The combined detection voltage (Eio) is set to be the sum of the products of a coefficient roughly proportional to each output voltage and each output current, and the combined detection voltage (Eio) is detected to provide overcurrent protection for the switching element of the switching circuit. ,
A multi-output switching power supply characterized in that the on period or off period or operating frequency of the switching element is variably controlled. 2. The multi-output switching power supply according to claim 1, wherein the value of the series resistor is set so that the resistance loss is approximately proportional to the output power of each of the plurality of outputs. 3. The multi-output switching power supply according to claim 1, wherein the values of the series resistors are set so that the resistance losses of the series resistors are approximately equal when the plurality of outputs output maximum rated currents.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11881581A JPS5819921A (en) | 1981-07-29 | 1981-07-29 | Multioutput switching power source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11881581A JPS5819921A (en) | 1981-07-29 | 1981-07-29 | Multioutput switching power source |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5819921A JPS5819921A (en) | 1983-02-05 |
| JPS634421B2 true JPS634421B2 (en) | 1988-01-28 |
Family
ID=14745816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11881581A Granted JPS5819921A (en) | 1981-07-29 | 1981-07-29 | Multioutput switching power source |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5819921A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60157615A (en) * | 1984-01-27 | 1985-08-17 | Fujitsu Ltd | Neutral point direct grounding type constant current circuit |
| US4586119A (en) * | 1984-04-16 | 1986-04-29 | Itt Corporation | Off-line switching mode power supply |
| JPH0326283U (en) * | 1989-07-21 | 1991-03-18 | ||
| JP5195603B2 (en) * | 2009-04-15 | 2013-05-08 | 株式会社デンソー | DCDC converter control device and control system |
| US8814327B2 (en) | 2011-07-01 | 2014-08-26 | Canon Kabushiki Kaisha | Power supply apparatus and printing apparatus |
-
1981
- 1981-07-29 JP JP11881581A patent/JPS5819921A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5819921A (en) | 1983-02-05 |
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