JPS6343940B2 - - Google Patents

Info

Publication number
JPS6343940B2
JPS6343940B2 JP55146673A JP14667380A JPS6343940B2 JP S6343940 B2 JPS6343940 B2 JP S6343940B2 JP 55146673 A JP55146673 A JP 55146673A JP 14667380 A JP14667380 A JP 14667380A JP S6343940 B2 JPS6343940 B2 JP S6343940B2
Authority
JP
Japan
Prior art keywords
output
synchronization
signal
bit
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55146673A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5769950A (en
Inventor
Keiichi Yamauchi
Ryuichi Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP55146673A priority Critical patent/JPS5769950A/ja
Publication of JPS5769950A publication Critical patent/JPS5769950A/ja
Publication of JPS6343940B2 publication Critical patent/JPS6343940B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP55146673A 1980-10-20 1980-10-20 Synchronizing detection circuit Granted JPS5769950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55146673A JPS5769950A (en) 1980-10-20 1980-10-20 Synchronizing detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55146673A JPS5769950A (en) 1980-10-20 1980-10-20 Synchronizing detection circuit

Publications (2)

Publication Number Publication Date
JPS5769950A JPS5769950A (en) 1982-04-30
JPS6343940B2 true JPS6343940B2 (enrdf_load_stackoverflow) 1988-09-01

Family

ID=15413010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55146673A Granted JPS5769950A (en) 1980-10-20 1980-10-20 Synchronizing detection circuit

Country Status (1)

Country Link
JP (1) JPS5769950A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5922458A (ja) * 1982-07-29 1984-02-04 Iwatsu Electric Co Ltd デ−タ収録方式
JPS6331329A (ja) * 1986-07-25 1988-02-10 Nec Corp 制御信号検出保護回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592414B2 (ja) * 1977-02-12 1984-01-18 富士通株式会社 積分形保護回路

Also Published As

Publication number Publication date
JPS5769950A (en) 1982-04-30

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