JPS6342920B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a remote monitoring and control device.

A remote monitoring and control device is a device that monitors and controls distant equipment via a small number of signal transmission paths, and therefore encodes monitoring and control data and transmits it at a predefined rate. Therefore, there is usually a time delay of several hundred milliseconds to several seconds in data transmission, but there is no need for high-speed signal transmission between the master station and slave stations because there is a protective device that operates reflexively on the distant equipment side. and
This transmission time delay usually does not pose a problem.

However, recently, remote monitoring and control systems have become more sophisticated.
As the area expands, even if each remote facility is protected by protective devices installed at each location as before, there is a need to accurately record and analyze their operating times and order, and there is a need to collect measurement data. In this case, a problem has arisen in that the data collection points of different slave stations must be collected at the same time.

To solve these problems, a clock circuit is installed in the remote monitoring and control device, and the operation of the protection device and equipment is transmitted along with this time code.Also, all slave stations are measured at the same time at a predetermined time. One possible method is to store the data in memory and then transmit it to the master station.

What is important in this case is that the clock circuits of the master and slave stations are synchronized within a practically acceptable error range.

It is necessary to suppress errors within a few milliseconds when analyzing equipment operations and data in power systems, and for this reason, conventionally, in addition to data transmission for remote monitoring and control, a dedicated system was used to synchronize parent and child clock circuits. It was necessary to use a signal transmission path and a code transmitting/receiving circuit.

The present invention provides a device that can synchronize parent and child clock circuits using only a signal transmission path and a code transmission/reception circuit for normal remote monitoring control without using a special signal transmission path or code transmission/reception circuit. It is.

FIG. 1 is a diagram showing an example of a block diagram of a remote monitoring and control device according to the present invention.

In FIG. 1, O is the master station of the remote monitoring and control device;
1, 2, . . . are slave stations. In master station O, GP is a display panel that displays the status of each slave station, CD is a control console that issues control commands to each slave station, TW is a typewriter that records operations and data, and CPU ₀ is an arithmetic processing circuit. , DO ₀ is the output circuit, DI ₀ is the input circuit, TC
is the typewriter control circuit, CL ₀ is the master clock circuit,
TR ₀ is a code transmitting/receiving circuit, and MD ₀ is a modulation/demodulation circuit.

In addition, in slave station 1, CPU ₁ is an arithmetic processing circuit,
MD ₁ is the modulation/demodulation circuit, TR ₁ is the code transmitting/receiving circuit, DI ₁
is the input circuit, DO ₁ is the output circuit, and CL ₁ is the slave clock circuit.

The slave station 2 has a similar configuration except that the suffix of the code of each circuit is changed from 1 to 2.

L ₁ and L ₂ are signal transmission paths connecting the master station O and the slave stations 1 and 2, respectively.

Next, regarding the operation of FIG. 1, FIG. 2 shows a time chart of codes transmitted and received between the master station and the slave station.
This will be explained using FIGS. 3 and 4.

FIG. 2 is a diagram showing a time chart of codes sent and received when performing normal remote monitoring control, FIG. 3 is a diagram showing a time chart of codes sent and received when synchronizing the slave clock circuit with the master clock circuit, FIG. 4 is a diagram showing a time chart of codes transmitted and received when synchronizing the slave clock circuit with the master clock circuit and sending back the quality of the result to the master station.

First, the operation when performing normal remote monitoring control will be explained.

In Figure 1, the arithmetic processing circuits of slave stations 1 and 2
CPU ₁ and CPU ₂ constantly scan the status of the monitored equipment input to input circuits DI ₁ and DI ₂ of each station, and store the latest status. The arithmetic processing circuit CPU0 of the master station ₀ periodically creates a code for a data request for each slave station, and provides it to the code transmitting/receiving circuit _TR0 . The given code is a so-called parallel code in which each bit exists in parallel, and the code transmitter/receiver circuit TR ₀
sends out this signal sequentially in time, converts it into a so-called serial code, and supplies it to the modulation/demodulation circuit MD ₀ . The modulation/demodulation circuit MD ₀ modulates this into a form that is compatible with the signal transmission path and is less susceptible to noise, such as a frequency shift heying (FSK) signal in the voice frequency band, and transmits it to the signal transmission paths L ₁ and L. ₂ to slave stations 1 and 2. In slave stations 1 and 2, modulation/demodulation circuits MD ₁ and MD ₂ respectively demodulate the signal arriving from the master station and transmit it to code transmitting/receiving circuits TR ₁ and TR ₂ . Code transmitter and receiver circuits TR ₁ and TR ₂
returns the incoming serial code to parallel code and transmits it to the arithmetic processing circuits CPU ₁ and CPU ₂ . Arithmetic processing circuit
CPU ₁ and CPU ₂ determine whether the code of the incoming data request belongs to their own station, and if it is their own station, they send and receive the code of the latest status of their own control equipment and measured values that they have memorized. Give to circuit TR ₁ or TR ₂ . The following is transmitted in the opposite direction from the data request signal from the code transmitting/receiving circuit TR ₁ or TR ₂ to the modulation/demodulation circuit MD ₀ of the master station O via the modulation/demodulation circuit MD ₁ or MD ₂ and the signal transmission line L ₁ or L ₂ . , the code transmitting/receiving circuit TR reaches ₀ . The code transmitting/receiving circuit TR ₀ transmits the received code to the arithmetic processing circuit CPU ₀ , _which stores it and displays it on the display panel via the output circuit DO ₀ .
Make GP display.

A time chart of code transmission and reception performed in the above operation is shown in the first half of FIG. 0, 1, and 2 at the left end of the figure indicate the station numbers in FIG. 1, respectively. First, the data request code of slave station 1 is sent from master station O.
Send DRQ ₁ . The arrow pointing diagonally downward represents the status of signal transmission, indicating that the signal arrives at slave stations 1 and 2 after a time delay of τmsec. Strictly speaking, the signal transmission time delays to slave stations 1 and 2 are different, but the time delays are mainly caused by the modulation and demodulation circuits MD ₀ , MD ₁ , MD ₂
The delay caused by the signal transmission paths L ₁ and L ₂ can usually be ignored compared to the former, so when modulation and demodulation circuits with the same characteristics are used, the signals arrive at slave stations 1 and 2. The times can be considered to be almost the same.

The arithmetic processing circuit CPU ₁ of the slave station 1 determines that the code of the incoming data request is that of its own station, and transmits the latest data. This signal DOT ₁
It also arrives at the master station O after a time delay of τmsec, as shown by the dotted line going diagonally upward. The arithmetic processing circuit CPU ₀ of the master station O stores this as described above and outputs the output circuit DO _0.
Display it on the display panel GP via . Next, the arithmetic processing circuit CPU ₀ is a data request code for slave station 2.
Create DRQ ₂ and send it to code transmitting/receiving circuit TP ₀ ,
The same operation as for slave station 1 is performed.

Next, when controlling the equipment of slave station 1 from master station O, select the relevant equipment on the control console CD, perform control operations such as turning on and off, and this signal will be input to input circuit DI ₀ and processed. In response to this, the circuit CPU ₀ creates a corresponding code, and causes the code transmitting/receiving circuit TR ₀ to transmit the code OPE ₁ of "Slave station 1 device control" shown in the second half of FIG. When this code arrives at slave stations 1 and 2 and is received by their respective code transmitting/receiving circuits TR ₁ and TR ₂ , the arithmetic processing circuit CPU ₁ of slave station 1 determines that it is a control code for its own station and the corresponding equipment. , gives a control command to the corresponding device via the output circuit DO ₁ shown in FIG. Then, the response of the corresponding device is confirmed via the input circuit DI ₁ , and a response code RES ₁ is created and transmitted to the master station O. The master station O confirms the response of the corresponding device based on the response from the slave station 1 and displays it on the display panel GP. Thereafter, the arithmetic processing circuit CPU ₀ returns to the slave station data request operation, creates and sends a data request code DRQ ₁ to the slave station 2.

The above is the operation of normal remote monitoring and control using the time chart shown in FIG. 2, and in the conventional remote monitoring and control system, there was no particular practical problem with the above-mentioned monitoring and controlling operation.

However, as systems have recently become more sophisticated and wider in area, they are not only capable of simply monitoring and controlling distant equipment, but also recording and analyzing the operating order of equipment in different locations when an abnormality occurs, and collecting measurement values at the same time. The need has arisen.

For this reason, the master station O is provided with a _master clock circuit CL, and the slave stations 1 and 2 are provided with slave clock circuits CL ₁ and CL ₂ , respectively.
When an abnormality occurs, the arithmetic processing circuits CPU ₁ and CPU ₂ add and store the time signals from the child clock circuits CL ₁ and CL ₂ to the input signals from the input circuits DI ₁ and DI ₂ , respectively, and respond to a data request from the master station O. The arithmetic processing circuit CPU ₀ of the master station O edits the data in chronological order and records it on the typewriter TW via the typewriter control circuit TC, or sends data including time information to the slave station 1. and 2 arithmetic processing circuits
CPU ₁ and CPU ₂ store measurement data at the same time determined in advance and send it to the master station O, and the arithmetic processing circuit CPU ₀ of the master station O analyzes the status of the system to be monitored and controlled based on these data. began to be carried out.

In this case, what is important is that the clock circuits of the master station and each slave station are synchronized within a practical range, but as mentioned above, in the past, dedicated signal transmission paths and code transmission/reception circuits were used for this purpose. I needed it.

This invention eliminates this drawback, and its basic operation will be explained with reference to FIG.

0, 1, and 2 at the left end of Fig. 3 are the same as those in Fig. 2, and first the data request DRQ ₂ to the slave station is
A time chart of data transmission DOT ₂ based on this is drawn, which is exactly the same operation as explained in Fig. 2.

Then, at the time of setting the time (for example, once a day at 0:00 AM)
As the time approaches (time), the arithmetic processing circuit CPU ₀ of the master station O transmits a time setting code TSE that encodes the time to (for example, 0:00:00:00:00 milliseconds) to be set. Each slave station 1 and 2 receives this, and the arithmetic processing circuits CPU ₁ and CPU ₂ memorize the time to to be set and wait for the next arriving setting command signal SET.
The arithmetic processing circuit CPU ₀ of the master station O monitors the output of the master clock circuit CL ₀ and issues a setting command signal SET at a time point before the transmission delay time τ msec from to. Setting command signal
SET arrives at slave stations 1 and 2 after a delay of τmsec, that is, at time to, and with this arrival, the arithmetic processing circuit
CPU ₁ and CPU ₂ are child clock circuits CL ₁ and
Set CL ₂ to time to.

As described above, the master clock and each slave clock are synchronized, and then, as shown in the second half of FIG. 3, normal data request and transmission operations and control operations as necessary are performed.

The above method simply sets the time of the child clock, but if the setting command signal is not transmitted correctly due to noise etc., the correct time will not be set.
It is necessary to determine this, send the result back to the master station, and have it perform the time setting operation again if necessary.

FIG. 4 is a time chart according to the present invention showing the operation in this case.

The transmission and reception of the time setting code to is the same as in Fig. 3, but the setting command signal BT is not a simple pulse but a predetermined bit pattern (for example, |○|○|○
｜). Each slave station 1 and 2 sets the slave clock circuits CL ₁ and CL ₂ at the rising edge of the first bit of this bit pattern, but subsequently performs arithmetic processing on the bit pattern received by the code transmitter/receiver circuits TR ₁ and TR ₂ . circuit CPU ₁ and
The CPU ₂ checks whether or not the bit pattern is a predetermined bit pattern, and if the determination result is good, it is determined that the child clock was set at the correct time. Next, the code OK ₁ ? is checked from the master station O to each slave station 1 and 2 to see if the settings are correct. , OK ₂ ? and each slave station replies with the judgment results OK ₁ and OK ₂ . If everything is good, the routine goes to normal operation as shown at the end of FIG. 4, and if there is a negative station, the setting operation is repeated again.

If the operation shown in FIG. 4 is carried out, an even more reliable device can be obtained.

Note that FIGS. 1, 2, 3, and 4 are examples given to explain the configuration and operation of the present invention in an easy-to-understand manner. Of course, the present invention can also be applied to a system in which station data signals are constantly transmitted cyclically regardless of requests from the master station.

In addition, in special cases where the time is not set on all stations at the same time but on each slave station individually, and in special cases where the transmission time delay varies depending on the slave station, τ in Figures 3 and 4 can be changed for each slave station. Of course, it can be implemented.

Furthermore, since the setting command signal BT in Fig. 4 has information at the time of its rising edge, conversely, the last bit of the time setting code is extended and dropped at the time of to-τ (i.e., at the falling point of the setting command signal). It is also possible to set the However, extending the last bit is the opposite of stopping the code, and is still the same as stopping the transmission of the temporary significant code after transmitting the code indicating the time to be set.

In addition, in the above embodiment, the time setting signal is sent from the master station to the slave station before the transmission delay time τ from the set time to,
It is assumed that the clock circuit of the slave station is set to the set time to, but the master station sends a time setting signal to the slave station at the setting to, and the slave station sets the time to the time obtained by adding the transmission delay time τ to the above setting to. You may do so. In this case, the transmission delay time τ can be set to a different value for each slave station.

As described above, according to the present invention, the time setting signal of a predetermined pattern is transmitted from the master station to the slave station via the signal transmission path, and the clock circuit of the slave station is controlled by the time setting signal. The time is set in consideration of the transmission delay time of the transmission line, and it is determined whether or not the time setting signal has a predetermined pattern, and the result is sent to the master station, so the time can be set accurately. It is possible to confirm whether or not the time has been set, and to set the time with high reliability.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a block diagram of a remote monitoring and control device according to the present invention, and FIGS. It is a diagram showing a chart. In the figure, O is the master station, 1 and 2 are slave stations, L ₁ ,
L ₂ is a signal transmission path, TR ₀ , TR ₁ , TR ₂ are transmitting/receiving circuits, CL ₀ , CL ₁ , CL ₂ are time circuits, τ is transmission delay time, to is a predetermined time, SET, BT are time setting signals, OK ₁ and OK ₂ are transmission signals of the determination results.

Claims (1)

[Claims] 1. In devices that control and monitor devices installed in slave stations from a master station, signal transmission paths that have predetermined transmission delay time characteristics and that transmit signal data between the master station and slave stations, the master station, and Each of the slave stations includes a transmitting/receiving circuit for transmitting and receiving signals to and from the signal transmission path, and a time circuit is provided in each of the master station and the slave station to synchronize the master station and the slave stations in terms of time. When the time circuit of the master station reaches a predetermined time, the master station transmits a time setting signal of a predetermined pattern to the slave station via the signal transmission path and the transmitting/receiving circuit, and the clock circuit of the slave station is activated by the time setting signal. The time is set in consideration of the predetermined transmission delay time, the slave station determines whether or not the time setting signal follows a predetermined pattern, and the result is transmitted to the master station through the signal transmission path and the transmitting/receiving circuit. A remote monitoring and control device characterized in that it transmits data via.