JPS634275B2 - - Google Patents

Info

Publication number
JPS634275B2
JPS634275B2 JP8652481A JP8652481A JPS634275B2 JP S634275 B2 JPS634275 B2 JP S634275B2 JP 8652481 A JP8652481 A JP 8652481A JP 8652481 A JP8652481 A JP 8652481A JP S634275 B2 JPS634275 B2 JP S634275B2
Authority
JP
Japan
Prior art keywords
layer
conductor
etching
conductor pattern
mgf
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8652481A
Other languages
Japanese (ja)
Other versions
JPS57203282A (en
Inventor
Akira Hirano
Hideki Fujiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8652481A priority Critical patent/JPS57203282A/en
Publication of JPS57203282A publication Critical patent/JPS57203282A/en
Publication of JPS634275B2 publication Critical patent/JPS634275B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/08Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は導体パターンへの窓あけに際して導体
の損傷を防いでドライエツチングを行なう磁気バ
ブルメモリチツプの製造方法に関する。 磁気バブルメモリチツプは非磁性ガーネツトで
あるガドリニウムガリウムガーネツト
(Gd3Ga5O12)の上に必要とする磁性を備えたガ
ーネツト結晶薄膜をエピタキシヤル成長させ、こ
の上にポリイミド系樹脂或はSiO2層などをスペ
ーサとして導体パターンと駆動パターンの形成を
行いこの上にSiO2層などを保護層として設けた
後に電極部窓あけを行い個別に切断することによ
りメモリチツプが製造されている。 本発明はかゝるメモリチツプにおいて外部とり
出し電極として必要な電極部窓あけを導体パター
ンの損傷を防いで行う方法に関するもので以後従
来方法と比較し乍ら図面により説明する。 第1図は従来の方法により窓明けされている磁
気バブルメモリチツプの一実施例についての断面
構造で磁性ガーネツト結晶膜1の上には第1絶縁
層として厚さ約1000ÅのSiO2(酸化硅素)層2が
あり、この上に厚さ約3500ÅのAu(金)からなる
導体層3がこの上下に厚さ約200ÅのTaMo(タン
タル・モリブデン)合金層4を伴つた形でパター
ンが形成されている。 こゝでTaMo合金層は基板およびAu導体との
接着の向上と導体金属原子の拡散を防ぐためのも
のでこの金属に限定する必要はなく、Ta又はMo
など単独にまたTi(チタン)・Pt(白金)の組合せ
で用いられることもある。 次にこの上に層間絶縁として厚さ約3500Åの
SiO2絶縁層5を介して厚さ約4000Åのパーマロ
イよりなる駆動パターン6が設けられ更にこの上
に保護層7をつけてチツプの層構成が終り、その
後電極部8の窓あけが行われる。 こゝで磁気バブルメモリチツプや半導体ICの
ような微細パターンの形成にはパターン精度が高
いことおよびサイドエツチング現象を伴はないこ
とからドライエツチング技術が用いられている。 この技術の特徴は低圧下で導入されたハロゲン
元素などを含むガスを13.56MHz等の高周波でグ
ロー放電を起し、これによる低温プラズマにより
生成されたラジカル(遊離基)が表面物質と反応
して揮発性生成物を作り、これが排気されてエツ
チングが進行するものであり、放電様式及び反応
様式によりプラズマエツチング、ケミカルドライ
エツチング、リアクテイブイオンエツチング、な
どに分けられ、それぞれエツチングすべき基板料
により使い分けられているが、SiO2層をエツチ
ングする本目的にはプラズマエツチングが一般に
用いられている。 第3図はバレルタイプのプラズマエツチング装
置の構成図でAはこの断面図、Bはこの側面図で
あり、CF4(四弗化炭素)とO2(酸素)との混合ガ
スを送入孔9より供給し排気孔10より排気する
ことにより反応管11の真空度を3torrに保ち、
高周波電極12に13.56MHzの高周波を加えてグ
ロー放電を起させたものでエツチングすべき試料
ウエハーはホルダー14にのせて反応管11の中
央部に保持されている。 かゝる場合CF4とO2とはプラズマ放電により CF4→F*+CF3 * O2+e→O2 *+e こゝで*印はラジカルを表わす。 を発生するが、この場合エツチングに有効なラジ
カルはF*であり SiO2+4F*→SiF4+O2 の反応によりSiF4を生じガスとして排気されるこ
とによりエツチングが進行する。 またAu導体層の上に設けられているTaMo合
金層もこれと同時にエツチングされるがこれは
Ta及びMoがF*と反応して Ta+5F*→TaF5 Mo+6F*→MoF6 を生ずるためである。 こゝでTaMo合金のエツチングが容易に起る理
由は生成される弗化物融点および沸点が第1表の
ように低いことによる。
The present invention relates to a method of manufacturing a magnetic bubble memory chip in which dry etching is performed while preventing damage to the conductor when opening a window in the conductor pattern. Magnetic bubble memory chips are made by epitaxially growing a garnet crystal thin film with the required magnetism on gadolinium gallium garnet (Gd 3 Ga 5 O 12 ), which is a non-magnetic garnet, and then depositing polyimide resin or SiO on this. Memory chips are manufactured by forming a conductor pattern and a driving pattern using a spacer such as 2 layers, and then forming a protective layer such as an SiO 2 layer on top of this, making a window in the electrode area and cutting the chips individually. The present invention relates to a method of opening a window in an electrode portion necessary for an externally extending electrode in such a memory chip while preventing damage to the conductor pattern, and will be explained below with reference to the drawings in comparison with a conventional method. FIG. 1 shows a cross-sectional structure of an embodiment of a magnetic bubble memory chip which has been opened using a conventional method. On top of a magnetic garnet crystal film 1, a first insulating layer of SiO 2 (silicon oxide) with a thickness of approximately 1000 Å is deposited. ) layer 2, on which a pattern is formed with a conductor layer 3 made of Au (gold) about 3500 Å thick and TaMo (tantalum molybdenum) alloy layers 4 about 200 Å thick above and below this. ing. Here, the TaMo alloy layer is used to improve adhesion between the substrate and the Au conductor and to prevent the diffusion of conductor metal atoms, and it is not necessary to limit it to this metal.
It may be used alone or in combination with Ti (titanium) and Pt (platinum). Next, a layer of about 3500 Å thick is placed on top of this as interlayer insulation.
A drive pattern 6 made of permalloy with a thickness of about 4000 Å is provided via the SiO 2 insulating layer 5, and a protective layer 7 is further applied thereon to complete the layer structure of the chip, after which the electrode portion 8 is opened. Here, dry etching technology is used to form fine patterns such as magnetic bubble memory chips and semiconductor ICs because it has high pattern accuracy and does not involve the side etching phenomenon. The feature of this technology is that a gas containing halogen elements introduced under low pressure is used to generate a glow discharge at high frequencies such as 13.56 MHz, and the radicals generated by the low-temperature plasma react with surface materials. Etching proceeds by producing volatile products and exhausting them. Depending on the discharge mode and reaction mode, etching is divided into plasma etching, chemical dry etching, reactive ion etching, etc., and each method is used depending on the substrate material to be etched. However, plasma etching is generally used for this purpose to etch the SiO 2 layer. Figure 3 is a configuration diagram of a barrel-type plasma etching apparatus, where A is a cross-sectional view and B is a side view. The degree of vacuum in the reaction tube 11 is maintained at 3 torr by supplying from 9 and exhausting from the exhaust hole 10.
A sample wafer to be etched is placed on a holder 14 and held in the center of the reaction tube 11 by applying a high frequency of 13.56 MHz to the high frequency electrode 12 to cause glow discharge. In such a case, CF 4 and O 2 are generated by plasma discharge as follows: CF 4 →F * +CF 3 * O 2 +e→O 2 * +e Here, the * mark represents a radical. However, in this case, the effective radical for etching is F * , and the reaction of SiO 2 +4F * →SiF 4 +O 2 produces SiF 4 , which is exhausted as a gas, thereby promoting etching. Additionally, the TaMo alloy layer provided on the Au conductor layer is also etched at the same time.
This is because Ta and Mo react with F * to produce Ta+5F * → TaF 5 Mo+6F * → MoF 6 . The reason why TaMo alloy is easily etched is that the melting point and boiling point of the produced fluoride are low as shown in Table 1.

【表】 そこでこのようなプラズマエツチングによる窓
あけ処理で絶縁膜を構成しているSiO2層5,7
が除去されるのみでなく、Au導体パターン3の
上に形成されているTa・Mo合金層4も除去され
る結果Au導体パターンが直接F*およびO*などに
曝されて損傷が起ることになる。 この理由はF*が触媒として働らきAuとO*とが
反応するためと考えられている。 そこで、かゝるAu導体パターン3の損傷の防
止法として、導体パターン上にCr2O3(酸化クロ
ーム)の薄層を設けることもなされているがバレ
ルタイプの装置を用いる限りその効果は不充分で
ある。 本発明はバレルタイプのプラズマエツチングに
より絶縁層の穴あけ処理を行う際、Au導体パタ
ーンに損傷を与えないでエツチングを行うことを
目的としそのため導体パターンの上にエツチング
速度の小さいMgF2(弗化マグネシウム)層を予
め設けておき、穴あけ処理後に穴あけ部に残存し
ているMgF2を除去して電極部を露出させること
を本旨としている。 こゝでMgF2をAu導体パターンの保護層として
選んだ理由はMgF2は融点1260℃、沸点2260℃と
頗る高く、そのためエツチングされにくいことは
外ならない。 第2図は本発明を用いて第1図と同一のパター
ン形成および穴あけを行つた実施例の断面構造で
MgF2層15は抵抗加熱方法により約300Åの厚
さにAu導体層3上のTaMo保護層4の上に形成
した。 次に穴あけ法としては従来と同様に5%のO2
ガスを含むCF4ガスを用い真空度3torrの条件で
バレルタイプの装置を用いてプラズマエツチング
を行つた。 この場合、SiO2層のエツチング速度は約2000
Å/分であるのに対しMgF2層は5Å/分以下で
あつて殆んどエツチングされず、従つて穴あけ部
導体パターンの電極部8が損傷を受けることはな
い。 次にこの部分に残つているMgF2層15は
HNO3(硝酸)水溶液中に浸漬することにより容
易に除去することができる。 なおMgF2層は上記のようにプラズマエツチン
グ中保護膜として適しているだけでなく導体パタ
ーン形成の際の反射防止膜としても効果がある。 すなわち第1絶縁層2を基けた磁性ガーネツト
結晶膜1の上に導体パターン形成のための金属蒸
着を行ない、ホトレジスト膜塗布後に光照射して
必要なレジストパターンを形成する場合に精度の
高いパターンを作るには基板の反射率が低い状態
が望ましく本発明にかゝるMgF2を用いる場合は
これが非金属化合物であるため反射率は低く、そ
のためこの厚さを適当に選ぶとプラズマエツチン
グの保護層のみでなく導体パターン形成の際の反
射防止膜としても有効である。 本発明はバレルタイプのプラズマエツチング装
置を用いてSiO2保護層を穴あけを行う場合に下
層の導体を損傷することなく行うもので、本発明
の実施により従来と方法を変えずに目的を達する
ことができた。なお本実施例はAu導体の場合で
あるが、Cuについても適用できる。またMgF2
導体金属膜上の全面に亘つて蒸着させたが窓明け
が必要な電極部の近傍のみに限定して蒸着しても
よく、穴あけ後残存するMgF2の除去方法も化学
的エツチングに限られず「特許請求の範囲」内に
おいて適宜変形実施し得るものである。
[Table] Therefore, the SiO2 layers 5 and 7 that constitute the insulating film are
Not only is this removed, but the Ta/Mo alloy layer 4 formed on the Au conductor pattern 3 is also removed, resulting in the Au conductor pattern being directly exposed to F * and O * , resulting in damage. become. The reason for this is thought to be that F * acts as a catalyst and causes Au and O * to react. Therefore, as a method to prevent such damage to the Au conductor pattern 3, a thin layer of Cr 2 O 3 (chromium oxide) has been provided on the conductor pattern, but this method is ineffective as long as a barrel type device is used. That's enough. The purpose of the present invention is to perform etching without damaging the Au conductor pattern when drilling holes in the insulating layer by barrel - type plasma etching. ) layer is provided in advance, and after drilling, the MgF 2 remaining in the hole is removed to expose the electrode section. The reason why MgF 2 was chosen as the protective layer for the Au conductor pattern is that MgF 2 has an extremely high melting point of 1260°C and boiling point of 2260°C, so it is obvious that it is difficult to be etched. Figure 2 shows a cross-sectional structure of an example in which the same pattern formation and hole drilling as in Figure 1 were performed using the present invention.
The MgF2 layer 15 was formed on the TaMo protective layer 4 on the Au conductor layer 3 to a thickness of about 300 Å using a resistance heating method. Next, as for the drilling method, 5% O 2 was used as before.
Plasma etching was performed using a barrel type device using CF 4 gas containing gas at a vacuum level of 3 torr. In this case, the etching rate of the SiO 2 layer is approximately 2000
In contrast, the MgF 2 layer is etched at a rate of 5 Å/min or less, and is hardly etched, so that the electrode portion 8 of the perforated conductor pattern is not damaged. Next, the MgF 2 layer 15 remaining in this part is
It can be easily removed by immersion in an aqueous HNO 3 (nitric acid) solution. Note that the MgF 2 layer is not only suitable as a protective film during plasma etching as described above, but also effective as an antireflection film during conductor pattern formation. That is, when metal vapor deposition is performed to form a conductor pattern on the magnetic garnet crystal film 1 based on the first insulating layer 2, and the required resist pattern is formed by irradiation with light after coating a photoresist film, a highly accurate pattern is formed. It is desirable for the substrate to have a low reflectance.When MgF 2 is used in the present invention, the reflectance is low because it is a non-metallic compound, so if the thickness is selected appropriately, it will serve as a protective layer for plasma etching. It is also effective as an antireflection film when forming conductor patterns. The present invention uses a barrel type plasma etching device to drill holes in the SiO 2 protective layer without damaging the underlying conductor, and by carrying out the present invention, the purpose can be achieved without changing the conventional method. was completed. Note that although this example deals with the case of an Au conductor, it can also be applied to Cu. Furthermore, although MgF 2 was deposited over the entire surface of the conductive metal film, it may also be deposited only in the vicinity of the electrode parts where openings are required, and chemical etching can also be used to remove MgF 2 that remains after drilling. The present invention is not limited to the above, and may be modified and implemented as appropriate within the scope of the claims.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は磁気バブルメモリチツプにおいて電極
部の穴あけを従来方法で行う場合の断面構造図、
第2図は本発明の穴あけを行つた場合の断面構造
図、また第3図は穴あけに使用するバレル形プラ
ズマエツチング装図でAは断面図、Bは側面図で
ある。 図において、1は磁性ガーネツト膜、2,5,
7はSiO2絶縁層、3はAu層、4はTa・Mo層、
8は電極部、15はMgF2保護層。
Figure 1 is a cross-sectional structural diagram of a magnetic bubble memory chip in which electrode holes are formed using the conventional method.
FIG. 2 is a cross-sectional structural view of the hole-drilling device according to the present invention, and FIG. 3 is a diagram of a barrel-shaped plasma etching device used for the hole-drilling, with A being a sectional view and B being a side view. In the figure, 1 is a magnetic garnet film, 2, 5,
7 is a SiO 2 insulating layer, 3 is an Au layer, 4 is a Ta/Mo layer,
8 is an electrode part, and 15 is a MgF 2 protective layer.

Claims (1)

【特許請求の範囲】[Claims] 1 磁気バブルメモリチツプの導体部窓明け工程
において、窓あけをドライエツチングにより行う
場合、予め導体パターンを形成する金属層上に弗
化マグネシウムよりなる保護層を設け、窓あけ処
理後この部分に残存する弗化マグネシウムを除去
することを特徴とする磁気バブルメモリチツプの
製造方法。
1 In the conductor window opening process of a magnetic bubble memory chip, when opening the window by dry etching, a protective layer made of magnesium fluoride is provided in advance on the metal layer forming the conductor pattern, and the protective layer that remains in this part after the window opening process is A method for manufacturing a magnetic bubble memory chip, characterized by removing magnesium fluoride.
JP8652481A 1981-06-05 1981-06-05 Production of magnetic bubble memory chip Granted JPS57203282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8652481A JPS57203282A (en) 1981-06-05 1981-06-05 Production of magnetic bubble memory chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8652481A JPS57203282A (en) 1981-06-05 1981-06-05 Production of magnetic bubble memory chip

Publications (2)

Publication Number Publication Date
JPS57203282A JPS57203282A (en) 1982-12-13
JPS634275B2 true JPS634275B2 (en) 1988-01-28

Family

ID=13889370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8652481A Granted JPS57203282A (en) 1981-06-05 1981-06-05 Production of magnetic bubble memory chip

Country Status (1)

Country Link
JP (1) JPS57203282A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62183091A (en) * 1986-02-07 1987-08-11 Hitachi Ltd Manufacture of magnetic bubble memory element

Also Published As

Publication number Publication date
JPS57203282A (en) 1982-12-13

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