JPS634238Y2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a speech synthesis control device, and particularly to a speech synthesis device that controls the output speed of synthesized speech information.

<Prior art> In general, a speech synthesis device stores the steps and basic speech segments necessary for speech synthesis of a predetermined vocabulary in a memory in advance, and performs a specification for specifying specific speech information in the memory. It performs speech synthesis of the vocabulary based on the code information.

By sending the designated code information to the speech synthesizer in a predetermined order, complex words can be uttered.

Previously, the applicant configured a speech synthesis device that outputs predetermined speech information to be output by combining a plurality of speech segments so that when one phoneme is uttered, a silent section is also output together with it, We proposed a speech synthesis method that can produce natural speech output simply by combining various phonemes (Patent Application No. 54-39050).
issue).

The applicant has also proposed a speech synthesizer that can change the speech rate of synthesized speech without changing the sound quality, that is, without changing the pitch period (Japanese Patent Application No. 56119/1982).

<Purpose of the invention> The present invention is designed to perform speed control by changing the output speed, ie, the generation speed, of synthesized audio information using speed control code information.

One method of controlling speed using speed control code information is to include a silent section in predetermined audio information to be output, and to change this silent section using the speed control code information to control the output speed of the audio information. This is what I did.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of a speech synthesis control device according to the present invention.

In the figure, K is a key input device with numeric keys, alphanumeric keys, and other various keys, and EC
is an encoder that converts key input information,
CPU ₁ is read-only memory (ROM ₁ )
A central processing unit (processor) that controls the system according to instructions stored in advance.
ROM ₁ is a read-only memory that stores instructions or code information necessary for speed control.
RAM is a random access memory that stores key input information or processing information based on this information. DSC is a display control unit that controls the display unit DISP, and DISP is a display unit such as a liquid crystal display or a CRT display. A is a register that temporarily stores specification code information for specifying specific audio information in the audio memory input from a key input device or speed control code information stored in ROM ₁ memory, and JA is a register A. This circuit determines whether the code information temporarily stored in the 8-bit speed control code is either a designated code or a speed control code.For example, as described later, in FIG. If it is "1", it is determined that it is speed control code information, and if it is not, it can be determined that it is designated code information.

When it is determined that the code is a speed control code, the jump circuit JA outputs an H level signal, and on the other hand, when it is determined that the code is designated code information, the jump circuit JA outputs an L level signal. Outputs the signal.

IC is the input control section and IG is the gate.

Then, when the signal output from the jersey circuit JA is at H level, the input control unit IC receives the signal and temporarily stores the speed control code information of the lower two bits of the contents of the register A into the register B. . Further, the H level signal outputted from the jump circuit JA is inverted and becomes the L level, thereby rendering the gate IG non-conductive. As a result, the speed control code information output from the register A does not flow to the input port D side.

On the other hand, when the signal output from the jump circuit JA is at the L level, the signal is inverted and becomes the H level, making the gate IG conductive. As a result, the designation code information output from the register A flows to the input port D side. In addition, C is a memory that permanently stores the speed parameters necessary for normal speed control, regardless of the speed control code information stored in ROM ₁ memory. The speaking speed of the audio data is controlled based on the speed parameter. This parameter can be temporarily stored in register B via gate G by an auto clear signal (ACL) generated when the power is turned on, for example, and the fixedly stored speed parameter can be called the initial speed parameter. can. The VSC is a speech synthesizer whose details are shown in Figure 4, which will be described later.Port D inputs the specified code information, port S inputs the speed control parameter, and the voice synthesizer specified by the input specified code is used. They each have a port E that outputs an end signal (END code) when the audio output of specific audio information in the audio memory ends.

In addition. For example, in the memory C mentioned above, the initial code is S.CORD(1) (MIDDLE) shown in Figure 3.
The lower two bits “01” of “11111101” can be stored.

Therefore, unless a speed is specified, the sound will be made using this parameter. SP is a speaker for vocalization.

FIG. 2 is a flowchart of an embodiment in which the speaking speed of audio information is changed in the system of the present invention.

To explain the operation, first, in step n1, it determines whether or not a key has been pressed, and waits until a key is input. When a key is pressed, the CPU
The processor transfers the contents of the key input, a designation code (W.CORD) corresponding to a so-called symbol, to register A (n2). The voice synthesizer VSC receives the designated code at input port D and outputs it by voice synthesis (see Figures 1 and 4). When the audio output ends, the audio synthesizer VSC outputs an END code indicating the end from the output port E to the CPU ₁ processor, and the CPU ₁ determines the END code. Step n3 is a step to determine this END code, and here, in particular, it is determined whether a key input was made before the END signal was determined by CPU ₁ , or whether a key input was performed after the END signal was determined by CPU 1. It has a speed control feature.

In other words, the embodiment is an example in which the faster the key input operation is performed, the faster the voice production speed is.

Therefore, if the next key input is not made by the time the CPU ₁ processor determines the END code, it waits for the next key input at step n4 (n4), and if there is a key input here, the program executes the program as shown in Figure 3, for example. Speed control code S・CORD(1) stored in ROM ₁
(MIDDLE) Transfer "11111101" to the A register (n5), transfer the specified code (W.CORD) corresponding to the symbol of the input key to the A register, and then execute audio output.

On the other hand, if there is a key input before CPU ₁ determines the END code (n6), for example, the speed control code of ROM ₁ memory S・CORD(2) (FAST)
After transferring “11111110” to A register (n7),
The designated code corresponding to the symbol of that key is transferred to the A register.

In other words, the speed control code S・CORD(2) is S・
This is a code for producing voice faster than CORD(1).

The speech speed can be controlled in the manner described above.

FIG. 3 is a diagram showing an example of speed control code information and pause sound code information.

The speed control code can be controlled in 4 stages, and the memory
Stored in ROM ₁ as an 8-bit code.

The upper 6 bits of this code are the code that is input to the A register and determined by the jersey circuit JA as a speed control code, and the lower 2 bits are the B
It is stored as a speed control code parameter S in a register.

In addition, the rest sound code can be controlled in four stages (0 to 3), and will be explained in detail in Figure 4, which will be described later.
It is stored in the ROM ₂ and is uniformly determined based on the CPU ₂ processor from the specified code information input from the input port D of the speech synthesizer VSC and the speed control cobo parameter input from the input port S.

The speech rate of audio information is controlled by the silent section code (which can be stored in ROM ₁ ) output from the CPU ₁ processor, or the time (length) of the silent sections that are stored in ROM ₂ memory and make up each vocabulary. It is carried out by

For example, if speed control code B is specified, the silent period is in four stages from 0 to 3, that is, 140 msec.
(0 step), 120msec (1 step), 100msec
(2 steps) and 80 msec (3 steps) of silent (or pause) interval can be set.

Therefore, the four-stage speed control code from A to D input to the input port S of the speech synthesizer VSC.
The silent section is determined by specifying four levels of silence codes from 0 to 3 using the parameters and the specified code information input to input port D, thereby realizing control of the speech rate. .

FIG. 4 is a block diagram showing the detailed structure of the speech synthesizer VSC in the system block diagram of the present invention.

In the figure, CPU ₂ is a central processing unit (processor) that controls the voice synthesis data based on the input designated code information D and speed control code parameter S, R is a register that temporarily stores the designated code information input from the A register, ROM ₂ is a read-only memory that stores the voice synthesis procedure algorithm for each vocabulary, and also stores the silent section code. AR is the address register of memory ROM ₂ , and processor CPU ₂ transfers the input designated code information to this AR register and outputs the input speed control code parameter S to decoder DC ₁ .
BUFF is a buffer that temporarily stores the contents of the specified memory ROM ₂ .
It consists of an area d for storing data designating which basic voice decoder (i.e., voice segment) stored in the ROM ₃ is to be used, an area P for storing pitch control data, and an area s for storing volume information.
DC ₁ is a decoder for decoding speech segment specification data d and speed control code parameter S, and DC ₂ is a
is a decoder for decoding pitch control data P, and the pitch control data p in the buffer BUFF is
The counter CT is decoded into the following and output to the counter CT. Each time the clock pulse signal φ is input,
The contents are counted down, and the contents of the counter CT are judged by the jack circuit J. When the contents of CT are 0,
The pitch control is performed by outputting a reference level until the detection of the reference level.

The decoder DC ₁ decodes the code stored in the d area of the buffer BUFF, but if the content of the d area is a silent (pause) code, the speed parameter S output from the processor CPU ₂ as shown in FIG. For example, if the speed parameter is "10" of code No. "C" and the pause code corresponds to stage 2, the generation speed is controlled after a pause time of 80 msec.
Therefore, the decoder output decoded by DC ₁ is input to address counter AC of memory ROM ₃ .
ROM ₃ is a read-only memory that stores silence interval information along with speech segments. The contents of the designated memory ROM ₃ are output to register Y, and further sent to variable operation section M. Memory ROM ₃
Addresses are sequentially raised by the UP signal and output sequentially. The variation operation unit M performs variation operations such as amplitude level control on the basic audio data obtained from the memory ROM ₃ via the Y register based on the size information s of the buffer register BUFF. W is an output buffer, and digital values are outputted to this buffer and sequentially transferred to the digital-to-analog converter DA in synchronization with the timing of the sampling frequency Sf. The DA converter converts the digital value into analog audio information and outputs desired audio data from the speaker SP. Memory like this
The pause code output from ROM ₂ , that is, the d output of buffer BUFF, is set as the speed control parameter S.
By decoding this with the decoder _DC1 , even if the pause code is the same, the pause time can be changed by the speed code parameter S to control the speaking speed.

For example, by outputting the speed control code information in the same way as the specified code information as described above,
If three vocabulary words A, B, C, D, E, and F are to be output in succession, and vocabulary words A, B, and C are to be uttered slowly and words D, E, and F are to be uttered quickly, the following code can be sent. That is, X, A, B, C, Y, D, E, F where X is a control code for slow utterance, Y
is a control code for speaking quickly.

In this way, the audio output speed can be easily set by simply sending a control code before speed control.

<Effects> As explained above, according to the present invention, processing program command information, speed control code information for specifying the speed of audio output, and designation code information for specifying specific audio information in the audio memory are processed. Since the output speed of synthesized speech is controlled by storing predetermined speech information specified by the specified code information in the memory means and changing it using the speed control code information, it is possible to control the output speed of the synthesized speech information. Speed control can be performed by changing desired speed control code information. In addition, the specification code information and speed control code information sent from the central processing unit to the speech synthesizer can be sent in the same way, and there is no need to distinguish between the two and send and receive them separately, making control easier and the system configuration simpler and cheaper. Can be configured. Further, the speed control code information does not need to be sent every time the specified code information for specifying specific audio information in the audio memory is sent, and only needs to be sent once when changing, which greatly simplifies control. Furthermore, by changing the program command information, it can be applied to various electronic devices (eg, calculators, watches, game devices, etc.), making it extremely versatile. Furthermore, the output speed of the synthesized speech can be varied in various ways by combining the speed control code information and the silent section code included in the audio information.

[Brief explanation of the drawing]

Fig. 1 is a system block diagram of an embodiment of the speech synthesis control device according to the present invention, Fig. 2 is a flowchart for explaining an example of speed control in the system, and Fig. 3 is a system block diagram of an embodiment of the speech synthesis control device according to the present invention. FIG. 4, which is a diagram showing an example of pause sound code information, is a block diagram showing the detailed structure of the speech synthesizer in the system block diagram of FIG. 1. In the figure, K: key input device, EC: encoder,
CPU ₁ ~ _{CPU 2} : Central processing unit, ROM ₁ ~ _{ROM 3} :
Read-only memory, RAM: Random access memory, DSC: Display control unit,
DISP: Display section, A, B: Register, JA: Jersey circuit, IC: Input circuit, VSC: Speech synthesizer,
SP: Speaker, AR: Address register,
BUFF: buffer, DC ₁ ~ _{DC 2} : decoder,
RY: Register, AC: Address counter, DA:
D/A converter.

Claims (1)

[Scope of utility model registration request] It has an audio memory that stores audio information including a silent section code, and an audio output means that converts the contents of the audio memory into audio, processing program command information, speed control code information for specifying the speed of audio output, and the audio. a memory means for respectively storing designation code information for designating specific audio information in the memory; a central processing unit for executing arithmetic control based on the processing program instruction information read from the memory means; and the central processing unit. a first buffer means for temporarily storing the speed control code information or designation code information from the memory means associated with the apparatus; a determination means for determining the information content of the first buffer means; and a first buffer means for determining the information content of the first buffer means; a second buffer means for temporarily storing the speed control code information if the information content inputted to the first buffer includes speed control code information; and a second buffer means for temporarily storing the speed control code information; and means for controlling the speed by changing the silent section based on the silent section code included in the audio information specified by the specified code information and the speed control code information, and controlling the speed of the synthesized speech. A speech synthesis control device characterized in that it controls.