JPS6341935U - - Google Patents
Info
- Publication number
- JPS6341935U JPS6341935U JP13571286U JP13571286U JPS6341935U JP S6341935 U JPS6341935 U JP S6341935U JP 13571286 U JP13571286 U JP 13571286U JP 13571286 U JP13571286 U JP 13571286U JP S6341935 U JPS6341935 U JP S6341935U
- Authority
- JP
- Japan
- Prior art keywords
- digital pll
- circuit
- power supply
- reference power
- supply circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13571286U JPS6341935U (es) | 1986-09-03 | 1986-09-03 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13571286U JPS6341935U (es) | 1986-09-03 | 1986-09-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6341935U true JPS6341935U (es) | 1988-03-19 |
Family
ID=31038162
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13571286U Pending JPS6341935U (es) | 1986-09-03 | 1986-09-03 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6341935U (es) |
-
1986
- 1986-09-03 JP JP13571286U patent/JPS6341935U/ja active Pending
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