JPS6341410B2 - - Google Patents

Info

Publication number
JPS6341410B2
JPS6341410B2 JP55110892A JP11089280A JPS6341410B2 JP S6341410 B2 JPS6341410 B2 JP S6341410B2 JP 55110892 A JP55110892 A JP 55110892A JP 11089280 A JP11089280 A JP 11089280A JP S6341410 B2 JPS6341410 B2 JP S6341410B2
Authority
JP
Japan
Prior art keywords
capacitor
switch
operational amplifier
circuit
delay circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55110892A
Other languages
Japanese (ja)
Other versions
JPS5735836A (en
Inventor
Yoshio Serikawa
Masamichi Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP11089280A priority Critical patent/JPS5735836A/en
Publication of JPS5735836A publication Critical patent/JPS5735836A/en
Publication of JPS6341410B2 publication Critical patent/JPS6341410B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03BAPPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
    • G03B7/00Control of exposure by setting shutters, diaphragms or filters, separately or conjointly
    • G03B7/08Control effected solely on the basis of the response, to the intensity of the light received by the camera, of a built-in light-sensitive device
    • G03B7/081Analogue circuits

Description

【発明の詳細な説明】 本発明はカメラの測光回路に関する。[Detailed description of the invention] The present invention relates to a photometry circuit for a camera.

フオトダイオードの如き光起電力素子は応答性
の速い素子であるが、カメラの測光回路に使用す
ると、その接合容量への逆充電などによる電源応
答遅れが低揮度側で発生する。これを防止するた
めに従来は測光部の対数圧縮用ダイオードと逆
向きで並列にダイオードを接続してフオトダイオ
ードの接合容量に逆充電された電荷をある程度放
電させるもの、フオトダイオードに逆充電され
た電荷を電源投入後に一時的にフオトダイオード
の光電流を殖して放電させるもの、実公昭53―
19067号、実公昭53―19068号、実開昭50―31931
号のように測光用演算増幅器の反転入力側にフオ
トダイオード、対数圧縮用ダイオード以外のもの
を接続して電源応答速度を速くするものを提案し
ている。しかしの測光回路では対数圧縮用ダイ
オードと逆向きで並列に接続したダイオードは順
方向電圧が小さければ順方向電流も小さくなるた
め、フオトダイオードの接合容量に逆充電された
電荷を短時間に放電させることができず電源応答
速度を速くするという効果が少ない。またの測
光回路ではフオトダイオードの光電流を一時的に
殖すための光源と、この光源を電源開閉器に同期
して短時間点灯させるための回路とが必要となり
構成が複雑になる。更にの測光回路では測光用
演算増幅器の反転入力側にフオトダイオード、対
数圧縮用ダイオード以外のものが接続されるため
測光用演算増幅器の反転入力側のリークが発生し
やすくなり、リーク電流が測光精度を下げる原因
となる。測光用演算増幅器の反転入力側にコンデ
ンサを接続している場合コンデンサには漏電流が
有るため、この漏電流も測光精度を下げる原因に
なる。従つて低輝度側における電源応答性を速く
してもリーク電流、漏電流により低輝度側の測光
が行えなくなつている。
A photovoltaic element such as a photodiode is a fast-responsive element, but when used in a photometry circuit of a camera, a power response delay occurs on the low volatility side due to reverse charging of its junction capacitance. To prevent this, the conventional method was to connect a diode in parallel in the opposite direction to the logarithmic compression diode in the photometry section to discharge some of the charge reversely charged to the junction capacitance of the photodiode. A device that temporarily increases the photocurrent of a photodiode and discharges the charge after the power is turned on.
No. 19067, Publication No. 53-19068, No. 31931 of Publication No. 50-31931
proposed a method to increase the power response speed by connecting something other than a photodiode and a logarithmic compression diode to the inverting input side of a photometric operational amplifier, as shown in No. However, in a photometric circuit, the diode connected in parallel with the logarithmic compression diode in the opposite direction has a small forward voltage and a small forward current, so the charge reversely charged in the photodiode's junction capacitance is discharged in a short time. Therefore, the effect of increasing the power response speed is small. Furthermore, the photometry circuit requires a light source for temporarily increasing the photocurrent of the photodiode and a circuit for turning on the light source for a short time in synchronization with the power switch, making the configuration complicated. Furthermore, in the photometric circuit, since something other than the photodiode and logarithmic compression diode is connected to the inverting input side of the photometric operational amplifier, leakage is likely to occur on the inverting input side of the photometric operational amplifier, and the leakage current may affect the photometric accuracy. This causes a decrease in When a capacitor is connected to the inverting input side of a photometric operational amplifier, the capacitor has a leakage current, and this leakage current also causes a reduction in photometry accuracy. Therefore, even if the power supply response on the low brightness side is made faster, photometry on the low brightness side is no longer possible due to leakage current.

本発明は上記欠点を改良し、測光部に簡単な回
路を追加するだけで低輝度側における電源応答性
を速くするようにした測光回路を提供することを
目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a photometry circuit which improves the above-mentioned drawbacks and improves the power response on the low luminance side by simply adding a simple circuit to the photometry section.

以下図面を参照しながら本発明について実施例
をあげて説明する。
The present invention will be described below by way of examples with reference to the drawings.

本発明の第1実施例は低輝度側で電源応答遅れ
が発生する原因となるフオトダイオードの接合容
量への逆充電量を最小にすることによつて電源応
答速度を速くしたものである。また測光用演算増
幅器の反転入力端子は超高抵抗になるので最低必
要となるフオトダイオードと対数圧縮用ダイオー
ドしか接続しないで測光精度が下がらないように
している。
In the first embodiment of the present invention, the power response speed is increased by minimizing the amount of reverse charge to the junction capacitance of the photodiode, which causes a power response delay on the low brightness side. Furthermore, since the inverting input terminal of the photometric operational amplifier has an extremely high resistance, only the minimum required photodiode and logarithmic compression diode are connected to prevent the photometric accuracy from deteriorating.

第1図はこの第1実施例を示し、第2図はその
タイミングチヤートである。演算増幅器OP1は電
界効果トランジスタFET1,FET2、トランジス
タTr1〜Tr6、定電流源CC1〜CC4、コンデンサ
C1、抵抗R1,R2よりなり、対数変換用ダイオー
ドD1及びフオトダイオードD2と共に測光部MPを
構成する。フオトダイオードD2は演算増幅器OP1
の反転入力端子と非反転入力端子との間に接
続され、対数圧縮用ダイオードD1は演算増幅器
OP1の出力端子と反転入力端子との間に接続され
る。演算増幅器OP1は非反転入力端子及び共通
端子Nが接地され、電源端子Pが電源スイツチ
SW1を介して直流電源VBに接続される。遅延回
路DL1は電源投入より一定の時間動作するもの
で、タイマー等が用いられる。この遅延回路DL1
はa点に接続され、a点は電源スイツチSW1を介
して直流電源VBに接続されている。短絡用トラ
ンジスタTr7はコレクタが測光部MPの出力端子
V0に接続されてエミツタが接地され、ベースが
抵抗R3を介して遅延回路DL1の出力端子bに接続
される。立上り時間制御用コンデンサC2は一端
が出力端子V0に接続され、他端が抵抗R4、トラ
ンジスタTr8を直列に介してa点に接続されると
共にダイオードD3を介して演算増幅器OP1におけ
るトランジスタTr5のベースに接続される。トラ
ンジスタTr8のベースは抵抗R5、トランジスタ
Tr9を直列に介して接地され、トランジスタTr9
のベースは抵抗R6を介してb点に接続される。
FIG. 1 shows this first embodiment, and FIG. 2 is its timing chart. Operational amplifier OP 1 consists of field effect transistors FET 1 , FET 2 , transistors Tr 1 to Tr 6 , constant current sources CC 1 to CC 4 , and capacitors.
C 1 , resistors R 1 and R 2 , and together with the logarithmic conversion diode D 1 and the photodiode D 2 , constitute a photometry section MP. Photodiode D 2 is operational amplifier OP 1
The logarithmic compression diode D1 is connected between the inverting and non-inverting input terminals of the operational amplifier.
Connected between the output terminal of OP 1 and the inverting input terminal. The non-inverting input terminal and common terminal N of operational amplifier OP 1 are grounded, and the power supply terminal P is connected to the power switch.
Connected to DC power supply V B via SW 1 . The delay circuit DL 1 operates for a certain period of time after the power is turned on, and a timer or the like is used. This delay circuit DL 1
is connected to point a, and point a is connected to a DC power supply VB via a power switch SW1 . The collector of the shorting transistor Tr 7 is the output terminal of the photometry section MP.
The emitter is connected to V 0 and grounded, and the base is connected to the output terminal b of the delay circuit DL 1 via a resistor R 3 . One end of the rise time control capacitor C2 is connected to the output terminal V0 , and the other end is connected to the point a through the resistor R4 and the transistor Tr8 in series, and to the operational amplifier OP1 through the diode D3 . It is connected to the base of transistor Tr5 in. The base of transistor Tr 8 is resistor R 5 , transistor
Grounded through Tr 9 in series, transistor Tr 9
The base of is connected to point b via resistor R6 .

次に第1実施例の作用について詳述する。 Next, the operation of the first embodiment will be explained in detail.

電源スイツチSW1をオンすると、a点に直流電
源VBの出力が供給されて遅延回路DL1の出力が
高レベルになる。このため短絡用トランジスタ
Tr7がオンして測光部MPの出力側を短絡し、こ
の状態は測光部MPが電源スイツチSW1をオンし
てから安定に作動するまでの時間遅延回路DL1
より続けられる。またトランジスタTr8,Tr9
オンになりコンデンサC2が抵抗R4を通して充電
される。その後、遅延回路DL1の出力が低レベル
になると、トランジスタTr7〜Tr9がオフになる。
そしてフオトダイオードD2の開放電圧により演
算増幅器OP1の出力が高レベルに上がろうとする
が、コンデンサC2に充電された電荷がダイオー
ドD3を介して演算増幅器OP1に流れ込んでその出
力を低レベルにするように働くため、演算増幅器
OP1の出力はコンデンサO2より流れる電流によつ
て規制されながら第2図のアのように上がつて行
く。このように演算増幅器OP1の出力が上がつて
行くと、出力端子V0よりダイオードD1を介して
フオトダイオードD2に電流が流れる。この電流
により、フオトダイオードD2の開放電圧で充電
されたフオトダイオードD2の接合容量の電荷が
放電される。フオトダイオードD2が零バイアス
になつた時に出力端子V0からの電流が止まれば
良いが、演算増幅器OP1の入出力間の応答時間だ
け電流の止まるのが遅れるので、この遅れの間に
フオトダイオードD2の接合容量が逆充電される。
ただし、この逆充電される電荷はコンデンサC2
及びダイオードD3により上記の如く電流が流れ
て出力が規制されることによつて小さな値とな
る。この逆充電量は、対数圧縮ダイオードD1
出力側端子すなわち測光アンプの出力端子の電圧
上昇スピードが大きいほど多くなり、正常レベル
に達する迄の時間は長くなる。そこで図1のコン
デンサC2と抵抗R4から成る回路の時定数を大き
くとると、測光アンプの出力端の電圧上昇スピー
ドは下り、逆充電量は十分小さく出来る。フオト
ダイオードD2の接合容量に逆充電された電荷は
フオトダイオードD2の光電流により放電され、
出力が第2図のイのように目標値に達して以下正
常な測光動作が行なわれる。
When the power switch SW1 is turned on, the output of the DC power supply VB is supplied to point a, and the output of the delay circuit DL1 becomes high level. Therefore, the short circuit transistor
Tr 7 is turned on to short-circuit the output side of the photometer MP, and this state is continued by the time delay circuit DL 1 from when the photometer MP turns on the power switch SW 1 until it operates stably. Also, transistors Tr 8 and Tr 9 are turned on, and capacitor C 2 is charged through resistor R 4 . Thereafter, when the output of the delay circuit DL1 becomes low level, the transistors Tr7 to Tr9 are turned off.
Then, the output of operational amplifier OP 1 tries to rise to a high level due to the open circuit voltage of photodiode D 2 , but the charge stored in capacitor C 2 flows into operational amplifier OP 1 via diode D 3 and suppresses its output. The operational amplifier works to lower the level
The output of OP 1 rises as shown in Figure 2 A while being regulated by the current flowing from capacitor O 2 . As the output of the operational amplifier OP1 increases in this way, current flows from the output terminal V0 to the photodiode D2 via the diode D1 . This current discharges the charge in the junction capacitance of the photodiode D 2 that has been charged by the open-circuit voltage of the photodiode D 2 . It is sufficient if the current from the output terminal V 0 stops when the photodiode D 2 becomes zero bias, but since there is a delay in stopping the current by the response time between the input and output of the operational amplifier OP 1 , the photodiode The junction capacitance of diode D 2 is reversely charged.
However, this reversely charged charge is transferred to the capacitor C 2
The current flows through the diode D3 as described above, and the output is regulated, resulting in a small value. The amount of reverse charge increases as the voltage rise speed at the output terminal of the logarithmic compression diode D1 , that is, the output terminal of the photometric amplifier increases, and the time required to reach the normal level increases. Therefore, if the time constant of the circuit consisting of capacitor C 2 and resistor R 4 in Figure 1 is made large, the speed at which the voltage rises at the output terminal of the photometric amplifier is reduced, and the amount of reverse charging can be made sufficiently small. The charge reversely charged to the junction capacitance of photodiode D2 is discharged by the photocurrent of photodiode D2 ,
When the output reaches the target value as shown in FIG. 2A, normal photometry operation is performed thereafter.

ところで、この様に構成した場合、逆充電量を
小さくする為には帰還ダイオードD3を通して流
れる電流を徐々に長時間流す必要があるが、それ
だと充電時間が長くなり、測光アンプの不作動時
間が長くなつて、その後の正常レベルに達するの
が早くても全体の応答時間は長くなつてしまう。
By the way, with this configuration, in order to reduce the amount of reverse charging, it is necessary to gradually allow the current to flow through the feedback diode D3 for a long time, but this will lengthen the charging time and cause the photometric amplifier to become inoperable. As the time becomes longer, the overall response time becomes longer even if the subsequent normal level is reached quickly.

しかし本実施例の様にトランジスタTr5のベー
スにダイオードD3を通してコンデンサC2の電流
を供給するようにしておくと、測光アンプの出力
が正常時の値に近ずくとダイオードD3のインピ
ーダンスは高くなり帰還電流は少なくなつて測光
アンプの上昇スピードはコンデンサC2の放電終
了時は十分ゆつくりとなつている。最初の上昇ス
ピードは早くても、最終の上昇スピードがこの様
に遅くなるので短時間のコンデンサC2の放電で
もフオトダイオードD2の逆充電は十分小さく出
来る。すなわち測光すべき光の明るさがフオトダ
イオードD2で電気量に変換されて演算増幅器OP1
及び対数圧縮用ダイオードD1により対数圧縮さ
れ出力端子V0より出力される。
However, if the current of the capacitor C2 is supplied through the diode D3 to the base of the transistor Tr5 as in this embodiment, when the output of the photometric amplifier approaches the normal value, the impedance of the diode D3 will decrease. As the feedback current becomes higher and the feedback current decreases, the rising speed of the photometric amplifier becomes sufficiently slow when the capacitor C2 finishes discharging. Even if the initial rising speed is fast, the final rising speed is slow in this way, so even if the capacitor C 2 is discharged for a short time, the reverse charging of the photodiode D 2 can be sufficiently small. In other words, the brightness of the light to be measured is converted into an electrical quantity by photodiode D 2 and then sent to operational amplifier OP 1.
The signal is then logarithmically compressed by the logarithmic compression diode D 1 and output from the output terminal V 0 .

第3図は本発明の第2実施例を示す。 FIG. 3 shows a second embodiment of the invention.

この第2実施例では遅延回路DL2は出力が遅延
回路DL1とは反転したものとなり、トランジスタ
Tr9が省略されている。トランジスタTr8のベー
スは抵抗R5を介してb点に接続され、短絡用ト
ランジスタTr10はPNP形である。
In this second embodiment, the output of the delay circuit DL 2 is inverted from that of the delay circuit DL 1 , and the output is a transistor
Tr 9 is omitted. The base of the transistor Tr 8 is connected to point b via a resistor R 5 , and the shorting transistor Tr 10 is of PNP type.

第4図は本発明の第3実施例を示す。 FIG. 4 shows a third embodiment of the invention.

この第3実施例は出力が上記実施例とは逆極性
になつた例であり、フオトダイオードD2及びダ
イオードD1,D3が逆向きにされる。演算増幅器
OP1の非反転入力端子は抵抗R7を介して接地さ
れると共に抵抗R8を介してa点に接続され、演
算増幅器OP1の出力端子は抵抗R9を介して出力端
子V0に接続される。トランジスタTr10は出力端
子V0とa点との間に接続され、コンデンサC2
一端は抵抗R4、トランジスタTr8を直列に介して
接地されると共にダイオードD3を介してトラン
ジスタTr2のベースに接続される。
This third embodiment is an example in which the output has a polarity opposite to that of the above embodiment, and the photodiode D 2 and the diodes D 1 and D 3 are oriented in opposite directions. operational amplifier
The non-inverting input terminal of OP 1 is grounded via resistor R 7 and connected to point a via resistor R 8 , and the output terminal of operational amplifier OP 1 is connected to output terminal V 0 via resistor R 9 . be done. The transistor Tr 10 is connected between the output terminal V 0 and the point a, and one end of the capacitor C 2 is grounded through the resistor R 4 and the transistor Tr 8 in series, and is connected to the transistor Tr 2 through the diode D 3 . connected to the base.

以上のように本発明によれば光起電力素子と、
この光起電力素子が入力側に接続された演算増幅
器及びこの演算増幅器の帰還回路に接続された対
数圧縮用ダイオードを有する測光部と、電源投入
により一定の時間動作する遅延回路と、この遅延
回路の出力信号によりこの遅延回路の動作時にオ
ンして前記測光部の出力側を短絡する第1のスイ
ツチと、一端が前記測光部の出力端子に接続され
たコンデンサと、このコンデンサと電源との間に
設けられ前記遅延回路の出力信号により前記遅延
回路の動作時にオンして前記コンデンサを充電さ
せる第2のスイツチと、前記コンデンサの他端と
前記演算増幅器における入力側以外の所定箇所と
の間に接続され前記コンデンサを前記第1のスイ
ツチ及び第2のスイツチのオフ時に前記測光部へ
放電させることにより前記測光部の出力信号を規
制する整流素子とを具備するので、フオトダイオ
ード等の光起電力素子の持つ容量への逆充電量を
少なくすることができる。従つて低輝度側におい
てもカメラの電源投入とほぼ同時に測光出力を得
ることができてカメラのレリーズ直前に電源を入
れてもよく、かつ測光範囲を低輝度まで延ばすこ
とができる。又測光部に簡単な回路を加えるだけ
ですむので、コストが安く性能を上げることがで
き、更に電源投入直後の動作と測光動作を時分割
で行えるため消費電流を下げることができる。ま
た測光部における演算増幅器の入力側には回路を
付加しないので、この演算増幅器の入力側リーク
がなく、測光精度を下げることがない。
As described above, according to the present invention, a photovoltaic element,
an operational amplifier to which the photovoltaic element is connected to the input side; a photometric section having a logarithmic compression diode connected to the feedback circuit of the operational amplifier; a delay circuit that operates for a certain period of time when the power is turned on; a first switch that is turned on when the delay circuit is activated by the output signal of the delay circuit to short-circuit the output side of the photometric section; a capacitor with one end connected to the output terminal of the photometric section; and a switch between the capacitor and the power supply. a second switch provided in the switch that is turned on when the delay circuit is operated by the output signal of the delay circuit to charge the capacitor; and a second switch between the other end of the capacitor and a predetermined location other than the input side of the operational amplifier. A rectifying element is connected to the photovoltaic device such as a photodiode, and the rectifying element regulates the output signal of the photometry section by discharging the capacitor to the photometry section when the first switch and the second switch are turned off. The amount of reverse charge to the capacitance of the element can be reduced. Therefore, even on the low brightness side, a photometric output can be obtained almost at the same time as the camera is powered on, the power can be turned on just before the camera is released, and the photometric range can be extended to low brightness. Furthermore, since it is only necessary to add a simple circuit to the photometry section, the cost is low and the performance can be improved.Furthermore, since the operation immediately after power is turned on and the photometry operation can be performed in a time-sharing manner, current consumption can be reduced. Further, since no circuit is added to the input side of the operational amplifier in the photometry section, there is no leakage on the input side of the operational amplifier, and the photometry accuracy is not degraded.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2
図は同実施例のタイミングチヤート、第3図及び
第4図は本発明の他の各実施例を示す回路図であ
る。 DL1,DL2…遅延回路、C2…コンデンサ、D3
整流素子、Tr7〜Tr10…スイツチ、MP…測光部、
D1…対数圧縮用ダイオード、D2…光起電力素子、
OP1…演算増幅器。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a timing chart of the same embodiment, and FIGS. 3 and 4 are circuit diagrams showing other embodiments of the present invention. DL 1 , DL 2 ...Delay circuit, C 2 ...Capacitor, D 3 ...
Rectifying element, Tr 7 to Tr 10 ...switch, MP...photometering section,
D 1 ... Logarithmic compression diode, D 2 ... Photovoltaic element,
OP 1 ...Operation amplifier.

Claims (1)

【特許請求の範囲】[Claims] 1 光起電力素子と、この光起電力素子が入力側
に接続された演算増幅器及びこの演算増幅器の帰
還回路に接続された対数圧縮用ダイオードを有す
る測光部と、電源投入により一定の時間動作する
遅延回路と、この遅延回路の出力信号によりこの
遅延回路の動作時にオンして前記測光部の出力側
を短絡する第1のスイツチと、一端が前記測光部
の出力端子に接続されたコンデンサと、このコン
デンサと電源との間に設けられ前記遅延回路の出
力信号により前記遅延回路の動作時にオンして前
記コンデンサを充電させる第2のスイツチと、前
記コンデンサの他端と前記演算増幅器における入
力側以外の所定箇所との間に接続され前記コンデ
ンサを前記第1のスイツチ及び第2のスイツチの
オフ時に前記測光部へ放電させることにより前記
測光部の出力信号を規制する整流素子とを具備し
た測光回路。
1. A photometry unit that includes a photovoltaic element, an operational amplifier to which the photovoltaic element is connected to the input side, and a logarithmic compression diode connected to the feedback circuit of the operational amplifier, and operates for a certain period of time when the power is turned on. a delay circuit; a first switch that is turned on when the delay circuit is operated by an output signal of the delay circuit to short-circuit the output side of the photometric section; and a capacitor having one end connected to the output terminal of the photometric section; A second switch is provided between the capacitor and the power source and is turned on when the delay circuit is operated by the output signal of the delay circuit to charge the capacitor, and a switch other than the other end of the capacitor and the input side of the operational amplifier. and a rectifying element connected between a predetermined location of the switch and a rectifying element that regulates the output signal of the photometric section by discharging the capacitor to the photometric section when the first switch and the second switch are off. .
JP11089280A 1980-08-12 1980-08-12 Photometric circuit Granted JPS5735836A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11089280A JPS5735836A (en) 1980-08-12 1980-08-12 Photometric circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11089280A JPS5735836A (en) 1980-08-12 1980-08-12 Photometric circuit

Publications (2)

Publication Number Publication Date
JPS5735836A JPS5735836A (en) 1982-02-26
JPS6341410B2 true JPS6341410B2 (en) 1988-08-17

Family

ID=14547325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11089280A Granted JPS5735836A (en) 1980-08-12 1980-08-12 Photometric circuit

Country Status (1)

Country Link
JP (1) JPS5735836A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215908A (en) * 1988-07-04 1990-01-19 Toshiaki Hosoi Drill and its grinding method and device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2667673B2 (en) * 1988-03-19 1997-10-27 シャープ株式会社 Integrator circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4853687A (en) * 1971-11-08 1973-07-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4853687A (en) * 1971-11-08 1973-07-27

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215908A (en) * 1988-07-04 1990-01-19 Toshiaki Hosoi Drill and its grinding method and device

Also Published As

Publication number Publication date
JPS5735836A (en) 1982-02-26

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