JPS6341259B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a device that performs high-speed data transmission using a plurality of lines.

BACKGROUND ART Data transmission has conventionally been carried out by accommodating one or more communicators on a single line or conducting wire. Therefore, the data transmission speed is limited by the transmission speed (bandwidth) of the line, and when a modem is connected to an ordinary telephone line, it can reach no more than a few Kb/s.

Furthermore, as short-distance communication lines such as those between devices, data is transmitted in parallel over a plurality of conductive lines. In this case, since the distance is short and the transmission is in an almost fixed format, there is no difference in delay between conductors (lines), and the transmission speed is low (30 Kb/s conductor at most), so it is possible to use serial/parallel transmission. Signal conversion could also be handled without the use of special protocols. Therefore, if the same technology is applied to long-distance, high-speed data transmission, there will be problems such as line disruption due to fluctuations in delay differences between lines and line switching (which is often done in public networks). happens.

(Problem to be solved by the invention) In order to eliminate these drawbacks, the present invention transmits data information by dividing it into multiple lines, and absorbs the variation in delay difference between the lines by using a packet format frame structure. The drawings will be explained in detail below.

(Structure and operation of the invention) FIG. 1 shows an embodiment of the present invention, in which 1 is an input line, 2 is a switch for cutting and distributing a data string to a plurality of lines, and 3 is a bit on input line 1. a converter for converting the transmission speed to the transmission speed of the transmission line 5; 4 a packet assembler for converting into packets;
5 is a transmission line between sending and receiving, 6 is a packet decomposer on the receiving side, 7 is a buffer memory to prepare for frame loss due to transmission path fluctuations, 8 is a speed converter to increase the original transmission speed, 9 is a plurality of lines 10 is a control circuit for driving switch 9 based on inter-line identification information and line order, 11 is a control line connecting 6 and 10, 12 is 9
and 10, and 13 is an output line. 3～
8 and 11 are installed one each corresponding to each line.

For example, an input data string of 64 Kb/s is divided into 5 transmission lines (lines) in Figure 1, and 3
It is carried on a 14Kb/s pulse train. Therefore, since each line has a gap equivalent to 1 Kb/s in addition to data, line control information such as inter-line identification information 14 and packet order 15 can be added to the line using 4.

The frame structure on the transmission line 5 is shown in FIG.
14 is inter-line identification information, which displays the numbers of multiple lines divided by 2. 15 represents the order of packets within the same line, 16 represents data, 1
7 is block error control information, and 6 is used to determine an error. These are inserted with appropriate control codes for block separation or synchronization as necessary. For the input switch 2, it is sufficient to switch the parallel contacts using a certain clock, but
The output switch 9 requires control in order to absorb fluctuations in the transmission line 5. FIG. 3 shows an example of the configuration of 9 and 10. 18 is an input line from the FIFO of each line, 19 is a contact that is driven by the inter-line identification information 14, and 20 is a contact that is driven by the intra-line order 15. 21 and 22 correspond to the control circuit 10;
This circuit converts and synchronizes information 14 and 15, respectively, and manages the order of received packets. First, keep contact 20 closed and connect line number management circuit 21.
The switch 19 is sequentially scanned according to the line number 14 sent from the packet decomposer 6, and packets having the same order of decomposition and extraction by the packet decomposer 6 are sequentially sent to the packet decomposer 13. This corresponds to one scan of switch 2 on the transmitting side. Next, the packet order is incremented by one, and after that number is confirmed by the order management circuit 22 via the packet decomposer 6, the packet series in the same order is sequentially sent out as before. If the packet order or transmission signal is found to be abnormal by the order management circuit 22 or the CRC check circuit of the packet decomposer 6, the switch 19 or 20 will be opened by the control circuit 21 or 22, and reception will be blocked. be done. This information is notified to the sending side as monitoring information, and retransmission is requested.

Although the case where the switches 19 and 20 and the control circuits 21 and 22 are separate regarding the line number and packet order has been described above, it is also possible to omit the switch 20. That is, by taking the logical sum of the control information from 21 and 22 and driving the switch 19, each line is output in accordance with the line number and packet order.
Data can be read from FIFO8.

FIG. 4 shows the transmitter side of another embodiment of the invention.
Reference numeral 23 denotes a packet multiplexer having functions of assembling and multiplexing packets for a plurality of data inputs 1'. 24 is a circuit that adds the line number 14 and packet order 15 necessary for transmission over multiple lines, which is the object of the present invention. In the second embodiment (FIG. 4), unlike the case in FIG. 1, the original signal is packetized, so the packet assembler 4 is not necessary.

FIG. 6 shows the packet format on the transmission path 5 in the case of FIG. 4. 14,15,
17 is the same as in Figure 2, but 28, 29, 3
0 and 31 represent the address field, control field, packet header, and frame check sequence of the original packet, respectively. These additional headers 14 and 15 are linked to the input switch 2 via a control line 25. That is, packets with the same line number 14 are sent to the same line 5, and the packet order follows the packet order 15.

The speed converter 3 sends the signal directly to the transmission line 5.

The receiving side is shown in FIG.
uses the information 14 and 15 to open and close the switch 9 as explained in FIG. 27 is additional header 1
This is a circuit for removing 4, 15 and 17.

The configurations shown in FIGS. 4 and 5 enable high-speed, long-distance data transmission even for packet-format input data without increasing the overhead for controlling multiple lines. Furthermore, the effect of packet multiplexing allows multiple data (terminals) to use the line efficiently.

Although FIG. 5 shows an embodiment in which the header removal is performed after the switch 9, this function may be assigned to the additional header discriminating circuit 26 (as in the packet decomposer 6 of invention (1)). In this case, the original packets (28-31 in FIG. 6) pass through the switch 9.

Furthermore, although FIG. 5 shows an embodiment in which the existing packet multiplexing device 23 is used as is, the function of the packet multiplexing device 24 is twofold.
It is also possible to merge into 3. If you do that, 2
There is no need to resynchronize packets (flag synchronization) between packets 3 and 24, which has the advantage of greatly simplifying communication processing.

(Effects of the Invention) As described above, the present invention enables long-distance, high-speed data transmission even when using multiple lines with variable transmission characteristics or multiple lines with significantly different characteristics. Although the devices are slightly different depending on whether the input data is continuous or in the packet format, the present invention can handle both types of data.

Therefore, by using the present invention, data transmission of several 100 Kb/s between Tokyo and Osaka, for example, which is not currently provided by the Telegraph and Telephone Public Corporation, becomes possible by using a plurality of dedicated lines.

Input data includes (i) computer input/output data, (ii) measuring instrument input/output data, as well as (iii) coded audio, (iv) coded images, etc. can be transmitted to.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a frame block diagram, Fig. 3 is a detailed functional explanatory diagram of the output side switch of Fig. 1, and Figs. FIG. 6 shows a frame configuration diagram of each of the input and output sides of other embodiments of the invention. 1: Input line, 2: Sending side switch, 3: Sending side speed converter, 4: Packet assembler, 5: Transmission line,
6: Packet decomposer, 7: Buffer memory, 8:
Receiving side speed converter, 9: Receiving side switch, 10:
Switch control circuit, 11: Control input line, 12: Control output line, 13: Output line, 14: Inter-line number identification information, 15: Intra-line packet order, 16: Data, 17: Error control information, 18: Receiving side Speed converter output line, 19: Inter-line contact, 20: In-line contact, 21: Inter-line control circuit, 22: In-line control circuit, 23: Packet multiplexer, 24: Header addition circuit, 25: Transmission switch Control line, 26: Header discrimination circuit, 27: Header removal circuit, 28,2
9, 30, 31: each address field, control field, packet header, and frame check sequence of the original packet.

Claims (1)

[Claims] 1. A means for converting transmission data into a plurality of parallel data strings, and a means for converting each parallel data string into packets and converting the data into parallel data while identifying data strings and managing the order of packets within the data string using packet headers. means for transmitting the serial data over a corresponding line, a packet decomposer provided on the receiving side, a switch that sequentially scans the output of each packet decomposer to reproduce and output the original serial data, and a switch that controls the switch. a control circuit for controlling the switch by first scanning packets having the same order in the data string but on different lines, and then incrementing the order in the data string and repeating the above scanning; A data transmission device comprising: 2 Adding a header that receives packetized data from a single line and adds a header to the outside of the packet frame that has control information, number identification for multiple lines that follow, and information on the order of packets within the same line. A circuit, a transmitting side switch which sequentially sends out packets in parallel to a plurality of lines according to the identification information and order information, and a receiving side switch which scans the parallel packet string and converts it into a serial packet string. 1. A data transmission device comprising: a receiving switch that outputs an output; and a control circuit that controls the receiving switch in accordance with a header added on the transmitting side.