JPS6340511B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for transferring multiple packets.

In recent years, with the development of LSI, multiprocessor systems that aim to improve performance by using a large number of processors to share and process large tasks have become popular. In a multiprocessor system, processing is performed while data is exchanged between a plurality of processors, so the method of data transfer between the processors has a large effect on performance. Conventionally used methods include a crossbar switch method and a multi-stage network method. The crossbar switch method has high performance because any input can be connected to any output, but the number of circuit elements increases on the order of ^N2 with respect to the number of processors N, resulting in high costs. In addition, the multi-stage network method connects the small inputs (often 2 inputs x 2 outputs) of the aforementioned crossbar switches in multiple stages, and the performance is the same as the crossbar switch method, but the cost is lower.
Since it is on the order of NlogN, it is a method with an excellent performance/price ratio. However, with the conventional multi-stage network system, the control circuit that determines the overall route is centralized, making control complicated, and the problem of collisions between two different processors trying to transfer packets to the same processor. The disadvantage was that this resulted in a decrease in performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a transfer device that eliminates the above drawbacks and allows a plurality of processors to communicate efficiently.

The transfer system of the present invention is a device that inputs packets consisting of a plurality of bit strings from a plurality of input ports and sends the packets from a plurality of output ports, and inputs the packets to each of the plurality of input ports and temporarily stores the packets. An input buffer section, a means for extracting a part of the bit string stored in each input buffer section from a preset position, and one of a plurality of output ports for decoding the extracted bit string. a decoding circuit that selects a packet, an arbiter that selects one selection signal from the plurality of decoding circuits for each of the plurality of output ports, and a multiplexer that extracts a packet from an input buffer section corresponding to the input port selected by the arbiter. , and an output buffer section for temporarily storing packets output from the multiplexer and transmitting the packets from the output port.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a transfer device showing one embodiment of the present invention. I1, I2...IN are multiple input ports, and 01, 02...0M are multiple output ports. IB1, IB2, . . . IBN are input buffer sections corresponding to respective input ports. S1, S2
...SJ...SN are the respective input buffer sections I1 and I
2...IJ...It is a means for extracting a part of the bit string from the bit string of the packet stored in IN, and SL is information on a preset position. D1, D
2, DJ...DN decodes a part of the extracted bit string and connects the corresponding arbitrator A1, A2...AM
A selection signal is sent to one of the. R11, R12...R1
M is a decoding circuit D1 and an arbitrator A1, A2...AM
This is a signal line that connects the terminals and sends selection signals. Similarly R.J.
1, RJ2...RJM is the decoding circuit DJ and arbitrator A
1, A2...This is a signal line that connects AM and sends a selection signal. Arbitrators A1, A2...AM are connected to decoding circuits D1, D2...DJ...DN and send selection signals through line groups R11, R21...RJ1, RN1, R12,
R22…RJ2…RN2,…, R1M, R2M…
Connect RJM...RNM and select one from the selection signals coming from each. X1, X2...XM are multiplexers corresponding to the respective output ports 01, 02...0M, and input buffer sections corresponding to the selected input ports of the arbiters A1, A2...AM, respectively.
Take out a packet from one of IB1, IB2...IBJ...IBN. 0B1, 0B2...0BM are output buffer units that store packets output from multiplexers X1, X2...XM, and send the packets to corresponding output ports 01, 02...0M, respectively.

FIG. 2 shows the input buffer section IB1 shown in FIG.
One input buffer section in IB2...IBJ...IBN
FIG. 2 is a block diagram showing an example of the configuration of an IBJ. 21 is a buffer memory for storing input packets;
2 is a control circuit that inputs packets via input port IJ. DJ, SJ, and BJ are signal lines that constitute input port IJ, and DJ is the packet data line,
SJ is the packet transmission line and BJ is the busy line. The control circuit 22 notifies the packet sending side via the busy line BJ that the buffer memory 21 is available. The packet sending side is the packet data line DJ.
The content is placed on a packet, and a transmission signal is transmitted to the control circuit 22 from the packet sending line SJ. The control circuit 22 sends a load signal 203 to the buffer memory 21 and also outputs a ready signal 202 to indicate that a packet has been received. At this time, data line 201, FJ
Output packet data to . Reference numeral 204 is an end signal indicating that the input packet has been transmitted to the corresponding output buffer section, and the control circuit 22 notifies the packet sending side via the busy line BJ that the next packet can be input.

FIG. 3 is a block diagram showing an example of the configuration of SJ, which is one of the means S1, S2 . . . SJ . 31 is
The bit string of the packet data line 201 is shown, SF
1, SF2 . . . SFL indicate a part of bit string group of the packet data line 201. Numeral 32 is a multiplexer which takes out one bit string of the bit string groups SF1, SF2, . Information for selection is given to the multiplexer 32 by the setting information SL.

Figure 4 shows the decoding circuits D1 and D shown in Figure 1.
2. DJ... is a block diagram showing an example of the configuration of one of the DNs. QJ1, QJ2…QJM and AJ
1, AJ2...AJ1, AJ2...AJM constitute a line group RJ1, RJ2...RJM that sends selection signals in pairs, and QJ1, QJ2...QJM go to respective arbitrators A1, A2...AM. This is a selection request line group, and AJ1, AJ2, . . . AJM are selection approval line groups coming from the arbiter. 41 is a decoder which inputs the sub-bit string 301 and issues a selection request to one of the selection request line groups QJ1, QJ2, . . . QJM corresponding to decoding. 42 is an OR circuit and is a group of selection approval lines.
AJ1, AJ2...AJM are input, and when an approval signal is received from any one, a termination signal 204 is output.

Figure 5 shows the arbitrators A1, A2...AK shown in Figure 1.
... is a block diagram showing an example of the configuration of one of the AMs, AK.

51 is a priority encoder which inputs selection request line groups Q1K, Q2K...QNK from line groups R1K, R2K...RNK that send selection signals connected to the respective decoding circuits D1, D2...DN;
Even if there are multiple selection requests, one will be selected based on the priority.
50 encoded outputs corresponding to selected selection requests
Roll 1. The example of the configuration of the priority encoder is not limited to this, and of course a system in which selection requests are selected in the order in which they occur is also effective. 52 is a decoder which decodes the encoded output 501 and outputs the decoding circuit D selected by the priority encoder 51.
1, D2...corresponds to one of the DNs. Selection approval is given to one of the selection approval line groups A1K, A2K...ANK.

Figure 6 shows the multiplexers X1 and X shown in Figure 1.
2,...XK...XM is a block diagram showing an example of the configuration of one XK.

61 is a multiplexer and encodes output 5
01, the respective input buffer sections IB1,
IB2...data line F1 for packets coming from IBN,
Input F2...FN, select the corresponding one, and output 601.

FIG. 7 shows the output buffer section 0B1 shown in FIG.
FIG. 2 is a block diagram showing a configuration example of one 0BK among 0B2...0BK...0BM.

71 is a buffer memory which inputs the output 601, temporarily stores it, and outputs the data to the packet data line 701 of the output port 0K. A control circuit 72 sends a set signal 70 to the buffer memory 71 when the output 601 is input. Reference numerals 702 and 703 are a packet sending line and a busy line, respectively, of the output port 0K, and when the busy line 703 is in the busy line state, the control circuit 72 issues a packet sending signal to the packet sending line 702, and sends out one packet.

FIG. 8 is a block diagram showing an example of a multi-stage network constructed using a plurality of transfer devices of the present invention.

81, 82, 83, and 84 are transfer devices of the present invention, each of which has two inputs and two outputs.

I11, I12, I13, and I14 are input ports of the two first-stage transfer devices 81 and 82. The connections between the first stage and next stage ports are 011 and I21, 012.
The output ports of the next stage transfer devices 83 and 84 connecting 013 and I22, and 014 and I24 are 02 and I23.
It is 1,022,023,024. 801,8
02 is setting information for each of the transfer devices 81, 82 and 83, 84 to determine which sub-bit string is extracted from the bit string of the packet. In FIG. It is set to extract the second bit.

This shows that two packets 85 and 86 have arrived from ports I11 and I13. It can be seen that the first and second bits of both packets 85 and 86 have values of "1" and "0", respectively. When the packet 85 enters the transfer device 81 from the input port I11, the first bit becomes "1".
Therefore, the signal is sent from the output port 012 and immediately enters the transfer device 84 from the next input port I23. Since the second bit of the packet 85 is "0", the packet 85 is sent to the output port 023 of the transfer device 84. Similarly, packet 86 is
It is sent out from the output port 023 through the path 13→014→I24→023. It should be noted here that two different packets 85 and 86 will come out of the same output port 023. In the conventional method, when two packets go to the same exit at the same time, it is detected beforehand;
It was necessary to delay one packet. If the transfer device of the present invention is used, there is no need to worry about such matters, and the packets can be kept on standby in each buffer memory and processed in order by the arbiter. Furthermore, since each transfer device determines the destination from a portion of the bit string of the packet, it can be seen that the destination determination process is distributed.

According to the present invention, there is provided a device that inputs packets consisting of a plurality of bit strings from a plurality of input ports and sends out the packets from a plurality of output ports, the input port inputting the packets to each of the plurality of input ports and temporarily storing the packets. A means for extracting a part of the bit string stored in the buffer section from a preset position, and a plurality of bit strings coming from a decoding circuit for decoding the extracted bit string and selecting one of the plurality of output ports. an arbiter that selects one of the selection signals; a multiplexer that takes out one packet from one of the input buffer sections corresponding to the one selection signal selected by the arbiter; and an output from the multiplexer. The present invention provides an efficient transfer device characterized by having an output buffer section for temporarily storing packets to be transmitted and transmitting the packets from a corresponding output port.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a transfer device showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration sequence of one IBJ among the input buffer sections IB1, IB2...IBJ...IBN shown in FIG. 3 shows means S1, S2...SJ...SN for extracting part of the bit string shown in FIG.
Block diagram showing an example of the configuration of one of the SJs, No. 4
The figure shows decoding circuits D1, D2...DJ shown in Fig. 1.
...A block diagram showing an example of the configuration of DJ, one of the DNs,
Figure 5 shows the arbitrators A1, A2...AK... shown in Figure 1.
A block diagram showing a configuration example of AK, one of AM,
Figure 6 shows the multiplexers X1 and X2 shown in Figure 1.
...XK...A block diagram showing an example of the configuration of XK, one of XM, Figure 7 is the output buffer section 0 shown in Figure 1.
A block diagram showing an example of the configuration of one 0BK among B1, 0B2...0BK...0BM, and FIG. 8 is a block diagram showing an example of a multi-stage network configured using a plurality of transfer devices of the present invention. It is. In the figure, IB1, IB2...IBJ...IBN are input buffer units, S1, S2...SJ...SN are means for extracting part of the bit string, D1, D2...DJ...DN are decoding circuits, X1, X2...XK... XM is a multiplexer, A1, A2...AK...AM is an arbiter, 0B1,
0B2...0BK...0BM is the output buffer section, 21,
71 is a buffer memory, 22 and 72 are control circuits,
31 is a bit string of packet data, 32, 61
is a multiplexer, 41 and 52 are decoders, 42
is an OR circuit, 51 is a priority encoder,
81, 82, 83, 84 are transfer devices, 82, 86
indicates a packet, respectively.

Claims (1)

[Claims] 1. A transfer device that inputs a packet consisting of a plurality of bit examples from a plurality of input ports and sends the packet from a plurality of output ports, and an input buffer that inputs the packet to each of the plurality of input ports and temporarily stores the packet. a means for extracting a part of the bit string stored in the input buffer section from a predetermined position; and means for decoding the extracted bit string and outputting the extracted bit string to one of the plurality of output ports. a decoding circuit that selects one of the plurality of selection signals coming from the plurality of decoding circuits to each output port, an arbiter that selects one of the plurality of selection signals coming from the plurality of decoding circuits to each of the output ports, and one of the selection signals that corresponds to the one selection signal selected by the arbiter. a multiplexer for taking out one packet from one of the plurality of input buffer sections; an output buffer section for temporarily storing the packet output from the multiplexer and transmitting the packet from the corresponding output port; A transfer device characterized by having the following.