JPS6339929B2 - - Google Patents

Description

Claim 1: A controller for controlling a digital device, comprising three control memories each containing the same set of microinstructions, each of the microinstructions having a control field for controlling the digital device. , a jump address field that specifies the location of the next microinstruction when each microinstruction is to jump to a subroutine or return from a subroutine instruction; an instruction field identifying whether the instruction is a return instruction or whether no action is requested; three address registers containing addresses of instructions; an instruction coupled to each of said memories and said digital device to receive control and instruction fields of a microinstruction retrieved from one of said control memories; registers; interconnect means coupled between each of said control memories and address registers of other control memories for providing jump addresses to address registers of said other control memories; and said instructions of said instruction registers. field portion and said address register to identify one of said registers as a program counter, to identify one of said registers as a jump address register, and to identify one of said registers as a subroutine. and logic means for specifying as a register for a return from the microcontroller. 2. The logic means is configured to identify different address registers as program counters depending on whether the microinstruction currently being executed is a jump to a subroutine instruction or a return from a subroutine instruction. 2. A microcontroller according to claim 1, wherein the microcontroller comprises: 3. The microcontroller further comprises a multiplexer coupled between the respective control memory and the instruction register to select an instruction field and a control field of one of the microinstructions retrieved from the respective control memory. A microcontroller according to claim 1, comprising: 4. The microcontroller further comprises a plurality of multiplexers, each of the multiplexers connected between each of the address registers and a jump address output of another control memory, the multiplexer further comprising an external source of the address of the microinstruction. A microcontroller according to claim 1, coupled to a microcontroller according to claim 1. 5. The microcontroller of claim 1, wherein each of said address registers is a register counter that is incremented to sequentially retrieve a sequence of microinstructions from its corresponding control memory. 6. The microcontroller is further coupled between the respective registers and memory;
2. The microcontroller of claim 1, further comprising timing means for applying a microinstruction control field to said instruction register at respective clock times. 7. A microcontroller for controlling a digital device, further comprising three control memories each containing the same set of microinstructions, each of the microinstructions having a control field for controlling the digital device; When said respective microinstruction should jump to a subroutine,
or a jump address field that identifies the location of the next microinstruction when a subroutine instruction should return, and whether a particular microinstruction is a jump or return instruction, or does not request any action. said controller further comprises: three address registers provided for each said control memory containing the address of the next microinstruction to be fetched; an instruction register coupled to a digital device to receive control and instruction fields of microinstructions retrieved from one of said control memories; and an address register of each of said control memories and the other control memory. interconnection means coupled between said instruction field portion of said instruction register and said address register for providing a jump address to said other control memory address register; a program counter, one of said registers as a jump address register, and one of said registers as a register for a return from a subroutine; condition selection means for receiving a condition signal to specify that a conditional branch is required in the execution of said sequence of microinstructions, said logic means comprising said condition selection means and said three address registers; a microcontroller coupled between said digital device for selecting which of said control memories to provide a next microinstruction upon receiving a condition signal from said digital device. 8. The microcontroller further comprises a multiplexer coupled between the respective control memories and the instruction registers for selecting an instruction field and a control field of one of the microinstructions retrieved from the respective control memories. 8. The microcontroller according to claim 7, comprising: 9. The microcontroller further comprises a plurality of multiplexers, each of the multiplexers connected between each of the address registers and a jump address output of another control memory, the multiplexer further comprising an external source of the address of the microinstruction. 8. A microcontroller as claimed in claim 7, coupled to. 11. The microcontroller of claim 7, wherein each of said address registers is a register counter that is incremented to sequentially retrieve a sequence of microinstructions from its corresponding control memory. RELATED APPLICATIONS United States Patent Application Serial No. 438702 entitled "Multiple Control Storage System for a Pipelined Microcontroller" filed by Carlos F. Horvath on November 3, 1982.
No. (Special Publication No. 59-502080) “Multiple control storage in a pipelined microcontroller for handling nested subroutines” filed by Carlos F. Horvath on November 3, 1982 United States Patent Application Serial No. 438703 entitled
59-501998). FIELD OF THE INVENTION This invention relates to pipelined microcontrollers, and more particularly to such controllers that utilize multiple control memories to perform parallel operations, thereby reducing cycle time losses. Description of the Prior Art Microprogramming is a technology that replaces the macroinstruction decoding logic circuit in a processor with memory, which includes memory for each gate in the processor so that different macroinstructions can be executed. Various control signals are stored for activating the . These control signals may be entirely encoded, partially encoded, or unencoded, depending on the desired word length of the corresponding microinstruction. The macroinstruction operator then serves as an address to control storage or microinstruction memory. The use of such microprogramming techniques provides a great deal of design flexibility in the architecture. It is important to note that the types of control signals that can be generated are not fixed for any particular processor, and that different high-level programming languages are used for specially manufactured mainframe computers. This is because even if a language is designed for a specific language, it can be selected for emulation or interpretation with a host of that language. Because of this flexibility in design, almost all small and medium-sized programming systems and certain microprocessors are constructed using this technology. However, accessing or receiving a macroinstruction from control storage requires more time than if the same macroinstruction operator were to be decoded by the decoder logic. For this reason, hardwired logic circuits are preferred when designing large, high-speed processors. A technique to improve speed and reduce the clock time required to execute a microinstruction is to pipe the fetch of a macroinstruction operator (microinstruction address) with the execution of a previous microinstruction. Techniques exist to create lines or overlaps. Such techniques are described in US Pat. No. 3,886,523 to Ferguson et al. However, even with such overlap techniques, there are still sequences of clock times in which the microcontroller is not being used due to changes in the routine being executed. That is, the data processor does not execute a single sequence of instructions at either the macro-instruction level or the micro-instruction level. Periodically, internal or external conditions occur that require a sequence of instructions to branch to other routines and provide an appropriate response to the condition. Additionally, many routines are formed as a series of nested subroutines,
This requires the processor to jump to a subroutine and return from this subroutine to some other location different from the parent routine that was being executed. As mentioned above,
In a pipelined microcontroller, this would require fetching a new subroutine and discarding the current sequence being executed again, thereby losing cycle time. Therefore, a primary object of the present invention is to provide an improved microcontroller for a data processor that minimizes clock cycle loss. Another object of the invention is to provide an improved microcontroller for a data processor that allows for overlap between instruction fetching and conditional branch instruction fetching. Yet another object of the invention is to provide an improved microcontroller for a data processor that allows jumps to and returns from subroutine instructions to overlap with current fetch instruction fetches. be. SUMMARY OF THE INVENTION To achieve the above objects, the present invention is directed to a microcontroller for controlling a digital device formed from a plurality of control stores, each of which has a corresponding control store. It has register counters that address different locations within the device.
Each control store is accessed on each clock cycle so that one of the microinstructions retrieved from the selected control store
It has an instruction register for receiving one. In this way, a microinstruction is placed in the instruction register on each clock cycle, even if the previous microinstruction was a conditional branch, a jump to a subroutine, or a return to a subroutine instruction. Given. To reconcile jumps to subroutines and corresponding returns from subroutine instructions,
The corresponding addresses of this return subroutine are stored in the pushdown stack, in the opposite order of the one in which they were placed at the top of the stack, and in the selected register counters mentioned above. It is beginning to be given to one. Therefore, the nature of the invention is such that multiple microinstructions can be provided to the instruction register on each clock cycle, so that the instruction register can receive the appropriate microinstruction on each clock cycle. Present in a microcontroller with multiple memories.

[Brief explanation of the drawing]

The above-mentioned objects and other objects, advantages and features of the present invention will become more apparent from the following description with reference to the drawings. In these figures, FIG. 1 is a conceptual diagram of a conventional microcontroller. FIG. 2 is a conceptual diagram of the microcontroller of the present invention. FIG. 3 is a sequence diagram of instructions representing a program segment as executed by the present invention. FIG. 4 is a conceptual diagram of an arbitration logic circuit used in the present invention. FIG. 5 is a diagram depicting a truth table showing the operation of the present invention. General Description of the Invention The present invention is configured to provide control signals that activate various gates and registers within a microprogram data processor during each clock cycle of operation. This control signal may be coded or uncoded. As mentioned above, in conventional microprogram devices, whenever a conditional branch instruction is encountered, or a jump instruction to a subroutine or a return instruction from a subroutine is encountered, clock time is lost. Ta. Such a conventional microprogram controller is shown in FIG. As shown in FIG. 1, the corresponding microinstructions are stored in a control memory 10, which may be, for example, a read only memory (ROM). As explained in more detail below, each microinstruction includes a field of control signals that may be fully coded or partially coded. It may be present or partially unencoded. In addition, each microinstruction is subject to a conditional branch, whether the current microinstruction is followed by the next microinstruction in the sequence, or by a jump to or return from a subroutine instruction. Contains a sequence field that specifies whether it is an instruction. This field also alternately contains a jump address or a return address. When this control store is addressed by the address register 11, the corresponding microinstruction is read in parallel and applied to the instruction register 12, from where this field is retrieved.
Activates or activates a digital device to be controlled, such as an arithmetic logic unit. When executing a conditional branch or jump to subroutine instruction, the sequence field provides an alternate address to multiplexer 13 during the same clock cycle. When a conditional branch instruction is being executed, the conditional jump control circuit determines whether the accompanying instruction is true or false, and if true, gives a signal to the multiplexer 13 and sends a signal to the multiplexer 13, The address is transferred to the address register 11. At both the macro-instruction level and the micro-instruction level, extensive use of data processors has the special property of using a push-down stack or set of first-in-last-out registers. Such a stack may require a return address to be stored when jumping to a subroutine, and on the other hand, the subroutine may need a return address when jumping to another subroutine. It is particularly useful for a number of reasons.
With nested subroutines in this way, each time a jump into a subroutine occurs, the return address is placed at the top of the stack, and when additional return addresses are subsequently placed at the top of this stack, “Butsuyu”
Will be taken down. As the various subroutines exit, they are given the necessary return addresses starting at the top of the stack in the reverse order in which they were entered. Such a stack for a microcontroller is shown in FIG.
It is shown as When the microinstruction currently being executed from instruction register 12 is a return from a subroutine instruction, the appropriate address is provided from control stack 16 via multiplexer 13 to address register 11. The microprocessor shown in FIG. This is accomplished in the controller of FIG. 1 by incrementing the contents of address register 11 each time it is presented to control store 10. With this kind of action,
A new microinstruction is applied to the instruction register 12 at each clock time. However, when a conditional branch, jump to a subroutine, and return from a subroutine instruction is encountered, the contents of address register 11 must be replaced before the appropriate action can be taken, thereby There was a loss of clock cycles. To reduce this loss of clock cycles, the present invention is arranged to provide the output of the control store to the instruction register on each clock cycle in the manner shown in FIG. . In FIG. 2, there are three different storage controllers 20a, 20b, 20c, which are configured to provide a field of control signals along with sequence information to the instruction register 22 by a multiplexer 22a. There is. However, the jump address JA, which can also be used for conditional branches and returns from subroutine instructions, is stored in register counters 21a, 21 other than the register counters corresponding to the respective control stores 20a, 20b, and 20c.
b and 21c, respectively. For this purpose, register counters 21a, 21
b, 21c have multiplexers 23a, 21c, respectively.
23b and 23c are provided to determine which of the jump addresses from other control stores is to be received or to determine which of the jump addresses from the main stack 26 is to be received in the event of a return from a subroutine instruction. Select whether or not to receive the first one. As shown in FIG. 2, each of the register counters also has a first
It is also possible to receive the next address from an external source, as was done in the conventional controller of the figure. Which input is selected by each of multiplexers 23a, 23b and 23c corresponds to sequence information given to instruction register 22 from the control storage device selected at that time. This can be known from the output from the arithmetic logic circuit 27. Control stores 20a, 20b, 20c are provided with the same set of microinstructions. However, when looking at any given time, each individual control memory is transferred from the arithmetic logic circuit 27 to the corresponding register counter 21a, 21b, 21c.
Depending on the count load information given to
It is used in one different mode out of the three modes. These three modes are "Program Counter Register,""Jump Address Register," and "Start of Stack Register." Each of the three registers is
It has a 2-bit register that functions as a tag register, and the state of the corresponding register counter and the designated destination can be known by the value loaded into the corresponding tag register. Here, a register counter is used in place of the address register 11 in FIG. 1, so the incrementer 15 in FIG. 1 is not necessary. The operations described in detail below control the three control stores 20a, 20b, and 20c.
transfers a field of control information to the instruction register 22 on each clock cycle if the microinstruction currently being executed is a conditional branch instruction, a jump to a subroutine instruction, or a return from a subroutine instruction. You can keep giving. That is, if register counter 21a has been designated as the program counter register, it will continue to provide addresses to control storage 21a and its own contents until a branch, jump or return instruction is indicated in instruction register 22. continues to increment. During this period, one of the registers 21b and 21c is designated as the jump address register, and the other of these is designated as the first of the stack registers, so that the three control stores 2
0a, 20b, 20c all provide microinstructions to multiplexer 22a. 3 taken out
The two microinstructions concern the current program count address, jump address and the top of the stack, i.e. the return address from the subroutine; one of these microinstructions is selected by the arbitration logic 27. and provided to instruction register 22 on each clock cycle.

[Detailed description of the invention]

FIG. 3 illustrates a sequence of microinstructions as may reside in each control memory or ROM used in the present invention. As shown here, the first field represents the jump address JA, where the current microinstruction requests a conditional branch, jump to or return from a subroutine. It has the property of specifying the address of the next microinstruction to be executed. The second field, marked with an asterisk, is the instruction field, which includes branching, branching,
It contains as many bits as necessary to identify a jump or return, or, when neither is present, to identify a sequence of register counters that function as program counter registers. An example of a typical microinstruction is the instruction register 22.
are shown in more detail in FIG. 2 by the respective fields forming the . Each ROM
Note that the jump address stored as part of a microinstruction in a microinstruction is not provided to the instruction register. The instruction field shown here includes a 1-bit jump to the subroutine field, a 1-bit return from the subroutine, a 1-bit jump or conditional branch field, and a zero to enable exclusive OR gate 24a to execute the condition. It includes a 1-bit inversion field that transmits the jump enable signal from selection register 24 to arbitration logic 27. The condition code selection in instruction register 22 includes as many bits as are needed to select any one of the condition signals applied to condition selection logic 24. The remaining fields in instruction register 22 present in the sequence of microinstructions shown in FIG. 3 are used to activate the digital device being controlled. When all bits in the instruction field of a microinstruction are zero, the program counter register continues to increment through the sequence of instructions shown in FIG. When a particular register counter is designated as a "program counter register", it is sequentially incremented by one in each subsequent ROM. Also, a particular register counter is designated as a "jump address register" to hold the address of the instruction that should take the next branch if the condition being tested requires it. When a particular register counter is designated as a "jump address register", it is loaded on each clock so that there is always an instruction to take a branch to the output of the corresponding ROM. Finally, when a particular register counter is designated as the "top of the stack register", it will contain the return address of the calling program whose address was originally loaded. This "top of the stack register" is loaded only when a "push" instruction is encountered. In this case, the old contents of this register have been moved to the main stack 26 of FIG. This register counter always holds the contents of the topmost element of the main stack. However, when a return instruction is encountered, this instruction register can be immediately loaded with the contents of the address where the return is to be specified. This is, of course, possible by retrieving the contents of the location where the "top of the stack register" returns. To illustrate what happens in the various register counters for different sequences of microinstructions as shown in FIG. 3, and what results as the output of the corresponding ROM in FIG. Thus, with the present invention, it may be possible to see how microinstructions are provided to instruction register 22 (of FIG. 2) on each clock cycle. For example, if microinstruction 10 of FIG. 3 is currently being executed and register 21c of FIG. 2 is designated as a "program counter register," then register counter 21b is designated as a "jump register." Also, register 21a is designated as the "head of the stack register." The control and instruction fields of microinstruction 10 are now in instruction register 22 and register counter 2
1c is incremented to hold the address of instruction 11, and register counter 21b holds the jump address field of microinstruction 10 (for example, this jump address is
0), and the register counter 21a holds the first stack address (for example, the contents of this register are set to 90).
The output of ROM 20c is a control data field, and the instruction field of instruction 11 having (75) as the jump address is applied to multiplexer 23b of FIG. The output of ROM20b is the control data field and instruction field of instruction 100, and its jump address (300).
is applied to multiplexer 23c in FIG. The output of ROM 20a is the control data field and instruction field of microinstruction 90, whose jump address (400) is provided to both multiplexers 23b and 23c. If the microinstruction 10 is a jump instruction, the register counter 21b becomes a "program counter register" and the instruction register 21b becomes a "program counter register".
2 will contain the control data field and instruction field of the microinstruction 100, and
Jump address (300) to register counter 21c which is “jump address register”
is given, but the contents of the register counter 21a are not affected. At this point, the output of the ROM 20c has become the control data field and instruction field of the instruction 300, and its jump address (8) has been given to the multiplexer 23b. The output of the ROM 20b is now the control data field and instruction field of the microinstruction 101, and its jump address (35) is given to the multiplexer 23c. No change has occurred in the output of the ROM 20a. When the microinstruction 10 is a jump to a subroutine instruction, the register counter 21b becomes a "program counter register" and its contents (100) are incremented by 1, and the contents of the instruction register 22 are changed to the control data field of the instruction 100 and It becomes a command field.
Register counter 21a now becomes the "jump address register" and contains the jump address (300) of microinstruction 100, while register counter 21c is the "start of stack register".
Therefore, the content (11) is maintained. ROM2
The output of 0b serves as the control data field and instruction field of the microinstruction 101, and its jump address (35) is sent to the multiplexer 23.
is transmitted to a. Register counter 21a contains the jump address of microinstruction 100 (300), and the output of register counter 21a is the control data field and instruction field of instruction 300, whose jump address (8) is transmitted to multiplexer 23b. Ru. ROM20c
The output remains the same. During,
The previous contents of register 21a (identified as 90) are placed at the beginning of main stack 26 via multiplexer 26a. When the microinstruction 10 is a return from a subroutine instruction, the register 21a now becomes the "program counter register" and is 1
is incremented by The instruction register 20 includes a control data field and an instruction field for an instruction 90, and the output of the ROM 20a is an instruction 91.
The jump address is applied to multiplexer 21b. The register counter 21b becomes a “jump address register”,
The output of ROM 20b becomes the jump address of the previous microinstruction and the corresponding control data and instruction fields. Register counter 21, which is the “head of the stack register”
The contents of c will include the contents previously placed at the beginning of the register, and the output of ROM 20c will contain the contents of the microinstruction at that address. The logic circuit that determines the role distribution of the register counters is included in the arbitration logic circuit 27 of FIG. This logic circuit is nothing but a state machine. Two bit registers 27a, 27b and 27c (see FIG. 4) associated with each register counter are present in this logic circuit. The signal that drives this logic circuit is the second
This occurs in the instruction register 22 of the figure and the condition selection unit 24 of FIG. The output of arbitration logic circuit 27 is shown in more detail in FIG. These outputs drive data/address multiplexers 23a, 23b, 23c and also
register counters 21a, 21b and 21
Drives the load/count enable input to c. As mentioned above, the arbitration logic circuit 27 of FIGS. 2 and 4 is essentially a state machine, which determines the type of instruction being executed and the state or mode of the three register counters 21a, 21b and 1c. It corresponded to each combination of. There are next states of registers and register counters and source selection actions. Second
Arbitration logic circuit 2 in Figures and Figure 4
The operation of each register and ROM of the present invention controlled by 7 is detailed in the table in FIG. In this FIG. 5, the inputs and outputs of arbitration logic circuit 27 are depicted, along with the current and next states of the respective register counters. The first line of Figure 5 shows the type of instruction currently being executed, including a no-action NA, subroutine where the register counter designated as the "program register counter" continues to increment. Jump JMS,
and returns from subroutines, RETs, jumps or conditional branches JMP. Second
The rows indicate various combinations of the modes of the respective register counters, where A means the register counter 21a in FIG. 2, B means the register counter 21b, and C means the register counter 21c, respectively. . The modes of the different register counters are as follows: "jump address register" is "J", "start of stack register" is "S",
Also, write the “program counter register” in C,
each represents. The third line shows each subsequent state or mode. The fourth line shows the actions that occur in each of the register counters, where L indicates that the register counter is being loaded with a new address, O indicates that the register counter retains its current contents, and , indicates that the register counter is being incremented. The fifth line indicates which ROM or control store is the source of the new address given to the loaded register counter.
Line 6 indicates which ROM is the source of the instruction and control data fields loaded into instruction register 22 of FIG. 2, and line 7 indicates which ROM is the source of the instruction and control data fields loaded into instruction register 22 of FIG. If the source of the placed address exists, it indicates which register counter the source is. For example, consider the first combination of modes in a no-action (NA) type of instruction. The fact that AR is equal to J means that the register counter 21a in FIG. 2 is in the "jump address register" mode, and the register counter 21a in FIG.
1b is in the "head of stack register" mode, and register counter 21c is in the "program counter register" mode. The next line on the same line is
Indicates that the states or modes of various registers have not changed. The fourth line of this line shows that register counter 21a has been loaded with a new address, register counter 21b has maintained its contents, and register counter 21c has been incremented. The fifth line is in the register 21a as shown in FIG.
Indicates that the jump address is being loaded from the ROM 20c. Also, the IS of the 6th line of this line
indicates that instruction register 22 of FIG. 2 is loaded with respect to ROM 21c, and the last line of this line indicates that nothing is placed at the beginning of stack 26 of FIG. Another example of the actions of the present invention relating to the execution of a jump instruction JMS to a subroutine is shown in the first line of the JMS category of the truth table in FIG. The register counter 21a is in "jump address register" mode,
Register counter 21b is in "top of stack" mode and register 21c is in "program count register" mode. At the next clock time, the states of the various register counters are such that register counter 21a becomes the "program counter register," register counter 21b becomes the "jump address register," and register counter 21c becomes the "start of stack register." ”. The next line is
The register counter 21c is incremented,
It shows that a new address is loaded into the register counter 21b, and the next line shows that the source of the new address is the ROM 20a. The next line shows that instruction register 22 of FIG. 2 is loaded from ROM 20a, and the last line shows that register 21b is placed at the beginning of stack 26 of FIG. With the example described above, the rest of the table in FIG. 5 will be clear. However, in the return from a subroutine of type RET instruction, the Z in the fifth line indicates that the top of the stack is the source for loading each register counter. Summary Microcontrollers for digital devices, that is, at each clock time,
A microcontroller is disclosed that is configured to be able to provide microinstructions to a corresponding instruction register from one of three different control memories or ROMs. In this way, a sequence of microinstructions can encounter conditional branches to other subroutines, jumps to subroutines, and returns from subroutines, where the correct No clock cycles are lost because microinstructions are always ready to be presented to the instruction register. Although only one embodiment of the present invention has been disclosed here, it is obvious to those skilled in the art that modifications and changes can be made without departing from the spirit and scope of the claims. Will.