JPS6337757A - Frame signal system - Google Patents

Abstract

PURPOSE:To handle diverse services by collecting many frames which include CHs of a monitor signal and a voice or data into a multiframe, and making the logical bit of the multiframe display bit of a start frame different from those of other frames. CONSTITUTION:The logical value of the frame signal of the final frame of the multiframe from a channel device 2 is set to 0 and then multiframe bits of respective frame signals of frames except the final frame are all set to a logical value 1 and received, so all the multiframe display bits of respective frames other than the multiframe display bit having the logical value 0 in the start frame of the multiframe outputted by a switching circuit 31 have the logical value 1. Consequently, the multiframe display bit which has the logical value 0 is detected to decide the start frame of the multiframe and a monitor signal necessary for diverse services can be discriminated based on the multiframe display bit.

Description

[Detailed Description of the Invention] [Summary] In order to increase the number of supervisory signal bits for each channel, the supervisory signal bits attached to the channel and a plurality of channels (8
A multi-frame is constructed by collecting a large number of frames containing a number of monitoring signal bits, and a multi-frame display bit with a different logic value from other frames is added to the first frame, and each frame is set to 121. It is intended to identify channel monitoring signals.

[Industrial application field]

The present invention relates to improvements in frame signaling in digital switching systems.

Digital switching systems are beginning to be put into practical use as next-generation switching systems.

As the number of communication services provided by this switching system increases, the number of monitoring signal bits representing the state of a channel (line) must also increase, and a signal system that transmits signals in a signal format suitable for this purpose is required.

For this reason, it is desired to provide a frame signaling system that transmits information using a highway format in which a large number of frames that combine a plurality of supervisory signal bits and channels are collected to form a multiframe.

[Conventional technology]

Figure 6 is a block diagram of a conventional frame signal system, and Figure 7 is a block diagram of a conventional frame signal system.
FIG. 8 is an explanatory diagram of a conventional highway format, FIG. 8 is an example of the structure of a conventional supervisory signal bit, and FIG. 9 is an explanatory diagram of the formation of a conventional highway format.

In FIG. 6, the subscriber's voice and the supervisory signal from the signaling device 1 are formed into a highway format (to be described later) in the communication path device 2, and then passed through the highway to the switching circuit 3 of the connecting device 3.
1 is input. The input is controlled by pulses from the timing circuit 33, a frame synchronization signal etc. are inserted at the output of the frame creation section 32, and the signal is outputted to the sending circuit 34 and sent out to the highway connected to the communication path device 2 on the receiving side. Ru.

The highway format transmitted on the highway is the 7th
As shown in Figure (a), 8 frames form a unit of 8 multi-frames. Inside each frame, there are 32 time slots (hereinafter referred to as TS) as shown in FIG. 7(b), TSO is assigned to frame signal TS, and TSI
-TS31 is assigned to voice or data channels (hereinafter referred to as CH), CHI to CH30 (TSI6
is empty).

The frame signal TS consists of 8 bits, bits 0 to 2 are used for frame synchronization, etc., and bits 3 to 7 are used for monitoring signals.

From an operational perspective, the number of CIs entering and leaving the exchange is 6 per route.
Each channel is set as a unit and is called a handling group (hereinafter referred to as HG).

Therefore, the 30 CHs are composed of 5HG (HGI to HG5), and the monitoring signal bits of each CH of each) IG are as shown in FIG.
C) bit 3~? (HGI to HG5).

Figure 8 shows an example of the structure of the supervisory signal bits. In the first frame, a multi-frame signal F (repeating logic value 1 and logic value O within each HG) indicates the beginning of each HG, and in the second and subsequent frames, each CIs belonging to the HG are entered with numbers. The * mark in the eighth frame indicates a transmission path failure notification bit.

In the configuration of the supervisory signal bits in Fig. 8, the supervisory signal bits of each CH are repeatedly transmitted every 8 multiframes, but the position of the multiframe signal F is as in this example (not limited to the first frame). , IIG, and can be placed at any frame position.

The highway information transmitted in the highway format as shown in FIG. 9(a) is sent to the input point a in FIG.
3, as shown in FIG. 9(b), the T of each frame is
A pulse is sent between bits O to 2 of SO, and the switching circuit 31
The input is switched to the frame creation circuit 32 side.

Since the output of the frame creation circuit 32 is logical 1 in this case, the output of the switching circuit 31 is as shown in FIG. 9(c).
A logic value of 1 is inserted into bits 0-2 of rso. T.S.
Bit O of O is a frame synchronization bit (in this case, logical value 1), thereby establishing frame synchronization.

When the pulse from the timing circuit 33 disappears, the input of the switching circuit 31 is switched to the point a side, and the highway information is input and output as is.

Therefore, the TSO of each frame includes supervisory signals (HGI~
Since the supervisory signal bit corresponding to each CH of HG5 is inserted as is, and the data of CHI to CH30 is also transmitted as is, the highway format signal shown in FIG. 9(c) is output to the output point C of the switching circuit 31. and the sending circuit 3
4 to the highway to the terminating channel device.

[Problem that the invention seeks to solve]

In the conventional system, each CI has only one supervisory signal bit.

However, taking data terminals as an example, monitoring signals are used to determine whether the connection is good or not by performing loopback tests between the digital service unit (hereinafter referred to as DSU) and the exchange in order to identify failure points between the exchange and the data terminal. New bits are required.

As described above, since a large number of supervisory signal bits are required to provide various services, there is a problem that cannot be addressed by conventional methods.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

4 is a data terminal; 5 is a DSU that connects the data terminal 4 to the communication path device 2; 1 is a signal device that sends a monitoring signal regarding the status of CI used by telephone terminals, data terminals, etc.; 2 is a signal device that sends voice and data. It is a communication path device that combines a CH, a monitoring signal, etc. to form a frame for information transmission, and transmits a large number of frames in a multi-frame format on a highway.

Reference numeral 3' denotes a connecting device that connects the communication line equipment on the transmitting side and the receiving side to the highway, 31 a switching circuit that changes the content of the frame signal TS in the highway format to be transmitted, and 34 the output thereof being transferred to the receiving side. This is the output path for sending data to the communication path device.

Reference numeral 35 relates to the present invention, and receives a multiframe bit with a logic value of 0 in the frame signal TS of the last frame of a multiframe, and transfers a multiframe display bit with a logic value of O indicating the first frame of the multiframe to the next multiframe. A frame signal section 36 added to the frame signal TS of the first frame is related to the present invention and is a timing circuit that supplies timing pulses to the frame signal section 35.

[Effect]

A multi-frame bit set to a logical value O in the frame signal TS of the last frame of the multi-frame is received from the channel device 2 by the frame signal section 35, and at this point a pulse is sent from the timing circuit 36 to the frame signal section 35. When the signal is sent, the output of the frame signal unit 35 that is input to the switching circuit 31 is set to a logical value O.

Frame signal TS of the first frame of the next multiframe
When a pulse is sent from the frame signal unit 35 to the switching circuit 31 at the time of the first bit of Then, the multi-frame display bit, which is the first bit of the frame signal TS of the first frame of the multi-frame, is set to the logical value O.

Since all the multi-frame bits of each frame signal TS other than the last frame are received with the logical value set to 1, each of the multi-frame bits other than the multi-frame display bit with the logical value O in the first frame of the output multi-frame of the switching circuit 31 All frame multi-frame display bits are logical 1
becomes.

Therefore, by detecting the multi-frame display bit with a logical value of 0, the first frame of the multi-frame can be determined, and the monitoring signal bit of each CH can be determined based on the multi-frame display bit.

(Example〕 The present invention will be specifically explained below with reference to illustrated examples.

FIG. 2 is a block diagram of a frame signal system according to an embodiment of the present invention, FIG. 3 is an explanatory diagram of a highway format according to an embodiment of the present invention, and FIG. 4 is a configuration example of a frame signal time slot according to an embodiment of the present invention. , FIG. 5 is an explanatory diagram of the formation of a highway format according to an embodiment of the present invention. The same reference numerals indicate the same objects throughout the figures.

In Figure 2, a D type flip-flop (hereinafter referred to as F
37. The Nant gate 38 and the inverter 39 correspond to the frame signal section 35 in FIG.

The highway format of the input point d from the highway in FIG. 2 is as shown in FIG. 3(a) (48 frames form a unit and 48 multi-frames are formed).

There are <32 TS inside each frame as shown in Fig. 3(b), TSO is assigned to frame signal TS, and TSI to TS are allocated to frame signal TS.
31 is C for voice or data! It is assigned to CH11 to CH30 (TS16 is empty). The frame signal TS consists of 8 bits, bits O to 2 are used for frame synchronization, etc.
Bits 3-7 are used for supervisory signals.

CHs entering and leaving the exchange are set in units of 6 CHs for one route from an operational standpoint, as in the conventional technology, and are called HG. The above 30CII is 5HG()IGI-HG
5), and the monitoring signals of each 11G CH are shown in Figure 3 (
It is accommodated in bits 3 to 7 (HGI-HG5) of C).

Bit 0 of the first frame in FIG. 4 is a multi-frame display bit MF (logical value O in this case), and bits 1 and 2 are used for other purposes, but are currently set to logical value 1. Bits 3 to 7 are for HGI to HGS, and the monitoring signal S1 of CHI to C)15 is recorded.

Bit 0 from the second frame to the 48th frame takes a logical value of 1 in the multi-frame display pin (MP) and is used for frame synchronization.

HGI of the 1st to 8th frames as a group of 8 frames
~HG5 is a plurality of monitoring signals 3 corresponding to CHI~CH5
1 to S8 are sent out sequentially.

HGI to HG5 of the 9th to 16th frames are CH6 to CH
A plurality of monitoring signals 31 to S8 corresponding to the IO are sequentially sent out.

The monitoring signals continue to be transmitted in the same manner, and the last group, HGI to HG5 of the 41st to 48th frames are C)126 to
A plurality of monitoring signals 81 to S8 corresponding to CH30 are sequentially sent out.

As mentioned above, the monitoring signal of each CH in the multi-frame of the present invention is determined based on the multi-frame display bit set to the logical value O of the first frame. Monitoring signals required for service can be identified.

The formation of the multi-frame display bit structure of the first frame will be explained with reference to FIGS. 2 and 5.

From the highway to the input point d of the connecting device 3
), the multi-frame bit M is set to the logical value O of bit 2 of the frame signal TS of the 48th frame.
(All multi-frame bits M at the same bit position other than this frame are given a logical value of 1) is added to the input of the frame F37, and at the same time, the timing circuit 36 as shown in FIG. 5(e) The pulse sent to DFF37
, the output Q of the DFF 37 becomes a logic value 0, and the point r becomes a logic value O as shown in FIG. It remains as it is until M (logical value l) is reached.

At the beginning of the frame signal TS of the next first frame, the timing circuit 36 applies a pulse with a time width of 3 bits to the Nant gate 38 as shown in FIG. At the same time, as shown in FIG. 5(h), the input of the switching circuit 31 is switched to
Switch to the side.

At this time, point f has a logical value of 0 until bit 2 of the frame signal TS arrives, and therefore, as shown in FIG. 5(j), the O bit of the frame signal TS of the first frame, that is, the multi-frame display bit key becomes the logical value O.

! For <1.2 bits, since there is no pulse at the point, the input of the switching circuit 31 returns to the Nant gate 38 side and a logic value of 1 is inserted.

Since the pulse at point g disappears after the 3rd bit, the Nant gate 38 outputs the input as it is to the switching circuit 31, the monitoring signal sent out by the signal device 1 is output, and then the CH information is transmitted, as shown in FIG. ) as shown in the highway format.

Since the θ bit in each frame signal TS from the second frame onwards, that is, the multi-frame display bit MFc, and the multi-frame bit M of the highway format on the input point d side have a logical value of 1, and the point f also has a logical value of 1. Each multi-frame display bit has a logical value of 1 and can be distinguished from the first frame.

Therefore, by using the multi-frame display bin MF of logical value 0 as a reference, it is possible to identify the monitoring signal having the configuration described in FIG. 4.

〔Effect of the invention〕

As explained above, in the present invention, a large number of frames including a monitoring signal and a CI of audio or data are collected to form a multiframe, and the multiframe display bit of the first frame is set to the logical value of the multiframe display bit of other frames. By making the CHs different from each other, the number of CH monitoring signals can be increased by making it possible to identify the monitoring signals of each CI, and it is possible to cope with a variety of services.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of a frame signal system according to an embodiment of the present invention, Fig. 3 is an explanatory diagram of a highway format according to an embodiment of the present invention, and Fig. 4 is a diagram of the present invention. FIG. 5 is an explanatory diagram of the formation of the highway format in the embodiment of the present invention. FIG. 6 is a block diagram of a conventional frame signal system. FIG. 7 is a diagram of a conventional frame signal system. FIG. 8 is an explanatory diagram of the highway format. FIG. 8 is an example of the structure of a conventional monitoring signal bit. FIG. 9 is an explanatory diagram of the formation of a conventional highway format. In the figure, l is a signal device, 2 is a communication path device, 3 is a connection device, 4 is a data terminal, 5 is a digital service unit, 31 is a switching circuit, 34 is a sending circuit, 35 is a frame signal section, 36 is a timing Shows the circuit.

Claims (1)

[Claims] Data from a data terminal (4) issued by a voice or digital service unit (5) and a channel for sending voice or data transmitted in connection therewith from a signaling device (1). A communication path device (2) that combines monitoring signals indicating the status into frames consisting of frame signal time slots and channel time slots and transmits them on the highway in a multi-frame format that collects a large number of frames; In a digital switching system consisting of a connecting device (3') that connects the communication line equipment on the transmitting side and the receiving side, there is a switching circuit (31) that changes the content of the frame signal time slot of the frame, and the output thereof is connected to the receiving side communication. The connecting device (3'), which is equipped with a sending circuit (34) that sends out to the network device, receives a multi-frame bit with a logic value of 0 in the frame signal time slot of the last frame of the multi-frame, and A logical value of 0 indicating
A frame signal section (35) that adds a multi-frame display bit of 1 to a frame signal time slot of the first frame of the next multi-frame, and a timing circuit (36) that supplies a timing pulse to the frame signal section (35) are provided. A frame signal system characterized by: