JPS6337511B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a field effect transistor made of a multi-component semiconductor material using microfabrication technology that has low on-resistance in switching characteristics and high-speed response characteristics. (hereinafter abbreviated as FET).

(b) Background of the technology In recent years, active devices used to construct high-speed logic circuits have been developed using multi-component semiconductors with large carrier mobility, such as gallium arsenide (GaAs) and gallium aluminum arsenide (GaAlAs). Although there is a trend toward fabrication using materials, many semiconductor devices, especially FETs, using these materials are
As shown in the figure, it had a mesa-type structure. Here, 1 is semi-insulating (hereinafter abbreviated as SI).
The semiconductor substrate is made of GaAs, 2 is an active layer made of, for example, n-type GaAs, S, D, and G are source, gate, and drain electrodes, respectively, and AR is an active region.

If the part indicated as 3 in the figure is made of P-type GaAs, the FET becomes a junction gate FET (hereinafter referred to as JFET), and if this part is not present, it becomes a shot key barrier type FET (hereinafter referred to as SBFET). call)
becomes.

(c) Prior art and problems If these FETs are to be used in high-speed logic circuits, they must have high-speed response, that is, excellent high-frequency characteristics, and must have sufficiently low on-resistance. However, for this purpose, high precision is required in controlling the impurity concentration and dimensions (particularly the thickness d of the active layer 2) of the active layer 2.
By the way, the active layer thickness d is 0.2 to 0.3 μm in most cases.
It is often selected depending on the degree.

In addition, in order to keep the on-resistance sufficiently low and reduce power consumption, the distance between S and G and between G and D must be l.
In order to reduce G and increase the mutual conductance Gm, the length Gl of the gate electrode G must be set small, but as long as the above conventional structure is adopted,
It is extremely difficult to reduce the dimensions of l and Gl to 2μ or less, and this has been an obstacle in designing and manufacturing FETs with excellent switching characteristics.

(d) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention provides an excellent switching characteristic and low source by using a structure in which the device dimensions are not affected by photolithography and the dimensional limits of each process. ~ The purpose is to provide a FET that operates with a voltage between drains.

(e) Structure of the Invention According to the present invention, a semi-insulating semiconductor substrate 1, a gate 4 comprising a first conductivity type high impurity concentration semiconductor layer and having one slope, a semi-insulating semiconductor layer 5 covering a surface other than the slope; the semiconductor substrate 1; an active layer 2 of a second conductivity type provided on the surface of the semi-insulating semiconductor layer 5; A source 7S and a drain 7D provided on the active layer 2 divided into two by
Second conductivity type high impurity concentration semiconductor layer 6 directly under the electrode
S, 6D, and a step of forming a band-shaped gate having one slope on a semi-insulating semiconductor substrate and consisting of a first conductivity type high impurity concentration semiconductor layer; forming a semi-insulating semiconductor layer covering a surface other than one slope of the gate; forming an active layer of a second conductivity type on one slope of the gate, the semiconductor substrate, and the surface of the semi-insulating semiconductor layer; A second layer, which will become a source and a drain, is formed by molecular beam epitaxial growth from diagonally above the opposite side of the one slope of the gate.
A semiconductor device comprising the steps of forming a conductive type high impurity concentration semiconductor layer and forming electrodes for the source and drain from diagonally above the source and drain by a metal vapor deposition method. This is achieved by providing a manufacturing method.

(f) Embodiment of the invention FIG. 2 shows a semiconductor device according to the present invention, namely
Figure 3 is a side view of a JFET whose main material is GaAs, and a perspective view showing its structure, with the same symbols used for the same parts as in Figure 1.

First, in Fig. 2, 4 is a P+ type disposed on an SI-GaAs substrate (hereinafter simply referred to as the substrate) 1.
The GaAs portion has a ladder shape, and the portion 4 plays a role as a gate of the JFET of the present invention. The impurity concentration in this region 4 is set to a high concentration of about 1×10 ¹⁸ , but the impurity to be doped is, for example, beryllium (Be).
is used. And this part, gate 4
may be made of GaAlAs, and in this case, a heterojunction is formed at the part in contact with the active layer 2, that is, the lower right surface of the active region AR, so that the forward rise in the current-voltage characteristics exhibited by the junction is Since the voltage increases, the range of gate voltage application can be expanded. However, for convenience of explanation, the material of this portion will be explained below as P+ type GaAs.

As shown in Figure 2, this part, that is, the upper and right slope parts of gate 4, is made of SI-GaAs.
covered by layer 5. Furthermore, SI-GaAs
Layer 5, gate 4, and substrate 1 connected to gate 4
The FET active layer 2 is provided to commonly cover the three regions (including the left side H in the figure).

Furthermore, the portion of the active layer 2 that forms the left slope of the mountain-shaped portion, except for the portion shown as Z in ^FIG .
It is covered with high impurity concentration layers 6S and 6D made of GaAs, and gold germanium nickel (AuGeNi) alloy films 7S and 7D are disposed on the upper surfaces of both n+ type layers 6S and 6D, respectively, and the source S
and drain D electrodes are formed.

This AuGeNi alloy film is also applied to the bonding area 6 of the gate 4 as shown in Figure 3.
The gate electrode G is arranged as shown in FIG.

By the way, the part AR of the active layer 2 that is in contact with the left slope of the gate 4 is the part that becomes the active region in the JFET of this structure, and the contact length Gl is the effective gate length. first disposed on substrate 1 to configure
The GaAs layer has a thickness of, for example, about 1 μm. In other words, since the height of the ladder-shaped gate 4 is about 1 μm, the effective gate length Gl in the JFET with this structure is
It is understood that it can be made as short as about 1.3 μm.

Also, source S and drain D electrodes 7S, 7
The high impurity concentration layers 6S and 6D immediately below D are grown to a thickness of, for example, 0.5 μm by oblique irradiation with a molecular beam in the direction of arrow A in FIG. 2, as will be described later. For this reason, both of these impurity concentration layers 6S and 6D are formed separately, but due to the effect of the oblique irradiation of the molecular beam, the right end of the high impurity concentration layer 6S and the active area AR and the high impurity concentration layer 7D.
Each distance l between the left end of the active area AR and the active area AR is short, about 1 μm.

Because of this structure, the JFET shown in Figures 2 and 3
Since the distance l between S and G and between G and D of the JFET can be made very short, the resistance between S and D of the JFET is sufficiently low, and therefore the on-resistance becomes an extremely large value, and the active region n-type GaAs with high mobility AR
Because it is made using , its response speed is extremely fast, making it highly useful for high-speed logic circuits.

The structure of the JFET of the present invention has been described above, and below, using FIG.
The manufacturing process will be explained.

First, SI-GaAs substrate 1 with (100) plane as the main surface
P+ type GaAs doped with Be (the impurity concentration is about 10 ¹⁸ ) as shown in Figure 4a on the main surface of the
A layer 10 is uniformly formed, and a predetermined portion of the layer 10 is diagonally etched as shown by the dashed line to remove the P+ type GaAs layer 10a. In this case, the part shown as F is the part that becomes gate 4 in FIG. 2, but since the bonding area for gate 4 (the part shown as 6 in FIG. 3) must be made in advance The above-mentioned diagonal etching is performed using a resist so that a protrusion 20 having a width W is formed as seen in the plan view of FIG. 4b.

In this way, one side of the normal mesa (the opposite of the reverse mesa) having the ridges 21 is completed, and the main surface of the underlying SI-GaAs layer 1 appears in the concave portion to the right of the ridges 21.

Next, an SI-GaAs layer 11 is formed on this layer as _shown in FIG. call)
You can use this method. However, another method of liquid phase epitaxial growth (hereinafter referred to as LPE) can also be used. Then, as shown by the chain line C, diagonal etching is performed again, and the SI-GaAs layer shown as 11a becomes a P+ type shown as 10b.
Remove along with the GaAs layer.

By the way, to create a forward mesa structure by performing the above diagonal etching, use an etching solution such as 8H ₂ O ₂ + 1H ₂ SO ₄ + 1H ₂ O, and align the ridges 21 at the ends of the mesa that are to be created in the <011> axis direction. Alternatively, a reactive etching technique can also be used.

Furthermore, as shown in Figure 4d, an n-type
When a GaAs layer 12 (with an impurity concentration of about 10 ¹⁷ ) is formed, this becomes the active layer 2 in FIG. Note that this n-type GaAs layer is controlled to have a thickness of about 0.2 μm on the left mesa surface 22 of the gate 4, for example.

Next, as shown by the arrow ho in Figure 4e, the molecular beam is incident obliquely to form the MBE of n+ type GaAs.
Do growth. In this way, the slope 23 on the left side of the n-type GaAs layer becomes a shaded area and becomes an n-type layer shown as Z.
The n+ type GaAs is not grown on the surface of the GaAs layer, and as a result, the n+ type GaAs is 13a, 1
It grows separated into two regions as shown in 3b. According to experiments conducted by the inventors, by setting the incident angle θ of the molecular beam to 40°, the length l of the portion 24 to which n+ type GaAs is not deposited in FIG.
It is known that it can be made to 0.5 μm.

By using such a technique, the length of the portion shown as 25 (effective gate length Gl) becomes 1.3 μm, and the end portion 13b of the n+ type GaAs layer, which becomes the high concentration impurity layer directly under the drain electrode, and the active region AR. The distance l between the drain side end portion 26 can be 1.4 μm.

Then, as shown in FIG. 4f, the n+-
An AuGeNi alloy layer is deposited on the GaAs layers 13a and 13b from an oblique direction as shown by the arrows,
The source and drain electrodes 6S and 6D are formed, but due to such oblique vapor deposition, the part indicated by Z becomes a shadow, and no vapor deposition is performed on the part indicated by Z. Also, since the portion Y outside the chain line is an unnecessary portion, it is removed by etching.

On the other hand, at this stage, the protrusions 20, which were half-formed in FIG. 4b, are pulled out from directly under the active layer formed by the n-GaAs layer 12, and are shown as 4a and 4b in FIG. 4g. Because it is created in a structure that is integrated with the strip-shaped part,
The AuGeNi alloy layer 7G must also be formed on the upper surface of the protrusion 20. The band-shaped part 4b seen in Figure 4g remains, but unlike the part 4a that functions as the gate pull-out part, this is unnecessary, so it is shown with a chain line G. The lower portion 4b is removed by etching.

The protrusion thus created functions as the gate bonding area 6 in FIG. 1, and its side view is as shown in FIG. 4h, which corresponds to It is nothing but a cross section.

As mentioned above, if the manufacturing process shown in Figures 4a to 4h is followed, the structure shown in Figures 2 and 3 can be obtained.
JFET is completed.

FIG. 5 is a cross-sectional view showing the structure of a JFET according to a second embodiment of the present invention.
The difference from JFET is that the gate is made of P-type Ga.
The (Al)As layer 4 is placed on a predetermined portion of the SI-GaAs substrate 1.
In the JFET of the second embodiment, which is manufactured by implanting Be ions, the difference in level produced is reduced, and the manufacturing yield is improved accordingly.

(g) Effect of the invention In a JFET having a structure made using the process described in detail above, the
Since it is easy to make the distance L between D and the gate length Gl small, great practical effects can be expected.

[Brief explanation of drawings]

Figure 1 shows a conventional semiconductor device, namely
Cross-sectional diagrams showing the structure of GaAsJFET, Figures 2 and 3
The figures are a side view and a perspective view showing the structure of a GaAs JFET according to the present invention, and Figures 4a to 4h are according to the present invention.
FIG. 5 is a cross-sectional view showing the structure of a JFET that is a modified embodiment of the present invention. In the drawing, 1 is the substrate, 2 is the active layer, 4 is the gate, 5 is the semi-insulating n-type GaAs layer, 6 is the bonding area, 7S and 7D are the source and drain electrodes, respectively, and 7G is the gate electrode. show.

Claims (1)

[Claims] 1. Consisting of a semi-insulating semiconductor substrate 1 and a first conductivity type high impurity concentration semiconductor layer,
a gate 4 having one slope; a semi-insulating semiconductor layer 5 covering a surface of the gate other than the one slope; and a semi-insulating semiconductor layer 5 provided on the surfaces of the one slope, the semiconductor substrate 1, and the semi-insulating semiconductor layer 5. a second conductivity type active layer 2; and second conductivity type high impurity concentration semiconductor layers 6S and 6D immediately below the source 7S and drain 7D electrodes provided on the active layer 2 divided into two by the one slope.
A semiconductor device comprising: 2. Forming a band-shaped gate having one slope on a semi-insulating semiconductor substrate and consisting of a first conductivity type high impurity concentration semiconductor layer, and a semi-insulating semiconductor layer covering the surface other than the one slope of the gate. forming an active layer of a second conductivity type on one slope of the gate, the semiconductor substrate, and the surface of the semi-insulating semiconductor layer; From diagonally above,
A step of forming a highly impurity concentration semiconductor layer of the second conductivity type that will become the source and drain by molecular beam epitaxial growth, and also forming electrodes for the source and drain from diagonally above by metal evaporation. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.