JPS6337254B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronically controlled fuel injection device for an internal combustion engine (hereinafter referred to as engine) that controls the amount of fuel injected into the engine.

[Prior Art] In the prior art, a damper-type intake air amount detection device, for example, is used as a means for detecting the intake state of the engine. However, in this damper-type intake air amount detection device, the damper is deformed by the backfire, resulting in malfunction.Also, since the intake air amount is converted into voltage by a variable resistor linked to the damper, the contact point of the variable resistor is contact failure,
This has the disadvantage that if a normal output voltage cannot be obtained due to wear and tear of the resistor, the engine will not be properly supplied with fuel and the engine will stop.

Conventionally, abnormalities in the main engine sensors and the main fuel control computer are determined by determining whether or not the value of the current flowing through the main fuel control computer and the fuel injection valve is within a preset normal current value range. It is known that when an abnormality is determined, the fuel injection amount is controlled using separately provided backup engine sensors and a backup fuel control computer (for example, US Pat. No. 3,834,361).

[Problem that the invention seeks to solve]

However, with the conventional type mentioned above, high accuracy is required compared to other sensors, and the intake pipe absolute pressure is more likely to cause trouble than other sensors, and if trouble occurs, it is likely to cause fatal injury. The intake condition detection means consisting of a sensor malfunctions,
Even if output data outside the normal range occurs, if the current flowing to the main fuel control computer and fuel injection valve is within the normal current value range based on data from other sensors, it is determined to be normal. There is a problem in that fuel supply that does not correspond to the engine state is performed based on the data of the intake state detection means in which the abnormality has occurred, and the engine may stop.

Further, there is a problem that not only a backup engine sensor is required in addition to the main engine sensors, but also a backup fuel control computer is required in addition to the main fuel control computer, resulting in a significant increase in cost.

Therefore, the present invention makes it possible to reliably detect failure of the intake condition detection means and maintain good engine operation, and also eliminates the need to separately provide a backup engine sensor and backup fuel control computer, resulting in an inexpensive configuration. It is something.

[Means for Solving the Problems] Therefore, as shown in FIG. 1, the present invention comprises: intake state detection means for detecting the intake air amount or intake negative pressure of an internal combustion engine; and rotation detection means for detecting the rotation of the engine. and throttle opening detection means for detecting the opening of a throttle valve of the engine; throttle opening data of the throttle opening detection means, intake state data of the intake state detection means, and rotation data of the rotation detection means. an injection amount calculating means for calculating a required fuel injection amount mainly using as a parameter; an intake state detection abnormality determining means for determining whether the output data from the intake state detecting means is normal; and the intake state detecting abnormality determining means. When it is determined that an abnormality has occurred in the intake state detection means, the operation state detection means for detecting the operating state of the engine based on the output from the throttle opening detection means and the intake state detection means are abnormal. an electronic device for an internal combustion engine, comprising: a microcomputer that includes a fixed output setting means for setting a fuel injection amount according to the operating state of the engine detected by the operating state detecting means when the operating state of the engine occurs; A controlled fuel injection device is provided.

[Effect]

As a result, the intake state detection abnormality determining means directly detects whether the output data from the intake state detecting means is normal or not, and the intake state detecting abnormality determining means detects whether or not the intake state detecting means is abnormal. When it is determined that the detected amount of fuel is being The fixed output setting means sets the fuel injection amount according to the operating state. Moreover, the intake state detection abnormality determination means, the operating state detection means, and the fixed output setting means are included in the microcomputer together with the injection amount calculation means, and a separate back-up computer is not required.

〔Example〕

An embodiment of the present invention shown in the drawings will be described below.

First, the principle of converting the intake pipe negative pressure from the intake air amount and engine speed will be explained with reference to various characteristic diagrams shown in FIGS. 2A and 2B. 2A and 2B show the characteristics of a known electronically controlled fuel injection system using intake negative pressure, and both were experimentally determined.
Figure 2 A shows the intake pipe negative pressure P (absolute pressure) in the electronically controlled fuel injection system due to the intake negative pressure.
and the injection pulse width τ to keep the engine air-fuel ratio constant.
It shows the relationship between the two, and has the width indicated by the diagonal line. This width is given by a correction factor KN based on the engine speed, and the characteristics of KN are as shown in FIG. 2B.

When the characteristics shown in FIG. 2A and B are collectively expressed by an equation, it can be seen that the injection pulse width τ is given as a function of the intake negative pressure P' and the engine speed N as shown below.

τ=f ₁ (P', N)...(1) Here, the intake negative pressure P' is defined as in the following equation.

P′=P ₀ −P (P ₀ : atmospheric pressure) Now, the injection pulse width τ in equation (1) represents the fuel injection amount to keep the engine air-fuel ratio constant, so its value is essentially must be proportional to the intake air amount (intake air amount) per engine revolution, and is expressed by the following equation.

τ∝Q/N ...(2) (Q: Intake air amount (g/sec)) From equations (1) and (2), intake negative pressure P', intake air amount Q, and engine speed N are (3) It is related as in the expression.

Q/N=f ₂ (P', N)...(3) From equation (3), the following equation is obtained.

P'=g ₁ ((Q/N), N)=g ₂ (Q, N)...(4) In other words, the intake negative pressure P can be converted from the intake air amount Q and the engine speed N. I understand.

Next, in FIG. 3, 0 is an engine, and 1 is a known damper type intake air amount detection device, which constitutes an intake state detection means for detecting the intake state of the engine 0. 2 is a known intake air temperature detection device built into the intake air amount detection device 1, and 3 is a throttle switch linked to a throttle valve, which serves as a throttle opening detection means. 5 is an angle detection device using a known electromagnetic pickup that detects the tooth pulse of a ring gear attached to the crankshaft of engine 0 as a rotation angle, and 4 is similarly attached to a point corresponding to the rotation reference position of the ring gear. This is a reference position detection device using an electromagnetic pickup that detects one reference pulse per crankshaft rotation by detecting the position of an iron piece. The reference position detection device 4 and the angle detection device 5 constitute rotation detection means that generates an angle pulse every time the internal combustion engine 0 rotates by a predetermined angle. 6
is a cooling water temperature detection device that detects the cooling water temperature, which indicates the engine temperature. Then, the intake air amount detection device 1,
Each analog signal detected by the intake temperature detection device 2 and the cooling water temperature detection device 6 is converted into a digital signal by an analog-to-digital converter (A-D converter) 200 and input to the main processing circuit 100.
Further, the angle signal detected by the angle detection device 5 is input to the shaping circuit 110, and the reference pulse similarly detected by the reference position detection device 4 is shaped by the timing pulse generation circuit 120.
Using the angle signal outputted from 10, the angle signal is input to a main arithmetic circuit 100 and a rotation speed detection circuit 130, which form arithmetic sections divided into two groups. In addition, the same signal is sent to a fuel injection (hereinafter referred to as EFI) converter 30, which will be described later.
0a, 300b and ignition advance angle (hereinafter referred to as BGI)
It is also used as a trigger signal for the converter 400. The signal from throttle switch 3 is ON when the throttle is fully closed, and OFF for all others.The ON-OFF signal is ON when the throttle is fully open, and OFF for others.
Two types of ON-OFF signals are directly input to the main processing unit 100. A rotation speed detection circuit 130 that calculates the engine rotation speed from the angle pulse from the rotation detection means inputs the period of the output signal of the timing pulse generation circuit 120 as a reciprocal of the rotation speed to the main processing circuit 100 in binary code. For the operation of this rotational speed detection circuit 130, a constant clock signal supplied from a clock signal generation circuit 30 consisting of a known crystal oscillation circuit is used.

Now, the main arithmetic circuit 100 that has received the input signal described above is triggered by the output signal of the timing pulse generation circuit 120 and performs a predetermined arithmetic operation.
The fuel injection pulse data is transferred to the EFI converter 300a,
300b, the ignition advance angle data is transferred to the EIG converter 40.
0 as a binary code. EFI converters 300a and 300b are clock signal generation circuits 3
The main arithmetic circuit 1 is controlled by a constant clock signal from 0.
The injection pulse data from 00 is converted into a time width and applied to the injection valve drive circuits 10a and 10b. Therefore, the injection valve drive circuit 10a controls the fuel injection valves 7b and 7c for the second and third cylinders among the electromagnetic fuel injection valves 7a to 7b installed in the intake pipe of the engine 0, and the injection valve drive circuit 10b controls the fuel injection valves 7b and 7c for the second and third cylinders. , 4-cylinder fuel injection valve 7
a, 7d. The EIG converter 400 converts the ignition advance data from the main calculation circuit 100 into an angle signal 1.
10a and a constant clock signal from the clock signal generation circuit 30, the reference pulses 120a, 1
The angle from 20b is converted and applied to the ignition coil drive circuits 20a and 20b. Thereby, the ignition coil drive circuit 20a is configured to use a double coil 40 that supplies high voltage to the 2nd and 3rd cylinder spark plugs 8b and 8c among the ignition plugs 8a to 8d installed in the engine 0.
The coil drive circuit 20b drives a double coil 40b that supplies high voltage to the ignition plugs 8a and 8d for the first and fourth cylinders.

600 is a timer that is activated by the ignition timing signal from the EIG converter 400 and returns after 300μs, and stops the main processing circuit 100 during operation (referred to as OH in Toshiba's TLCS-12A).
The operation of the main arithmetic circuit 100 is stopped. The reason for this is to prevent the main arithmetic circuit 100 from malfunctioning due to ignition noise occurring during the time the ignition plug is ignited while the timer 600 is operating. Reference numeral 9 denotes a starter switch that provides engine starting information to the main processing circuit 100. Therefore, the main arithmetic circuit 100 controls the EFI (electronically controlled fuel injection system).
Calculation of engine fuel requirement and EIG
It constitutes a calculation unit that commonly executes the state of the ignition advance angle of the engine in the (electronically controlled ignition system) in a time-sharing process.

Based on the basic operating principle and basic configuration described above, the detailed configuration and operation of each part will be explained below. FIG. 4 shows an A-D converter 200 that converts the output signal from the intake air amount detection device 1 from analog to digital.
The detailed circuit configuration is shown below. Since the other analog inputs, intake air temperature and cooling water temperature, are converted from analog to digital in the same manner as the intake air amount, only the analog-to-digital conversion operation of the intake air amount Q is shown in the waveform diagram in Figure 5. This will be explained using the operation waveforms shown below.

First, in FIG. 4, 1a is a potentiometer built into the intake air amount detection device 1, and its terminal electronics V _B , V _C , V _S and the intake air amount Q are related by the following equation.

Q=K/(V _C −V _S )/V _B =K/(U ₁ /U ₂ )
...(5) In equation (5), K is a proportionality constant.

From formula (5), the terminal voltage of potentiometer 1a is
If U ₁ /U ₂ is detected, it can be seen that the intake air amount can be determined by reciprocal calculation within the main calculation circuit 100.

Now, when the constant clock signal shown in FIG. 5a is input to the input terminal 200a, a waveform as shown in FIG. 5b is obtained at the output of the NOR gate 206.
Here, 204 is a binary counter (RCA, CD4040
The 4-frequency divided output _Q2 is added to the data input of flip-flop 205 (RCA, CD4013). Divide-by-four output of binary counter 204
Since Q ₂ is delayed by half a clock in the D flip-flop 205 and then applied to the input of the NOR gate 206, the output of the NOR gate 206 has a repetitive waveform as shown in FIG. 5b. The output of NOR gate 206 is inverted and amplified by transistor 201, and a step voltage is applied to the input of operational amplifier 202 (RCA, CA3130). This operational amplifier 202 constitutes an integrating circuit, and when the inverting input terminal voltage is higher than the non-inverting input terminal voltage, the output voltage of the operational amplifier 202 decreases linearly with a time constant determined by the capacitor 2021 and the resistor 2022, and the inverting Similarly, when the input terminal voltage is lower than the non-inverting input terminal voltage, it increases linearly. Now, the non-inverting input voltage of the operational amplifier 202 is set to approximately V _B /2 by the division between the resistors 2024 and 2025, so when the output voltage of the transistor 201 is at a high level, the output voltage of the operational amplifier 202 is linear. decreases, and increases linearly at low levels. As will be described later, in this circuit, only the increasing side of the output voltage change of the operational amplifier 202 is used for the A-D conversion operation, and it is desirable that the decreasing side be short due to time constraints. Therefore, when the output voltage of the transistor 201 is at a high level, it is necessary to shorten the time constant of the integrating circuit. This switching operation is performed by an analog switch 203 (RCA, CD4066). The voltage waveform shown in FIG.
When added to the control input C of No. 3, the analog switch 203 becomes conductive between the input i and the output O when the control input is at a high level, and is cut off when the control input is at a low level. Therefore, if the resistor 2023 is made sufficiently smaller than the resistor 2022, the transistor 2023
When the output of 1 is at a high level, the time constant of the integrating circuit can be made sufficiently shorter than when it is at a low level.
A triangular wave similar to the sawtooth wave shown in FIG. 5d is obtained.

Next, the voltage is converted into a time width using the triangular wave. At this time, the rise of the triangular wave has some delay with respect to the input waveform of the integrating circuit (Figure 5b), so in order to obtain a time width proportional to the voltage from the above triangular wave, it is necessary to detect the rise of the triangular wave. be. Comparator 212 is used for this purpose and connects the non-inverting input terminal voltage of comparator 212 to resistor 212.
If the voltage is set to a value extremely close to 0 volts by dividing the voltage by 1,2122, and the above triangular wave voltage is applied to the inverting input terminal, the output of the comparator 212 will generate a pulse that detects the rising edge of the triangular wave as shown in Figure 5e. can get. The output of the comparator 212 is added to the reset input of the counter with divider 208 (RCA, CD4017), and since the clock input of the counter 208 receives a sufficiently high frequency clock signal from the input terminal 200b, the comparison After the output of the divider 212 falls and the reset of the divider counter 208 is released, there is a slight time difference between Q ₁ and
Thin pulses appear sequentially on the Q ₂ and Q ₃ outputs. After the third _Q3 output among these is inverted by the inverter 209, the R-S flip-flops 213 and 214 are set. The output of a comparator 210 that compares the potentiometer output voltage V _C and the triangular wave voltage is added to the reset input of the R-S flip-flop 213, and when the triangular wave voltage rises and matches V _C , the comparator 210 is activated. In order to change the output from high level to low level, R-S flip-flop 2
13, the time width T _C shown in FIG. 5g is obtained at its Q output. Similarly, the Q output of the R-S flip-flop 214 has V _S as shown in FIG. 5f.
A pulse width T _S proportional to is obtained. As is clear from the configuration of the integrator circuit, the voltage increase rate of the triangular wave is proportional to the power supply voltage VB, so the time required for the triangular wave to rise to a certain voltage from the rise is inversely proportional to VB. That is, in FIG. 5f and g, there is the following relationship: T _S ∝V _S /VB, T _C ∝V _C /VB (6). From equations (5) and (6), U ₁ /U ₂ = (V _C /V _S ) /VB = V _C /VB-V _S /VB∝T _C -T _S ...(7), and U ₁ /U ₂ is proportional to the difference between T _C and T _S.

To obtain the difference between T _C and T _S , NAND the Q output of R-S flip-flop 213 and the Q output of R-S flip-flop 214.
If the output of the NAND gate 215 is input to the D input of the D flip-flop 216 and simultaneously inverted in synchronization with the clock signal (D flip-flop output), T _C and T _S as shown in FIG. 5h are obtained.
A pulse with a difference of . Furthermore, to convert the pulse width shown in Figure 5h to a binary number,
Only when the output of the D flip-flop is at a high level by the NAND gate 217, the clock signal is output to the binary counter 218 as shown in FIG.
(RCA, CD4040), and the output Q ₁ ~ of the binary counter 218.
Q ₁₂ in memory devices 219a to 219c (RCA company,
CD4035) and is stored in accordance with the timing signal from the counter 208 with a depider, a binary code output proportional to the value of U ₁ /U ₂ can be obtained at the output terminals 220a to 220l.

The intake air temperature and water temperature input to the other A-D converters can also be converted into binary codes using the same circuit operation as above.
If a comparator is connected to compare the triangular wave voltage appearing at point The binary counter and memory provide a binary code output proportional to the input voltage. In this embodiment, the clock frequency input to the input terminal 200a is _C2 and 500
Hz, the clock frequency input to terminal 200b is
_C1 uses 520Kz, both of which are supplied from the clock signal generation circuit 30. Resistor 2022 is 33K
Ω, 2023 is 100Ω, 2024 is 22KΩ, 20
25 is 18KΩ, 2122 is 56KΩ, 2121 is 15
Ω, metal film resistors are used in both cases, and the capacitor 2021 is a 0.068 μF polycarbonate capacitor.

Next, the configurations of the angle detection device 5 and the reference position detection device 4 for detecting the rotation angle of the engine 0 are shown in FIG. In FIG. 6, 51 is a ring gear, 4
1 is an iron piece attached to one point of the ring gear, and its position is set at a reference position of 60 degrees before the top dead center of the first cylinder. The ring gear has 115 teeth, so the angle detection device 5 detects 115 pulses per crankshaft rotation. Also,
The reference position detection device 4 detects once per revolution of the crankshaft, if it is a 4-cycle 4-cylinder engine,
Detects the position 60 degrees before top dead center of the first or fourth cylinder.

The signal detected by the angle detection device 5 is shaped by an angle signal shaping circuit 110. This shaping circuit 11
The configuration of 0 is shown in FIG. The angle signal input to the input terminal 1100 is appropriately clamped by the integration time constant determined by the resistors 1102, 1106 and the capacitor 1104 and the Zener diode 1103, and is input to the inverting input terminal of the comparator 1101 (Motorola, MC3302). . At the same time, the inverting input of the comparator 1101 is biased with the forward voltage of the diode 1105, and the non-inverting input of the comparator is biased to the same value as the inverting input side by dividing the resistors 1107 and 1108. Then, due to the pulsation of the angle signal voltage input from the input terminal 1100, a pulse signal with an inverted input phase is obtained at the output of the comparator 1101. resistance 110
9 is a positive feedback resistor that sharpens the rise and fall of the pulse, and 1110 is a load resistor. Further, an inverter 1111 is connected to match the phase with the input signal.

As mentioned above, the signal detected by the reference position detection device 4 is generated once per crankshaft rotation (360°).
However, in a 4-stroke, 4-cylinder engine, ignition is required once every 180°, so it is necessary to create an apparent reference position signal at a position 180° from the original detection position. There is. This operation is performed by the timing generation circuit 120, whose circuit configuration is shown in FIG. 8, and the operating waveforms of each part are shown in FIG.
As shown in FIG. In FIG. 8, a signal detected by the reference position detection device 4 is input to an input terminal 1200. This signal is shaped by a shaping circuit 125. Since the shaping circuit 125 operates in the same manner as the circuit shown in FIG. 7, the explanation thereof will be omitted. Angle signal shaping circuit 1 is connected to the input terminal 1201.
10 is added to the input terminal 1202, and a clock signal (520 KHz) which is sufficiently faster than the angle signal frequency is input to the input terminal 1202. The angle signal applied to the input terminal 1201 is synchronized with the clock signal by the D flip-flop 1204 and then sent to the D flip-flop 1.
In addition to the clock input of 205, the input terminal 120
A reference signal added to 0 is synchronized to the angle signal. Therefore, as shown in Figure 9 a, b, c, the input terminal 1
The reference signal a input to 200 has a waveform shown in c in synchronization with the angle signal b. The reference signal frequency waveform shown in FIG. 9c is a counter 1209 with a divider.
(RCA company, CD4017) in addition to the reset input,
As shown in FIG. 9d, the _Q1 output produces a thin pulse that appears immediately after the fall of the synchronizing signal c.
This becomes a signal indicating the original reference position.

Next, in order to obtain an apparent reference signal on the opposite side of 180°, the 180° position is determined by counting the tooth pulses of the ring gear from the above-mentioned original reference position. In other words, as mentioned above, the ring gear has 115 teeth, so
The number of teeth corresponding to 180° is 57.5, which is no longer an integer value. This indicates that if the reference position signal shown in FIG. 9d is output at the rising edge of the angle signal b, the apparent reference position signal must be output at the falling edge of the angle signal b. . Therefore, in this embodiment, the inverter 1206, the counters 1207 and 1208 with dehyder, and the NOR gate 121
0 to create the multiplication signal shown in Figure 9e,
The 180° reference position signal is arranged to arrive at the falling edge of the angle signal b. Counter with divider 1207
The reset input of the counter 1208 has an inverted signal of the angle signal FIG.
Since the signal shown in is input as is, the Q ₃ output of the counter 1207 obtains a thin pulse synchronized with the rising edge of the angle signal (FIG. 9b), and the Q ₁ output of the counter 1208 receives a pulse synchronized with the falling edge. is obtained. Furthermore, both are NOR gate 1
210, and the multiplied signal shown in FIG. 9e is obtained at its output.

Next, the multiplier signal e in FIG.
(RCA, CD4040) to count up to the 180° position. The count value corresponding to 180° is 57.5×2=115, but the configuration is such that the binary counter 1213 counts one pulse from the divider equipped counter 1207 immediately after it is reset by the reference signal from the dehyder equipped counter 1209. Therefore, the count value of the binary counter 1213 is 115 + 1 = 116 = 2 ⁶ + 2 ⁵ +
Set it to 2 ⁴ + 2 ² . When the count value of the binary counter reaches “116” after being reset, NAND gate 1
The output of 211 changes from high level to low level.
The waveform is shown in Figure f. NAND gate 1211
The output of the NAND gate 1212 is further connected to the input of the NAND gate 1212 and the recent input of the counter with divider 1214.
When the output of the gate 1211 becomes low level, the clock input to the binary counter 1213 is stopped, and at the same time, the counter with divider 1214 outputs the 180° position signal shown in FIG. 9g to the _Q1 output.

As a result, a 360° periodic pulse shown in FIG. 10a is obtained at the output terminal 1216 of this circuit, and a 360° periodic pulse shown in FIG. 10b with a 180° delay is obtained at the output terminal 1215.

In addition, the input terminal 1203 has an angle signal shaping circuit 1.
10 outputs are connected. The reference signal 120a (FIG. 9a) is a binary counter 1221 (RCA company,
CD4040) and set the output of the NAND gate 1222 to which its Q ₂ , Q ₄ , and Q ₅ outputs are connected to a high level, the output of the inverter 1223 is input with the reference signal 120a as shown in FIG. 10c. At that point, it becomes low level. From this state, the angle signal is input as a clock, and after 26 counts, the outputs Q ₂ , Q ₄ , and Q ₅ of the counter 1221 all become high level, and the output of the NAND gate 1222 becomes low level, so that the inverter 1223 The output changes state to a high level as shown in Figure 10c. The angle from the input of the reference signal 120a to this point is 3.13×26=81.38°. When the NAND gate 1222 becomes low level, the angle signal input to the binary counter 1221 is input to the NAND gate 1222.
Since it is stopped by 20, the binary counter 122
1 maintains the current state and inverter 122
The output of No. 3 maintains a high level until the next reference signal 120a is input. 180° opposite reference signal 1
The delay operation for 20b is also performed by the binary counter 122.
1', NAND gates 1220', 1222', and inverter 123', and the 10th
A delayed waveform shown in d with respect to FIG. b is obtained.

Next, the inverter 1224 and the capacitor 122
A narrow pulse is created at the rising edge of the output signal of the inverter 1223 by the NAND gate 1226 and the output signal of the inverter 1223' is inputted to the R-S flip-flop 1227, whose output 1228 is as shown in FIG. 10e. The EFI reference signal shown (Fig. 3, 120c) is obtained, and similarly, the EFI reference signal shown in Fig.
d) is obtained.

Next, the configuration of the rotation speed detection circuit 130 is shown in FIG.

The distribution circuit 12 is connected to the input terminals 1301 and 1302.
0 output signal is input, NOR gate 1303
and the inverter 1304 in FIGS. 10a and 10b.
An OR signal is obtained. A clock signal of an appropriate frequency from the clock signal generation circuit 30 is input to the clock input of the binary counter 1308.
The outputs Q ₁ to _{Q 12} of the binary counter 1308 are stored in memory devices 1309, 1310, and 1311 (RCA, Inc., respectively).
CD4035) is connected to the D input. Memory device 1
309, 1310, 1311 are inverters 113
The output of 04 is triggered by the 180° signal to store the count value of the binary counter 1308, and then the inverters 1305, 1307 and the capacitor 130
The 180° signal delayed by 6 is sent to counter 1308.
Set. Therefore, output terminals 1312a-l
gives a binary code proportional to the time required to rotate the crankshaft 180°. That is, a binary code proportional to 1/N is obtained at the output terminals 1312a to 1312l, and this is input to the main processing unit 100,
A rotational speed signal N is obtained by reciprocal calculation.

Next, the main processing circuit 100 will be explained. As described above, the main processing circuit 100 converts the intake air amount Q and rotational speed N into a negative pressure signal, converts the reciprocal of U ₁ /U ₂ detected from the intake air amount detection device 1, and performs 1/
In addition to advanced calculation functions such as reciprocal calculation of N, general EFEI and EIG control functions are required, so if it were constructed from individual parts, it would be quite large and the configuration would be complicated. Therefore, in this embodiment, a microcomputer (Toshiba Corporation, TLCS-12A), which executes various calculations in a time-sharing manner using software, is used as the main calculation circuit, thereby realizing miniaturization and simplification of the configuration. Since the configuration and operation of the microcomputer are well known, their explanation will be omitted here, and only the contents of the calculations will be described.

First, the EFI calculation is started by the output signal 120c or 120d of the timing pulse generation circuit 120. At this time, it is first checked whether the intake air amount data Q is correct or not. The check method is to take the maximum value of the intake air amount data under normal engine operating conditions as Q _MBX and the minimum value as Q _{MiN .}
When ≦Q≦Q _MAX , the intake air amount data Q is determined to be normal, and when Q<Q _MiN or Q _MAX <Q, it is determined to be abnormal.
At this time, if it is determined to be normal, the process proceeds to the NORMAL ROUTINE step for performing normal arithmetic operations. The arithmetic operation of the main arithmetic circuit 100 described above in the case of EFI control is shown in the flowchart of FIG.

First, in a first step 100-1, it is determined whether the intake air amount Q is equal to or larger than a preset maximum intake air amount _QMAX , and if the judgment is NO.
NORMAL, which causes normal arithmetic operations to be performed in the case of
Go to ROUTINE100-5, and if YES, the second
Proceed to step 100-2 and set the minimum intake amount in advance.
Compare with Q _MiN . And this second step 100-
2, if the judgment is NO,
Go to NORMAL ROUTINE 100-5, and if YES, proceed to the next third step 100-3. This third step 100-3 is a step for determining the idle state of the engine based on the throttle opening degree, and it is determined whether the idle switch (IDLE SW) of the throttle switches 3 is ON, that is, the throttle valve is fully closed. However, in the case of YES, the process proceeds to step 100-8, where an injection pulse with a time width of Dτ ₁ =2.5 ms is commanded to the EFI pulse width exchangers 300a and 300b, and the fixed advance angle value Q _{1 is}
shall be. On the other hand, in the case of NO in the third step 100-3, the process proceeds to the next fourth step 100-4. This fourth step 100-4 is a step for determining the high load state of the engine based on the throttle opening.
Determine whether the power switch (POWER SW) is ON, that is, the throttle valve is fully open. If the determination is YES, proceed to step 100-7.
Then, the injection pulse with a time of Dτ ₃ = 7.1ms is generated.
A command is given to the EFI pulse width converters 300a and 300b, and a fixed lead angle value _Q3 is set. Further, in the case of NO in this fourth step 100-4, it is determined that the throttle opening is between the IDLE region and the POWER increase region and the engine is in a low load state, and the process proceeds to step 100-6. The injection pulse with a time width of Dτ ₂ =4.5 ms is sent to the pulse width converter 300a
300b and set it to a fixed lead angle value _Q2 .

As mentioned above, when the intake air amount data Q is judged to be abnormal,
The idle state of the engine (the idle switch
ON, power switch OFF), low load state (idle switch OFF, power switch OFF), high load state (idle switch OFF, power switch OFF)
ON) and outputs three types of fixed injection pulse data Dτ regardless of the intake air amount data Q. In this embodiment, the specific values of the fixed injection pulse data Dτ are Dτ ₁ = 2.5 msec equivalent in idle state, Dτ ₂ = 4.5 msec equivalent in steady state, and Dτ ₃ = equivalent in acceleration state.
7.1 msec, θ ₁ = 15℃A, θ ₂ = 20℃A, θ ₃ =
Equivalent to 25℃A.

Furthermore, if the intake air amount data Q is determined to be normal, in NORMAL ROUTINE step 100-5, L-EFI which is a known intake air amount method is used.
Calculate the required fuel amount by performing calculations equivalent to
Data is transferred to EFI pulse width converters 300a and 300b.

The calculation formula is shown below: Injection pulse data
Dτ is Dτ=W・A・S・(Q/N)・(K+D ₁ +D _P )
...(8) In the above equation, Dτ is binary data corresponding to the injection pulse width, W is the water temperature increase, A is the intake temperature correction, and S
is the increase after starting, which is a function of water temperature and time elapsed since engine starting. Q is the intake air amount, N is the engine rotational speed, and K is a constant coefficient that is constantly input and is binary data that determines the basic air-fuel ratio. D ₁ is the idle increase amount given by the throttle switch 3 only when the throttle is fully closed and is 0 otherwise. D _P is the amount given by the throttle switch 3 only when the throttle is fully open, and is the throttle fully open increase amount.
Also, when starting the engine, information is given from the starter switch 9, and fixed injection pulse data (equivalent to 6 msec in the example) is applied regardless of the above calculation.
is output.

As mentioned above, the intake air amount data U ₁ /U ₂ τ1/Q and the rotation speed data input to the main processing circuit 100 are both given in the form of reciprocal numbers of 1/N, so Q in equation (8) /N performs the operation X(1/N)÷(U ₁ /U ₂ ) instead of the operation X(Q÷N).

When the above calculations are completed, the injection pulse data Dτ
is output to the EFI converter 300a or 300b as a parallel binary code, but due to the temporal relationship between the calculation start and the converter trigger, the EFI reference signal 12
The result of the calculation started at 0c is sent to EFI converter 3.
The EFI converter 300b takes charge of the result of the calculation started by the EFI reference signal 120d.

Next, the EIG calculation is started by the outputs 120a and 120b of the timing pulse generation circuit 120, and the following processing is performed. The first function of EIG is
The advance angle characteristics for individual parameters as shown in FIGS. 2a and 2b are combined and controlled so that high pressure is applied to the spark plug at a predetermined ignition timing. Therefore, in this embodiment, the advance angle characteristics shown in FIGS. The angular quantities θ ₁ and θ ₂ are obtained, and the two are added to obtain predetermined ignition angle data. Here, as mentioned above, the reference position for calculating the ignition advance angle is 60 degrees before the top dead center of each cylinder, so for example, in order to ignite at a position with an advance angle of 10 degrees, the position is 60 degrees - 10 degrees = 50 degrees. The advance angle characteristics must be programmed so that the angle data of .

In order to carry out the above processing, first, as for the rotation speed advance characteristic, the rotation speed N is obtained by reciprocal calculation from the output 1/N of the rotation speed detection circuit 130, and the advance angle amount θ ₁ is obtained from the program in the memory area.

Next, the negative pressure advance angle is determined by converting the negative pressure from the intake air amount Q and the rotational speed N, and based on the converted value, the advance angle amount is obtained as follows. The rotational speed correction characteristic shown in FIG. 2B is programmed into the memory, and the rotational speed correction KN is read out from the rotational speed N obtained by the reciprocal calculation. Next, the EFI calculation term (Q/N) is divided by KN. This division means that in the characteristic diagram of the negative pressure and injection pulse width shown in FIG. 2A, the fluctuation width due to rotational speed correction is canceled and normalized to the lowest limit value of the shaded area in FIG. 2A. Here, input this lowest limit p-γ characteristic on the τ side, contrary to Fig. 2A, and p
side is programmed into memory as input, and τ
By inputting the above (Q/N)÷KN instead of , negative pressure p' can be obtained. Further, by inputting the negative pressure p' into the negative pressure advance angle characteristic shown in _FIG .

Next, the rotational speed advance amount θ ₁ and the negative pressure advance amount θ ₂ are added, and θ=60°−(θ ₁ +θ ₂ ) is further calculated.

Finally, set θ to the reference position 60° before top dead center.
The desired ignition timing can be obtained by calculating , but the minimum unit of the angle signal that becomes the clock is 360°/115≒
Since it is 3.13°, it cannot support division units smaller than 3.13°, but special processing has been performed to support finer angles. That is, the following characteristic calculation control is performed.

As an example, FIG. 13 shows a time chart for achieving an ignition timing of 5 degrees before top dead center. 1st
In Figure 3a, the reference signal 120a is at a value of 60 degrees before top dead center. b indicates an angle signal, c indicates ignition timing, and in order to detect 5 degrees before top dead center, it is sufficient to count 60 degrees - 5 degrees = 55 degrees from the reference signal position. As shown in d, when the angle signal of 55°/3.13°=17 pulses is counted, an angle of 0.53° remains as a remainder. Therefore, this remainder angle is approximated by proportional calculation with respect to time. That is, t at e corresponds to an angle of 0.53°, and can be approximated by the formula: t=T×0.53/3.13 (9). However, T is one period including t of the angle signal. However, as is clear from FIG. 13, T is a value that can be detected after the desired ignition timing has passed, and equation (9) is theoretically impossible, so the angle signal period T' one period earlier is substituted. In other words, t=T'×0.53/3.13...(10).

The above theory is based on the assumption that the lead angle amount data output from the arithmetic circuit has infinite resolution.Actually, the lead angle amount data has a finite resolution corresponding to the number of bits, as shown in Figure 13. The remaining angles shown as 0.53° in d have discrete values, and therefore t also has discrete values. The minimum unit of t is determined by how many lower bits of the advance angle amount data correspond to one period T' of the angle signal. For example, if the lower 3 bits correspond to T', since 2 ³ = 8, the minimum unit is 3.13°/8 = 0.39°, and in order to ignite at 5° before top dead center, the advance angle data is , 55/0.39÷141=“10001101”. The above 5 bits "10001" (17) of the above 8 bit binary number are used as main data and are counted as an angle signal in units of 3.13 degrees, and the lower 3
A proportional calculation corresponding to equation (10) is performed using bit “101” (5) as sub data. In this case, 3.13° corresponds to 2 ³ = 8, and 0.53° corresponds to "101" (5), so perform the calculation t = T' x 5/8 to find t, and finish counting the main data. By adding t afterwards, the desired ignition timing can be obtained.

Next, FIG. 14 shows an EFI converter 300a that receives data from the main arithmetic circuit 100.
The circuit configuration is shown in FIG. 15, and the operating waveforms of each part thereof are shown.

In FIG. 14, the input terminal 302 is connected to the output 120c (the first
5a) is input, the counter 313 with a divider generates a narrow pulse shown in FIG. The binary counter 304 counts the constant period clock signal (65KHz) applied from the input terminal 301, and when the number of input pulses reaches "41" after reset, the output of the NAND gate 305 changes from high level to low level.
The output of NAND gate 305 is inverter 306
is inverted by R-S flip-flop 307
Set. Therefore, the output is shown in Figure 15c.
The pulse width τo shown in is obtained. τo is an invalid time that does not contribute to injection specific to the fuel injection valve, and the injection width τ for actually operating the fuel injection valve is given by the sum of the calculated data portion τe and the invalid portion τo. The output of the R-S flip-flop 307 shown in FIG. 15e is input to the NOR gate 309 together with a constant cycle clock frequency, and the waveform shown in FIG.
9 to the binary counter 314. Here, the NOR gate 310 is provided to prevent the binary counter from completing one cycle within one reset period and from outputting the injection pulse again. On the other hand, input terminals 319 and 320 each have a main arithmetic circuit 1.
By adding input/output signals and device select signals from the device control unit (hereinafter referred to as DCU) in 00, the signal at the input terminal 320 is sent to the inverter 3.
21, and the inverted signal and input terminal 319
A latch signal is created by passing it through a NAND gate 322. The calculation data 318 of the main calculation circuit 100 is stored in the latch circuits 316a, 316b, 31
6c (both RCA, CD4042) is input to the input data terminal of the NAND gate 322.
The data is stored by the output signal of and the stored contents are outputted. The latch circuit 315a, 3
The outputs of 16b and 316c are sent to comparators 315a and 31
It is input to the input terminals 5b and 316c. Here, inputs a, b, c, and d of the latch circuit 316a are inputs A ₁ , A ₂ , A ₃ , and A ₄ of the comparator 315a, and inputs e, f, g, and n of the latch circuit 316a are inputs of the comparator 315b.
The inputs i, j, k _, l of the latch circuit 316c are A ₁ , A ₂ , A ₃ , A ₄ of the comparator _316c .
They are connected to A ₃ and A ₄ in this order. The outputs Q ₁ to _{Q 12} of the binary counter 314 are output to the comparator 315.
A, 315b, 315c (RCA, CD4063) are connected to the B inputs of the latch circuits 316a, 316b, 316c, which are connected to the A inputs thereof. This comparator 315a, 31
5b and 315c are A> as shown in FIG.
Each of the three states B, A=B, and A<B has inputs and outputs, and the corresponding inputs and outputs are connected. When the binary counter output and the calculation data input to a to l of each latch circuit are compared, the comparator 31
5c output A>B has high level when A>B, A≦B
A low level signal (Fig. 15e) is obtained. This becomes the injection pulse width τ.

Further, an EFI converter 30 operated by the other output 120d of the timing pulse generation circuit 120
0b has exactly the same configuration and operation, but the position where the injection pulse appears is different from that of the EFI converter 300a.
The only difference is 180°.

Further, since the injection valve drive circuits 10a and 10b are known ones, their explanation will be omitted.

Next, FIG. 16 shows the circuit configuration of the EIG converter 400, and FIG. 18 shows its operating waveforms. In FIG. 16, the input terminals 401, 401' are connected to the outputs 120a, 120 of the timing pulse generation circuit 120.
b. An angle signal and an input signal 40 are input to the input terminal 402.
3, a constant period clock signal C ₁ (520KHz) is input. In addition, latch circuits 416 of 418a to 418h
The main arithmetic circuit 10 is connected to the input terminals of a and 416b.
Among the advance angle amount data determined in 0, main data is input. Input terminals 420, 421, 422
is a signal from the DCU in the main processing circuit 100, input 421 is for main data, input 422 is for sub data, input 420 is inverted by inverter 423, and the inverted signal and input 421 are NANDed by NAND gate 424. This signal is used as a latch signal for main data, and the output of the inverter 423 and input 422 are NANDed by a NAND gate 425, and this signal is used as a latch signal for sub data. The main data is the latch circuit 416a, 41
Input data terminal 41 of 6b (RCA company, CD4042)
8 and the NAND gate 424
The main data is stored by the output latch signal, and the stored contents are output. The outputs of the latch circuits 416a and 416b are connected to the comparators 404a and 404a, respectively.
It is input to the input terminal of 404b. Here, inputs a, b, c, and d of the latch circuit 416a are input to the comparator 40.
A latch circuit 41 is connected to inputs A ₁ , A ₂ , A ₃ , A ₄ of 4a.
Inputs e, f, g, and h of 6b are connected in this order to inputs A ₁ , A ₂ , A ₃ , and A ₄ of comparator 404b, respectively. The main data comparator is a binary counter 40.
5. Consists of comparators 404a and 404b,
By counting the angle signals, the angle θ' (FIG. 18b) corresponding to the main data is obtained. The waveform in FIG. 18a is the output of OR gate 421. The sub-data obtained by the time proportional calculation shown in equation (10) are transmitted to latch circuits 417a, 417b, 41
7c is input to input terminals 419a to 419l. Said
Sub data is stored by the latch signal output from the NAND gate 425, and the stored contents are output. The latch circuits 417a, 417b, 41
The output of 7c is the comparator 415a, 415b, 415
It is input to the input terminal of c. Here latch circuit 4
The inputs a, b, c, d of the latch circuit 417a are inputs A ₁ , A ₂ , A ₃ , A ₄ of the comparator 415a, and the inputs e, f, g, h of the latch circuit 417b are the inputs A 1 , A ₁ , A 4 of the comparator 415b.
A ₂ , A ₃ , A ₄ are connected to the input i of the latch circuit 417c,
j, k, l are inputs A ₁ , A ₂ ,
They are connected to A ₃ and A ₄ in this order. This binary counter 414, comparators 415a, 4
The waveform shown in FIG. 18c is obtained by the sub-data comparator constituted by 15b, 415b, and 415c. Since the angle θ' corresponding to the main data is one set signal of the sub-data comparator, the time from the fall of θ' to the rise of the sub-data comparator output is t. Figure 18b,
From the waveform shown in c, the R-S flip-flop 410
The output shown in FIG. 18d is obtained.

500 is a selection circuit for the 1st and 4th cylinders and the 3rd,
It serves to select the ignition signal for the second cylinder and determine the coil charging time. The circuit diagram is the first
7, input 501 is the output of the angle shaping circuit 110, input 502 is the output _C1 of the clock signal generation circuit 30, input 503 is the output of the EIG converter 400, and 504 is the output 120a of the timing pulse generation circuit 120. each comes in.
Decimal counter with divider 505 (RCA company,
CD4017) converts the output signal of the EIG converter 400 into a thin pulse. When the output signal changes from "1" to "0", a clock signal is input, and when it counts 1, a thin pulse is generated at the "1" output. The "9" output shown in FIG. 18e is connected to the clock enable terminal so that only one pulse is generated at the output after being reset. Binary counter 506 (RCA company,
CD4040) is reset by counter 505 and counts the output signal of angle shaping circuit 110 as a clock. When counting 32, the count is stopped via the NOR gate 507. The output of the count 506 is shown in FIG. 18f. The counter 508 is originally a D flip-flop, and its output terminal is connected to the D input to form a 1/2 frequency divided binary counter. The output waveform is shown in Fig. 18h. FIG. 18g shows the signal of the output 120a of the timing pulse generation circuit 120. Therefore, the output of NOR gate 509 is as shown in FIG.
The output has the waveform shown in FIG. 18k. The waveform in FIG. 18j is the ignition signal for the third and second cylinders, _T1 is the ignition timing, and time _t1 is the coil charging time, which corresponds to 32 teeth of the ring gear. The k waveform in FIG. 18 is the ignition signal for the first and fourth cylinders, _T2 is the ignition timing, and time _t2 is the charging time of the coil, which corresponds to 32 teeth of the ring gear. The waveforms of j and k can be amplified by the coil drive circuits 20b and 20a, and ignition can be performed by the double coils 40b and 40a. Since the coil drive circuits 20a and 20b are known ones, their explanation will be omitted.

Next, the timer 600 will be explained. To explain the circuit diagram with reference to FIG. 19, the input 601 has
The output of the EIG converter 400 is input and reset is applied, and the clock _C3 from the clock signal generation circuit 30 is input to the input 602. When 128 clocks are input, the NOR gate 604 prevents the clock from inputting. The time it takes for output _Q8 to become "1" after reset is approximately 250 μS. By inputting this output to the input terminal operation stop input of the main arithmetic circuit 100, the main arithmetic circuit 100 stops operating for about 250 μS after the ignition signal is output. There is a delay of about 40 μS from the output of the EIG converter 400 until the high voltage is actually generated in the double coils 40a and 40b, and the ignition time is about 100 μS.
By stopping the operation of the engine, it is possible to prevent the entire system from malfunctioning due to ignition noise. Of course timer 600,
EIG converter 400, EFI converter 300a, 3
00b has no meaning unless malfunctions due to ignition noise are prevented.

Next, the double coils 40a and 40b will be explained.

As shown in FIG. 20, the double coil has a secondary winding open at both ends, and each is connected to spark plugs 24a and 24b of cylinders that are out of phase by 360 degrees. Therefore, a four-cylinder engine requires two double coils, and a six-cylinder engine requires three double coils.

As an example, FIG. 21 shows the temporal relationship when the first and fourth cylinders of a four-cylinder engine are driven by double coils.

In FIG. 21, the normal ignition timing for the first cylinder is S _a , the first cylinder is at the end of the compression stroke, and the fourth cylinder is at the end of the exhaust stroke. Sparks fly in the first and fourth cylinders at the same time, but since the pressure inside the cylinder is higher in the first cylinder, the spark voltage is almost concentrated at the spark plug in the first cylinder. Ignition position at the end of the 4th cylinder compression stroke
The same can be said for Sb, and this means that in double-coil ignition, if only top dead center can be detected, stroke discrimination is unnecessary, and the distributor for distributing high voltage to each cylinder can be omitted. Can be done.

Although the above embodiment has been described only for a 4-cylinder 4-cycle engine, the present invention can be applied to a 6- or 3-cylinder engine, in which case the timing pulse generation circuit 120 has 3 types of output for 6 cylinders and 3 types for 8 cylinders. In this case, four types are required, and accordingly, the number of EIG converters is three or eight for six cylinders.
Four cylinders are required.

Furthermore, in this embodiment, the EFI injection signals are set to two groups and the injections are made twice/one cycle, but it is also possible to use only one comparator for EFI and perform simultaneous two injections in all cylinders in one cycle. In addition, in this embodiment, the main calculation circuit 100 starts calculating EIG and EFI by generating two reference position signals using the ring gear.
EIG with reference signal 120a, second reference signal 1
20c is used as an interrupt signal to start calculation of EFI, but when calculations for other functions such as automatic transmission electronic control or anti-skid electronic control are integrated and calculated in the main calculation circuit 100, the interrupt signal is synchronized with each crank angle. It goes without saying that a reference position signal may be generated by a timing pulse generation circuit and this reference signal may be used as an interrupt signal for the main processing circuit 100.

Further, in this embodiment, an intake air amount detection device that detects the intake air amount is used as the intake state detection means,
In addition, as detailed in the text, the arithmetic circuit converts the amount of intake air and rotational speed into a negative pressure signal. It is also possible to determine the negative pressure directly.

〔Effect of the invention〕

As described above, in the present invention, it is possible to directly check for an abnormality in the intake state detection means that detects the intake air amount or intake negative pressure by using the microcomputer that performs the main calculation of the fuel injection amount. If an abnormality is detected in the condition detection means, the microcomputer detects the engine operating condition using the output from the existing throttle opening detection means as a parameter for the main calculation of the fuel injection amount, and It is possible to supply a fuel injection amount commensurate with the state, and therefore, even if the intake state detection means fails, there is no need to newly install a separate backup sensor or backup computer, and with an inexpensive configuration, This has the excellent effect of ensuring that the engine operates well.

[Brief explanation of the drawing]

The attached drawings show an embodiment of the electronic control device for an internal combustion engine according to the present invention, and FIG. 1 is a diagram corresponding to the claims of the present invention, and FIG.
Injection pulse characteristic diagram, Figure 2B is an engine speed-coefficient characteristic diagram showing characteristic selection in Figure 2A, Figure 3 is a configuration diagram showing the overall configuration of the device of the present invention, and Figure 4 is in Figure 3. An electrical wiring diagram showing the detailed configuration of the A-D converter,
Fig. 5 is a signal waveform diagram of each part of the circuit in Fig. 4, Fig. 6 is a detailed configuration diagram showing the rotation angle and reference position detection device in Fig. 3, and Fig. 7 is a detailed diagram of the shaping circuit in Fig. 3. FIG. 8 is an electrical wiring diagram showing the detailed configuration of the timing pulse generation circuit in FIG. 3. FIGS. 9 and 10 are signal waveform diagrams of each part of the circuit in FIG. 8. The figure is an electrical wiring diagram showing the detailed configuration of the rotation speed detection circuit in Figure 3, Figure 12 a, b
is an advance angle characteristic diagram programmed in the main arithmetic circuit in Fig. 3, Fig. 13 is a waveform diagram showing the ignition timing control operation of the main arithmetic circuit in Fig. 3, and Fig. 14 is an EFI diagram in Fig. 3. 15 is a signal waveform diagram of each part of the circuit in FIG. 14, and FIG. 16 is an electrical diagram showing the detailed configuration of the pulse width converter for EIG in FIG. 3. The wiring diagram, Figure 17, is an electrical wiring diagram showing the detailed configuration of the selection circuit in Figure 3.
Figure 8 is a signal waveform diagram of each part of the EIG pulse width converter in Figure 16 and the selection circuit in Figure 17, and Figure 19 is an electrical wiring diagram showing the detailed configuration of the timer in Figure 3.
FIG. 20 is a detailed configuration diagram showing the double coil ignition system in FIG. 3, FIG. 21 is an explanatory diagram of the operation of the double coil in FIG. 20, and FIG. 22 is a flowchart showing the operation of the main arithmetic circuit. 0...Engine, 1...Intake air amount detection device,
3...Throttle switch forming a throttle opening detection device, 4, 5...Reference position detection device and angle detection device forming main parts of a rotation detection device, 7a, 7b,
7c, 7d...Fuel injection valve, 8a, 8b, 8c,
8d...Spark plug, 10a, 10b...Injection valve drive circuit, 20a, 20b...Ignition coil drive circuit, 30...Clock signal generation circuit, 40a, 4
0b...Double coil, 100...Main calculation circuit,
110... Shaping circuit, 120... Timing pulse generation circuit, 200... A-D converter, 300
a, 300b...EFI pulse width converter, 400
...Pulse width converter for EIG, 500...Selection circuit, 600...Timer.

Claims (1)

[Scope of Claims] 1. Intake state detection means for detecting the intake air amount or intake negative pressure of the internal combustion engine; Rotation detection means for detecting the rotation of the engine; and detecting the opening degree of the throttle valve of the engine. Throttle opening detection means, and an injection amount for calculating a required fuel injection amount mainly using throttle opening data from the throttle opening detection means, intake state data from the intake state detection means, and rotation data from the rotation detection means. Calculating means, intake state detection abnormality determining means for determining whether output data from the intake state detecting means is normal, and intake state detecting abnormality determining means detecting whether an abnormality has occurred in the intake state detecting means. an operating state detecting means that detects the operating state of the engine based on the output from the throttle opening detecting means; and if an abnormality occurs in the intake state detecting means, the operating state detecting means detects An electronically controlled fuel injection device for an internal combustion engine, comprising: a microcomputer including a fixed output setting means for setting a fuel injection amount according to an operating state of the engine. 2. The throttle opening detecting means includes a throttle switch that detects the fully closed position and the fully open position of the throttle valve, and the operating state detecting means detects when the throttle switch detects the fully closed position of the throttle valve. When it is determined that the engine is in an idle state and the throttle switch detects the fully open position of the throttle valve, it is determined that the engine is in a high load state, and the throttle switch detects the fully closed position of the throttle valve.
When none of the fully open positions are detected, it is determined that the engine is in a low load state, and the fixed output setting means sets the fuel injection amount in three stages according to the three stages of operating states detected by the operating state detecting means. An electronically controlled fuel injection device for an internal combustion engine as set forth in claim 1.