JPS6336613A - Phase locked loop device - Google Patents

Abstract

PURPOSE:To obtain a frequency holding means suitable for monolithic circuit integration of a PLL by providing a trimming means adjusting the oscillated frequency of a variable frequency oscillator into a prescribed frequency in the missing state of a reference input. CONSTITUTION:A diode D191 compensating input/output nonlinearity and effect of temperature is connected to a VCO 100 whose oscillated frequency is changed in response to an input voltage and a voltage division circuit 200 including a trimming means is connected across the diode. A frequency deviation of the output of the VCO 100 is detected, the output of a trimming control circuit 700 generating a trimming is given to the circuit 200, whose output is given to a constant current circuit 300, and an output current I0 of the circuit 300 is given to an adder 170, where the phase of the reference input and that of the VCO output are compared (500) and the output current of a time/current conversion circuit 400 converting the phase difference into a current proportional thereto and the I0 are added and its resulting added output controls the VCO 100. In detecting the missing of the reference input by a timer 600, the frequency of the VCO is kept by using a signal stored in a ROM of the circuit 700.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase-locked loop W (hereinafter abbreviated as PLL), and particularly to a PLL suitable for communication, timing extraction of digital recording, and the like.

[Conventional technology]

In the conventional PLL, when the input signal is lost, the variable frequency oscillator (v
As a means of maintaining the frequency of CO), for example, JP-A-57
As described in Japanese Patent No. 160244, when an input signal is lost, measures are taken to switch vCO to a sample hold circuit with a large time constant and to switch the input signal to a crystal oscillator signal.

[Problem that the invention seeks to solve]

The above-mentioned prior art frequency holding means when an input signal is lost is a complicated and expensive means, and has problems such as being particularly unsuitable for monolithic integration.

One object of the present invention is to provide a means for frequency retention suitable for monolithic integration of PLLs, another object is to provide a means for eliminating the effects of component variations, and still other objects. The objective is to provide a means for easily converting to any frequency used.

[Means for solving problems]

The above purpose is to linearize the input/output characteristics of the variable frequency oscillator, and to provide a frequency trimming means to constant the gain of the variable frequency oscillator and its control circuit so that a predetermined oscillation frequency is achieved at a predetermined input value. This is achieved by controlling the oscillation frequency to a predetermined value when the input signal is lost. Note that a read-only memory (ROM) is used as a means for inputting the trimming amount, and a timer counter is used to detect loss of an input signal, both of which are integrated into a PLL chip. Further, a logic tester or a calculator is used as a means for detecting frequency deviation and generating a trimming amount.

[Effect]

The above configuration means is suitable for monolithic integration where the oscillation frequency can be maintained at a predetermined center frequency even when there is no input signal by writing trimming values such that the oscillation frequency becomes a predetermined value in the no-signal input state into the ROM. PLL can be realized. In addition, since this trimming adjusts the gain to a constant value even in linear or CO characteristics, it is possible to eliminate the effects of variations in component elements, and it is easy and accurate to reset the VCO bias value according to a predetermined relationship. You can set the desired center frequency.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 13.

FIG. 1 shows a PL including a frequency trimming device according to the present invention.
FIG. 2 is a circuit block diagram showing an example of L. FIG. In FIG. 1, 100 is a variable oscillator (VCO).

191 is a diode, 200 is a voltage divider circuit, 400 is a T/
In the I conversion circuit, 500 is a phase comparator, 600 is a timer (counter), and 700 is a trimming control device.

Note that the same reference numerals indicate the same or corresponding parts throughout the drawings.

Figure 1 (7) VCO100 is a transistor 111°11
2, capacitor (c) 115, resistor 121°122, diode 123, 124. Constant current source (I) 151, 15
It consists of an emitter-coupled multivibrator including 2. A diode 191 is connected in series to the power supply of the VCO 100, and this diode 191 is a diode for compensating for nonlinearity in input/output characteristics and temperature effects due to the diode of the VCO. A voltage dividing circuit 20 including trimming means is connected to both ends of the diode 191 via a terminal 195.
0 is connected to the trimming input terminal 21, and the VCO
A logic tester (trimming control device) 700 that detects a frequency deviation and generates a trimming amount is connected to an output terminal 180 of the device 100 . Output terminal 2 of voltage divider circuit 200
A constant current circuit 300 is connected to 15, and its output current 0 is connected to an input terminal 175 of the VCO 100 via a current addition circuit 170. This constant current circuit 300 includes a differential amplifier 310, a transistor 321 . Setting resistance (Ro) 3
The output current value 0 is set to a value obtained by dividing the voltage at the terminal 215 by the value Ro of the resistor 350. This output current value Io determines the center frequency of the VCO 100.

That is, the oscillation frequency is inversely proportional to the value Ro of the resistor 350.

In addition, the other input of the current addition circuit 170 is a T/I (time/current) conversion circuit 400 that flows a current proportional to the phase difference.
is connected to the input side of the T/I conversion circuit 400, and a phase comparator 500 and a timer (counter) 600 are connected to the input side of the T/I conversion circuit 400.
The phase comparator 500 receives an input signal (reference input) applied to its input terminal 501 and a VC applied to its input terminal 520.
UP and DOWN pulse voltages with widths proportional to the phase difference between the two alternating signals of the feedback signal from the output terminal 180 of the O100 are output to the output terminals 530 and 540. Various types of phase comparator 500 are known depending on the characteristics of the signals to be compared. Timer 600 has clock input terminal 6
10. A well-known counter having a reset input terminal 620 and an output terminal 630. A reset input terminal No. 8 (input A timeout signal is generated at the output terminal 630 when no signal (signal) is received. Here, the count time of the timer 600 is selected to be longer than the maximum continuous no-change time of the input signal.

Note that all components of the trimming control device 700 and the constant current circuit 300 shown in FIG. 1 except the setting resistor 350 are integrated on the same chip, and therefore complete oscillation operation can be achieved simply by adding the resistor 350. Further, the trimming control device (logic tester) 700 is inserted and used only during adjustment, and the input signal and the signal from the output terminal 180 are not applied during this adjustment. Further, feedback from the output terminal 180 to the input terminal 520 is performed when used as a PLL, and the feedback may be performed directly from the terminal 180 to the terminal 520, or indirectly through a gain circuit or a 1/n frequency dividing circuit. is also well known.

Figure 2 shows vCol and O in the PLL configuration of Figure 1.
It is a frequency characteristic diagram of O. In FIG. 2, by changing the voltage dividing point of the voltage dividing circuit 200 including the trimming means of FIG.
The oscillation frequency f of vC○100 is trimmed to a predetermined frequency fs when the values R and o of the zero setting resistor 350 are a predetermined value Rs. Therefore, characteristic B in Fig. 2,
As shown by C, all the characteristics of CO2O3 become quantified and normalized characteristics like characteristic A after trimming. This eliminates the influence of variations in the constituent elements, and for the same reason, the oscillation frequency f can be adjusted by one setting resistor 350.
The center frequency can be set accurately by the value Ro. Note that since the value RO of the setting resistor 350 and the oscillation frequency J of the VCO 1'OO are in an inversely proportional relationship, it is clear and convenient to trim the gains so that they correspond in binary numbers.

FIG. 3 is a circuit diagram showing an embodiment of the phase comparator 500 of FIG. 1. In FIG. 3, the phase comparator 500 includes D-type flip-flops 511 and 512, and an OR gate 5.
This is a well-known circuit consisting of 22 circuits. Also, Figure 4 shows the 3rd
FIG. In FIG. 4, fcn(V
510) is the input signal (signal of input terminal 510), J
osc (V520) is ■C○100 output terminal 18
0 signal (signal of input terminal 510), UP (V53
0) is the UP pulse voltage (output terminal 530 (7) voltage),
DOWN (V540) shows each waveform of the DOWN pass/Lz ffi pressure (voltage at output terminal 54°). Input signal (reference input) fco applied to input terminals 510 and 520 of phase comparator 500 in FIG. 4, VC○ output signal f os
UP and DOWN pulse voltages proportional to the phase difference of c are output from output terminals 530 and 540.

FIG. 5 is a circuit diagram showing an embodiment of the T/I conversion circuit 400 of FIG. 1. In FIG. 5, 440 is a T/V conversion circuit, 441 and 442 are OR gates, 443 is an inverter, 445 is a P ch MOS transistor, and 44
6 is an NchM OS transistor, 447°448 is a resistor, 449 is a capacitor, 450 is a V/I conversion circuit, 451 and 452 are NchMOS transistors, 1153 is a resistor, 455 and 456 are constant current circuits, 45
7,458 is a P Ch MOS transistor.

The T/I conversion circuit 400 in FIG. 5 is a T/I conversion circuit 440.
and a V/I conversion circuit 450, the T/V conversion circuit 4
A phase comparator 500 (
UP and DOWN pulses (FIG. 4) proportional to the phase difference from FIG. 3) are input. The pulse width of these UP and DOWN pulses is the transistor (switch) 445, 446,
It is differentially integrated and converted to voltage v1 in a circuit consisting of resistors 447°448 and capacitors 449, and the conversion gain is ¥cc/2 RC (R and C are resistance and capacitor values)
It is. This voltage vi and the transistor 451°452
, the V/I conversion circuit 450 consisting of a resistor 453, constant current circuits 455, 456, and transistors 457, 458 converts the current into a current Δ1 and outputs it from the output terminal 460, and the output current ΔI = (V+ −Vcc/2)/ R453(
R453 is a resistance value).

In addition, the T/V conversion circuit 440 is a transistor (switch)
UP from input terminals 410, 420 to 445, 446
, DOWN pulse, as well as a timeout signal input from the output terminal 630 of the timer 600 in FIG.
When the timeout occurs, the transistor (switch) 445
, 446 are closed and their output voltage v1 is approximately Vcc/
2, and by using such a timeout control signal as a condition for trimming, it is possible to perform trimming including fluctuations in the T/I power conversion circuit 400.

FIG. 6 is a circuit diagram showing an embodiment of a voltage dividing circuit 200 including a ROM of the trimming means shown in FIG.

In Figure 6, 210 (COM), 21 a (LS
B) ~ 21n (MSB) are trimming input terminals (pads for trimming signal input), 220 is ROM, 22 a
~22n is a ROM transistor, 23a ~23
n is a resistor, 24a to 24n are diodes, 261°26
a to 26n are constant current transistors, 27a to 27n are diodes, 28a to 28n are inverters, and 250 is a D/
251 is a decoder circuit, 252 is a switch circuit, and 253 is a voltage dividing circuit (resistance string). Note that in the current addition circuit 170, 176, 177, and 178 are transistors.

The ROM 220 of the trimming means in FIG. 6 includes transistors 22a to 22n corresponding to the bits that form the ROM, constant current transistors 26a to 26n that flow a minute reverse bias current to the emitter-base junction of each transistor, and level shaping inverters 28a to 22n. 28n, diodes 27a to 27n, 24a to 24n for voltage protection, resistors 23a to 23n for current limiting, and trimming input terminals (pads for trimming signal input) 210.21a to 21n. The reverse bias current flowing through the ROM transistors 22a to 22n is selected to a value such that a reverse voltage is sufficiently established and the junction is not damaged, for example, about several μA to 10 μ8, and the threshold values of the inverters 28a to 28n are set to the above values. It is set to a value lower than the guaranteed value of the junction breakdown voltage, for example, about 1 to 2V. Writing to the ROM 220 is performed using transistors 22a to 22.
This is done by applying a voltage of approximately +15 V, 10 mAmax with the trimming input terminals 21a (LSB) to 21n (MSB) positive to the common base terminal 210 (COM) of the bits to which the voltage is applied. The transistor exhibits an ohmic resistance of about several hundred ohms due to the junction breakdown caused by the above-mentioned injection energy, and the terminal voltage thereof becomes sufficiently lower than the threshold values of the inverters 28a to 28n to indicate that writing has been performed.

The voltage divider circuit 200 is basically a multiplication type D/A conversion circuit 2.
50, it is composed of a voltage dividing circuit (resistance string) 253, a switch circuit 252 for branch point selection, and a decoder circuit 251, and the voltage dividing circuit (resistance string) 253 corresponds to the code inputted from the inverters 28a to 28n. The voltage applied to the terminal 195 is divided and outputted to the output terminal 215. The output voltage of this D/A conversion circuit 250 is
, the output current is converted to 0 by a constant current circuit 300 consisting of transistors 321, 322, and a setting resistor 350, and is converted into an output current of 0 by a current adding circuit 170 of a current mirror consisting of transistors 176, 177, and a diode-connected transistor 175. 400 (Figure 5) output terminal 460
The constant current circuits 151 and 152 are controlled by the input terminal 175 of VCOloo (FIG. 1) via a diode-connected transistor 178 to change the oscillation frequency.

7 and 8 are the trimming control bag [70
FIG. 7 is a block diagram showing one embodiment of ROM 22.
0 (Figure 6) shows a configuration block that can write, pseudo write, and verify, and Figure 8 shows a configuration block of a frequency measurement circuit prior to writing.6 In Figures 7 and 8, 750 is a logic tester ( 751.752 in Fig. 7 is an inverter (driver gate), 760 is a pulse amplifier, 761, 762 are its transistors, 765, 766.767 is a relay, 770 is a write probe (pin card pin), 710 in Figure 8
is an input terminal from the output terminal 180 of vCO, 720 is an AND gate, and 730 is a binary counter.

There are three circuits between the logic tester 750 and the write probe in FIG. Route to test Levelle.

Two are pseudo write routes that can temporarily lower the potential of the sleeping pad to a low level via the inverter 752 and relay 767, and the third is the inverter 752. pulse amplifier 760,
The write route circuit is through the relay 766, and the output of the write pulse amplifier 760 is 15V + 10mA,
Writing is possible in about 1 ms. The frequency measurement circuit used before writing in Figure 8 is the same logic tester 7 as in Figure 7.
50 as well as an AND gate 720 and a counter 730, and the input terminal 710 of the gate 720 has vCOloo
The frequency signal of the output terminal 180 of is inputted. Therefore, by setting a constant gate time from the logic tester 750, counting the pulses during that time using the counter 730, and reading the counted value using the logic tester 750, the VCO1
00 frequency can be measured.

FIG. 9 is a flow diagram showing one embodiment of the trimming means of FIG. 1 (FIGS. 6, 7, and 8).

1 (FIGS. 6 to 8) and the trimming operation will be explained in more detail with reference to FIG. 9. First, in step S1, a tip to be trimmed is probed with a bin (probe) 770 (probe set). Next, in step S2, the power supply relay is turned on to supply power to the chip, and in switch S3, the voltage of the trimming pads 21a to 21n is read out by the logic tester 750 via the probe 770, and all bits are "H".
” state, and if even 1 bit is
If there is a bit in the IL''' state, the ROM 220 is initially defective, so reset it to another chip.
If the state is H''', an intermediate value (N=100.
...0), set the deviation Δf=O, and set v in step S5.
Measure the oscillation frequency j of COloo, and the deviation ΔJ from the center frequency is the trimming accuracy (±1/2LSB of N bits)
If the deviation Δf is large, Δf is added to N in step S5 and the determination is repeated. At this time, the voltage dividing circuit 200 (D/A conversion circuit 25
If the linearity of 0) is good, it will converge in one iteration, but
Even if the linearity is not good, the deviation Δj decreases rapidly, so it converges after 2 or 3 repetitions, and the measurement is completed in a short time. When the deviation Δf falls within the allowable value (trimming accuracy), the power to the chip is turned off in step S7, and in step S8, a roughening pulse for the junction is applied in accordance with the converged set value N to perform trimming. Next, in step S9, the power of the chip is turned on, and in step S10, the zapped values are read and matched, and if they do not match, it is assumed that there is some unwritten data, and the zapping is performed again.
If it is M, trimming of that chip is completed. The trimming means according to the above procedure is more reliable because it includes a confirmation process as well as a trimming element that is sure to operate, and it does not take much time for trimming, making it practical.
Even with bit precision, it takes about 1 second.

Next, Figure 10 shows the variable oscillator (VCO) 100 in Figure 1.
FIG. 3 is a circuit diagram showing another embodiment of the bias setting circuit. In FIG. 10, 113,1 of VCO 100
14 is a transistor, 116° 117 is a constant current source, 15
3,154 is a transistor, 161 to 164 are resistors, 1
75, 175' are the control input terminals from the transistor 178 of the current addition circuit 70 (Fig. 6), 190 is the bias setting circuit (bias current source), 191, 192 are the transistors, 193 is the resistor, and 200 is the variable It is resistance. The frequency of vCOloo in FIG. 10 can be adjusted by changing the current value of the transistor 192 by changing the variable resistor 200 of the bias setting circuit 190. Note that this type of VCO and its bias setting circuit can be modified in various ways as necessary.

Figure 11 shows the ROM of the trimming means in Figure 1 (Figure 6).
FIG. 2 is a circuit diagram showing another embodiment of a voltage dividing circuit 200 including the following. In FIG. 11, 291 (16R) to 298 (
16R) is a resistance. The voltage dividing circuit 200 in FIG.
This example shows a variable range of ±25% of bits, and weight resistors 291 (16R) to 298
Since (16R) is used, it has the advantage of having fewer circuit components and can be applied to voltage division and variable resistance, but on the other hand, the resistance after roughening needs to be sufficiently small compared to the unit resistance R. Furthermore, since the roughening pressure must be applied differentially, roughening becomes more difficult than in FIG. 6. Note that the voltage divider circuit and variable resistor for this type of trimming can also be modified as necessary. In addition, on-chip trimming elements such as polysilicon fuses and aluminum wiring can be laser cut, but laser cutting cannot be performed with a normal electrical tester1.

Next, FIG. 12 is a circuit block diagram showing another embodiment of a PLL including a frequency trimming device according to the present invention.

In FIG. 12, 260 is a D/A conversion circuit, 650 is a counter (timer), 660 is a switch, and 680 is a U/A conversion circuit.
D counter 800 is a comparator.

VC in P and LL in Figure 12 also under the input signal loss condition.
ROM220 is a means for trimming the center frequency of O100.
The trimming is performed by the D/A conversion circuit (1) 250 as in Fig. 1, but in the PLL shown in Fig. 1, when the input signal is lost, V C0100 always returns to a constant center frequency and oscillates. If there is a difference between the input frequency and the center frequency, it will cause disturbance during switching, so the first
In the PLL shown in Fig. 2, as a means to further improve this point, a counter (timer) (2) 650 at the time of input signal recovery is used.
and comparator 800. D/A conversion circuit (2) 260
is provided, and the D/A conversion circuit 26o is provided with a D/A converter circuit 26o for fine adjustment.
/A conversion circuit, and the D/A conversion circuit 250, for example, 1
After adjusting to a range of 1,000 ppm to several 11,000 ppm, the amount is further adjusted to a range of several ppm to several 10 ppm.

The output of the D/A conversion circuit 260 in FIG. T/V controlled by U/D counter 680
The output of the conversion circuit 440 is precisely tracked. If a loss of input signal occurs from this state, the counter (1)
After the time counted by 600, the T/V conversion circuit 440 is reset, and at the same time, the switch 660 is switched via the counter (2) 650, and the input of the VCO 100 is connected to the D/A conversion circuit 260 which is in the hold state. .

The oscillation frequency of the VCO 100 is held at the value before the loss of the input signal. When the primary input signal is restored, the reset of the T/V conversion circuit 440 is first released, and the T/V conversion circuit 440 performs phase comparison in the normal operation mode. Then, the input of the V/I conversion circuit 450 is switched to the T/V conversion circuit 440 side by the counter 650, and a closed loop is formed again.

FIG. 13 is a side view of operating waveforms in the PLL configuration of FIG. 12. In FIG. 13, the input signal vI! of the above operating state is shown. io, counter (1) 600, counter (2)
650, T/I conversion circuit 450 output, and VC○100 output waveforms are shown. As shown in FIG. 13, when held by the counter 650, the output f180 of the VCO 100 becomes completely bumpless, and disturbance can be minimized even during resynchronization (return).

〔Effect of the invention〕

According to the present invention, vCO
can be automatically trimmed to maintain good linearity and a constant gain, (1) the effects of component variation can be removed, improving yield, and (2) the gain accuracy is high, allowing users to adjust the operating frequency without making adjustments. (3) It can be used at any frequency over a wide range by simply changing one frequency setting resistor, improving economic efficiency; and (4) A predetermined center frequency can be secured even when the input signal is lost, making it easier for the system to Disturbances are reduced and (
5) Since it always starts from the center frequency, the system can be pulled into the system quickly, for example, within several tens of clocks, and (6
) Trimming (termination) is efficient because it confirms the soundness of the main parts of the PLL, and can also serve as efficient testing of the PLL.

(7) Suitable for integration, trimming can be made more efficient, and therefore a PLL with good performance can be provided at low cost.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram showing an embodiment of the PLL according to the present invention, Fig. 2 is a characteristic diagram of Fig. @1, Fig. 3 is a circuit diagram of the phase comparator shown in Fig. 1, and Fig. 4 is a f53 diagram. 5 is a circuit diagram of the T/I conversion circuit of FIG. 1, and FIG. 6 is a circuit diagram of the T/I conversion circuit of FIG.
A circuit diagram of a voltage divider circuit including the trimming means shown in FIG. 7,
8 is a block diagram of the trimming control device of FIG. 1, FIG. 9 is a flow diagram of the trimming means of FIG. 1, FIG. 10 is another circuit diagram of the VCO of FIG. FIG. 12 is a circuit block diagram showing another embodiment of the PLL according to the present invention.
is an operating waveform diagram of FIG. 12. 100... Variable oscillator (VCO), 191... Diode, 200... I. Voltage dividing circuit including rimming means,
220 ・=ROM, 300−・・constant current circuit, 40
0 ・=T/I conversion circuit, 500 ・・phase comparator, 60
0...Timer (counter), 700...1-rimming control device, 800...Comparator.

Claims (1)

[Claims] 1. A variable frequency oscillator whose oscillation frequency changes according to input voltage or current, and a phase comparator that receives the output of the variable frequency oscillator and a reference input and generates an output according to the phase difference between them. and a converter that converts the output of the phase comparator into a DC signal and inputs the DC signal to the variable frequency oscillator. 1. A phase synchronization device comprising: trimming means including storage means for adjusting the phase synchronization device. 2. The phase synchronization device according to claim 1, further comprising a timer for detecting the disappearance state of the reference input. 3. The phase synchronization device according to claim 1, wherein the storage means is a ROM.