JPS6336581B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel tuned circuit using switched capacitors.

Description of conventional technology: This is the original method for configuring a filter using a switch capacitor circuit.
There is a method of realizing the equivalent inductor L of the LC configuration filter using a switched capacitor circuit including an operational amplifier.

In this case, the output level of the operational amplifier is often higher than the input level, and when such an equivalent inductance is used, the distortion characteristics of the filter deteriorate significantly, resulting in a narrow dynamic range of the filter. There was a problem.

Purpose of the invention: The present invention realizes the parallel tuning circuits of LC configuration filters together in a switch capacitor circuit, and lowers the output terminal level of the operational amplifier in the switch capacitor circuit, thereby increasing the dynamic range of the switch capacitor circuit. The aim is to make it as wide as possible.

In the configuration of the present invention, a switched capacitor integrator consisting of an operational amplifier having a switched capacitor capacitance C ₀ at the input and an integral capacitance Ca in the feedback circuit is connected in cascade with a 1 sample time delay circuit having a switched capacitor configuration, The configuration is such that a signal is fed back from the output end of the switched capacitor integrator and the output end of the delay circuit to the input end via the switched capacitor circuit, and the integral coefficient C ₀ /Ca is C ₀ /Ca < 4.
It is characterized by having the following relationship.

Description of structure and operation of the invention: The details of the invention will be described below with reference to the drawings.

FIG. 1 is an example of a conventional inductor circuit having a switched capacitor configuration. The principle diagram is shown in Fig. 2. In Figure 2, switches S ₁ , S ₁₁ , S ₂ , S ₂₁ , S ₃ ,
S ₃₁ is T/ with the signal sampling period being Tsec.
Switched every 2 seconds. In FIG. 1, each switch is switched in the order of switch numbers 1→2→3→4→1. In Figure 2, the input voltage is V(Z) (Z=e ^j2 〓 ^fT )
As, the terminal BB′ when the switch falls to the left,
The voltages at the terminals of CC′ and DD′ are V ₀ (Z), V ₁ (Z),
When V ₂ (Z) is set, the current ΔQ, which is the amount of change in the charge flowing to the input terminal AA', is given by the following equation.

ΔQ(Z) = V(Z) ₂ 〓 ⁱ⁼⁰ Ci(1-Vi(Z)/V(Z)) (1) By the way, assuming S=j2πf, the circuit in Figure 2 equivalently operates as an inductor L. ^{In order to _ _} ) ² /1−Z ^-1 (2) must hold.

In order for the circuit in Fig. 2 to equivalently operate as an inductor L, by comparing equations (1) and (2), Ci(1-Vi(Z)/V(Z)) = T ² /4L It is necessary to determine the transfer function Vi(Z)/V(Z) so that (1+Z ⁻¹ ) ² /1−Z ⁻¹ (3) holds. There are various T ₁ and T ₂ that satisfy equation (3), one of which is the circuit shown in FIG. 1, where the following equation holds true.

ΔQ(Z)/V(Z)=C ₀ +C ₁ +C ₀ C ₀ /Ca Z ^-1 /1-Z
^-1 +C ₁ C ₀ /Ca Z ^-2 /1-Z ^-1 (4) For equations (3) and (4) to be equal regardless of Z
C ₀ , C ₁ , and Ca must have the following values.

C ₀ = 3/16 T ² /L, C ₁ = T ² /16L, Ca = 3/64 T ²
/L(5) At this time, Vi(Z)/V(Z)=-C ₀ /Ca Z ^-1 /1-Z ^-1 =-4Z ^-
1 /1−Z ^-1 (6), and the switch capacitor integral coefficient C ₀ /Ca
becomes 4. A large integral coefficient means that the amplitude of the output voltage Vi(Z) becomes large. Therefore, considering the distortion characteristics of the operational amplifier,
This integral coefficient should be as small as possible. 1st
Circuits different from diagram circuits e.g. literature ELECTRONICS
LETTERS lst February1979Vol.15No.3pp.87~
88“Switched Capacitor Circuits Bilinearly
Equivalent to Floating Inductor or FDNR”
In the circuits shown in Figures 3a and 3b, the integral coefficient becomes even larger. At present, the integral coefficient 4 of the circuit shown in FIG. 1 is the smallest.

Next, we will explain how to use the inductance of this switched capacitor configuration to configure a parallel resonant circuit with the capacitor Cβ.

Figure 3 is an explanatory diagram, and Figure 3 1 is the original
This is a parallel resonant circuit having an L ₁ Cβ configuration, and FIG. 32 shows this L ₁ realized by the inductance L ₁ of the switched capacitor configuration shown in FIG. 1. and the inductance L ₁ of the switch capacitor configuration
Since there are the above-mentioned problems, the present invention shown in FIG. 3 solves these problems.

That is, according to the present invention, N is realized by combining the parallel tuning circuit of Cβ and _L1 with the switch capacitor circuit shown in FIG. 1, and is obtained by finding each element as follows. It is. The relationship between the charge q(t) that has passed through the parallel tuned circuit shown in FIG. 3 up to time t and the terminal voltage V(t) of the parallel tuned circuit is given by the following equation.

q(t)=CβV(t)+1/L ₁ 〓V(t)dt (7) Qs(S)=(Cβ+1/S ² L ₁ )Vs(S) (8) Qs and Vs are each on the S plane are the charge and terminal voltage of the parallel tuned circuit. Furthermore, when considering on the Z plane, the following equation holds true.

Q(Z)={Cβ+T ² /4L ₁ (1+Z ^-1 /1-Z ^-1 ) ² }V(Z
)(9) The amount of charge ΔQ(Z) passing through the parallel tuned circuit at a certain time t=t _o is ΔQ(Z)=(1-Z ^-1 )Q(Z)=V(Z){Cβ(1- Z ^-1 ) + T
² /4L ₁ (1 + Z ^-1 ) ² /1 - Z ^-1 }(10). Here, when formula (10) is transformed by setting T ² /4L ₁ =Cx, the following formula holds true.

ΔQ(Z)=V(Z) {Cβ+Cx+(3Cx−Cβ)Z ^-1 /1−Z ^-1
+(Cβ+Cx)Z ^-2 /1-Z ^-1 }(11) For equation (4) and equation (11) to be equal regardless of Z Calculate C ₀ , C ₁ , Ca and integral coefficient C ₀ /Ca from equation (12).

C ₀ /Ca = 4Cx / Cx + Cβ (13) C ₀ = (3Cx - Cβ) (Cx + Cβ) / 4Cx (14) C ₁ = (Cx + C) ² /4Cx (15) Ca = (Cx + Cβ) ² (3Cx - Cβ) /16Cx ² (16) From equation (13), the following equation holds true in the range of 3Cx−Cβ>0.

C ₀ /Ca<4 For example, when Cx = 2730pF, Cβ = 3780pF, C ₀ /
Ca≒1.68, and the output voltage level of the operational amplifier is as follows:
This is approximately 1/2.4 times as large as when realized as a combination of the inductor and capacitor Cβ shown in the figure.

If Ca, C ₀ becomes too negative or too small, such as 3Cx<Cβ or 3Cx≒Cβ, use the circuit shown in Figure 4 to leave a part of Cβ and include it in the inductor of the switch capacitor configuration. Needless to say, it's a good thing.

As described above, in accordance with the present invention, _the circuit of _{FIG .}
It becomes possible to realize a Cβ parallel resonant circuit.

Next, the switch capacitor configuration according to the present invention will be described.
An example will be described in which a low-pass filter having an attenuation pole at a finite frequency is realized using an LC parallel resonant circuit.

FIG. 4 shows an equivalent circuit using R, L, and C elements, and FIG. 5 shows a low-pass filter realized using a corresponding switched capacitor. Resistors R ₁ and R ₂ in FIG. 4 are realized by capacitor C ₁ , switches S ₁ , S ₂ and C ₂ , S ₃ , S ₄ respectively,
A parallel resonant circuit including an inductance L ₁ and a capacitor Cβ is realized by a circuit 21. That is, the circuit 21 is a parallel resonant circuit having a switched capacitor configuration according to the present invention, and in the circuit of FIG. 1, C ₀ /
It has a relationship of Ca<4.

In this case, by using the parallel tuning circuit 21 having a switched capacitor configuration according to the present invention, the output level of the operational amplifier can be lowered, and a switched capacitor filter with a wide dynamic range can be obtained. . Also, 3Cx>
Cβ has the advantage that the number of capacitors can be reduced and is economical.

[Brief explanation of the drawing]

Fig. 1 shows the inductance of the switched capacitor configuration, Fig. 2 shows the principle of operation of Fig. 1, Fig. 3 shows an explanation of the parallel resonant circuit according to the present invention, and Fig. 4 shows the low-pass waveform with a finite attenuation pole. The circuit diagram of FIG. 5 shows an embodiment in which the circuit shown in FIG. 4 is realized using a parallel resonant circuit using a switched capacitor filter of the present invention. In the figure, Cβ is the capacitor that forms the parallel resonant circuit, and _L1 is the inductance caused by the switch capacitor in Figure 1.

Claims (1)

[Claims] 1 A switched capacitor integrator consisting of an operational amplifier having a switched capacitor capacitance C ₀ at the input and an integral capacitance Ca in the feedback circuit and a 1 sample time delay circuit having a switched capacitor configuration are connected in cascade, and the switched capacitor integrator It has a configuration in which a signal is fed back from the output end of the delay circuit and the output end of the delay circuit to the input end via a switched capacitor circuit, and is characterized in that the integral coefficient C ₀ /Ca has a function of C ₀ /Ca < 4. Switch capacitor parallel tuned circuit.