JPS6336163A - Ic testing device - Google Patents

Abstract

PURPOSE:To put plural ALPGs in parallel operation and to generate a test pattern at a high speed by developing a loop partially in a computer and assigning a program to respective algorithmic pattern generators ALPG. CONSTITUTION:The computer 1 analyzes the structure of the test pattern program for the pattern generators prior to test execution, and converts and generates test programs for the ALPGs (f) and (g), thereby transferring them to the ALPGs by using a data bus 22. A clock frequency dividing and distribution signal generator 21, on the other hand, generates an ALPG operation clock 23 and distribution signals 24-1 and 24-2 and pattern data is applied to a memory to be tested from a pattern generator 27. Then, a fail memory compares the output of the memory to be tested with an expected value on the basis of a decision strobe signal supplied from the timing generator 3 to a comparator, stores the obtained GO/NG decision result, and transfers it to the computer after the test execution, thereby performing defect analyzing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ICC testing device, and particularly to an IC testing device suitable for testing high-speed memories.

[Conventional technology]

The conventional device, as described in JP-A-54-12657, is equipped with N pattern generators and is arranged in a groove so that their outputs can be taken out sequentially. The IC test device was designed to generate patterns at a speed N times faster than the previous one. At this time, if the @fC under test is a logic IC that is tested using a test pattern called a random pattern without algorithmic properties, each pattern generator usually has a memory that stores the test pattern itself, and a memory that stores the test pattern itself. It is constituted by a relatively simple control logic circuit for reading, and it is thought that speeding up the operation by parallel reading as shown in the known example can be easily realized.

However, when the IC under test is a memory, a microprogram type algorithmic pattern generator (AL, PG) with arithmetic functions is used as a pattern generator.
However, in order to operate N units in parallel, it is necessary to use dummy cycles due to the fact that completely independent parallel operations such as array processors that perform vector operations are impossible, and the special nature of the test pattern. Because this is not allowed, it cannot be achieved simply by connecting N identical ALPGs; parallel programming technology is indispensable for such a hardware configuration and conventional computer technology. This known example did not take this point into consideration.

Problems that invention C attempts to solve] FIG. 3 shows a schematic configuration of a conventional memory IC testing device.

Among them, the timing generator 3 generates the late clock signal that determines the test cycle and the memory under test.
At what temporal position within Nykul? Generates a phase signal etc. that determines whether to give a k signal waveform. on the other hand,
The pattern generator 2 receives the late clock signal 4 from the timing generator 3, and in synchronization with this, executes the test program in the pattern generator for each test cycle,
various tests) generate patterns. This test program is generally developed and depacked on the computer/machine 1 of the test system, and then sent from the computer 1 to the pattern generator 2 for execution.

The pattern gator 5 from the pattern generator 2 is an address,
It consists of data to be applied to the memory under test, such as write data and write/read control data, and an expected value 6 to be compared with bladder ejection data.

In the fail memory, the obtained GO
/NG determination result is stored, and after the test is executed, it is transferred to a computer for failure analysis work.

FIG. 4 shows a schematic internal configuration of the pattern generator 2 shown in FIG. As shown in the figure, the sequence control unit is of a microprogram type, and includes an instruction memory 9 for storing the microprogram, a program counter 10 for determining the read address 14, a branch destination address generated during program execution, and a computer. It is comprised of a multiplexer f11 that switches between the program execution start address and the like specified from 1, and an instruction resolver that decodes the program contents, such as generating a load signal that takes in a new address into the program counter at the time of branching.

The arithmetic processing unit 8 performs arithmetic operations such as addition and subtraction according to the instruction data 15 from the instruction memo 99 of the sequence control unit 7.
It performs logical operations such as /1 inversion and bit shift, and outputs algorithmic pattern 5.

In this way, in ALPG, in order to realize movements that include branching operations such as loops and repeats according to the program itself, in terms of hardware, it has a feedback loop such as the branch destination address 13 and the load signal to the program kakunta. This makes it difficult to increase speed. Therefore, as a method for increasing speed by parallel execution of multiple low-speed memories storing test patterns, as described in the known example, multiple pattern generators 2 (ALPG) shown in FIG. 3 are used. A method is proposed in which multiple programs are executed in parallel. However, it is impossible to use the test program (microprogram) 12 (Fig. . This will be explained below using a memory test pattern generation program called gearropping shown in FIGS. 5 and 6.

FIG. 5 shows, together with a flowchart, the contents of a microprogram for generating a gearropping pattern when the memory capacity under test is 32 pints.

All cells of the memory under test are cleared using a loop L1 of 612 repetitions and 32 times.

(S; One of the cleared memory cells is set as a test cell, and data 1 is stored at the memory address (A=b address).
Write 1″.

(); As a disturbance cell, read and check the data at the address (A=A+j@ground) around the test cell.

(2): Read the test cell address (A=, address) and check the influence of accessing the disturbed cell.

■; After reading and inspecting the disturbance cell address (A=A+7) again, the remaining 6 cells excluding the test cell
It is determined whether the access to all 1 pits is completed as disturbed cells, and if it is not completed, loop L2 returns to processing step (2) and steps (2)-(2)-(2) are repeated.

■; After reading all the remaining cells as disturbance cells for one test cell, write data 1'a''' to the test cell address and clear it. Then, use all the cells as test cells and perform the above read test. If it is not finished, add 1 (===+i)t to the current test cell address (A=address A).
As loop L3, return to the processing step (return to K). After the inspection of all test cells is completed by executing the processing of ■ to ■,
The gear roping pattern program shown in FIG. 5 is completed and comes to an end. However, to be more precise, this is called a back pattern inspection, and the gear roping pattern is completed by executing steps 1 to 2 with the data M''8.'' and 1'' reversed, but this is omitted here.

In this way, a long test pattern called n-type can also be
Utilizing the regularity of the occurrence pattern, it can be expressed with just a few lines of program description, having a loop structure as shown in Figure 5.

Figure 6 schematically shows the flowchart in Figure 5, with two ALPGs ((
This figure shows possible operations that can be executed in parallel by alternately assigning tO) and tO)). As a result, the three loops L1. Each of L2 and L3 is responsible for the step that becomes the starting point for loop return.

ALPG and the ALP responsible for the loop return destination step
It can be seen that when executing the program shown in this figure, it is impossible to increase the speed by alternating operation using two ALPGs.

That is, in the loop Li in FIG. 6, the same steps are repeated, and ALPG ((a) is an independent operation,
It is impossible to execute PG(a) and (II:l) alternately.

Loop L2 is one repetition execution including return from step ■ to loop ■, and in the processing of ■-■-■, each (a)
=((2)=(A) is executed alternately in sequence, but when returning to ■-〇, it requires two consecutive operations of (A)-(A) and the same -ALI'G, making parallel execution impossible. In addition, loop L3 is exactly the same, and when the loop returns, ■
It can be seen that in -〇, ALPG with 14 points attached cannot be shared alternately with 10) - flight).

On the other hand, in each step of the program shown in FIG. 6, address calculations as shown in FIG. 5 are performed. Therefore, as mentioned above, in order for two ALPGs to execute programs alternately, it is necessary for each ALPG to perform calculations after knowing the calculation results of the other ALPGs.
The system did not take this point into consideration, and parallel processing of address operations was not possible.

As mentioned above, test programs previously created for IC test equipment configured with one ALPo cannot be applied to IC test equipment configured with N ALPGs in parallel for the purpose of speeding up. It became essential to take some new measures.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art as described above, and to provide an IC testing device that can operate a plurality of ALPGs in parallel and generate test patterns at high speed.

[Means for solving problems]

Conventionally, the test program (micro program) that was created for one ALPG IC testing device was converted into N pieces of A
In order to enable sequential and alternating execution in the LPG, the loop is partially expanded in advance in the computer so as to eliminate inconsistencies in the sequential nature that occur in the loop, as described in FIG. Then, in addition to extracting the processing steps that each of N A and LPG should be responsible for from the developed program, we also extract the processing steps that each of N A and LPG should be responsible for. Create a program for The above problem can be solved by converting the program in this way and transferring it from the computer to the instruction memory 9 of each ALPG before test execution. Figures 1 and 2
The figure shows an example in which the program in FIG. 6 is expanded in a loop so that it can be executed in parallel by two ALPGs, and a program that can be executed by each of the two ALPGs is created. The first point of the present invention is shown in FIGS. 1 and 2.
As shown in the figure, each ALPQ program is developed in advance using a calculation means that is a component of the invention so that the number of steps in the loop is an integral multiple of the number of parallel ALPGs, and the speed is increased. The objective is to enable parallel execution of i1.

- On the other hand, by expanding in this way and assigning programs to each Al and PG, for each Al and PG, only the programs assigned are executed at intervals equal to the number of ALPGs. Therefore, it is necessary to give the processing contents of other ALPGs as an accumulated instruction.

This will be explained with reference to FIG. The operational expression for the internal structure of the ALPG mentioned in the explanation of Fig. 4 is as shown in Fig. 9.
is expressed in Here, the subscript T indicates a certain program step, ST is the AI at a certain program step,
The internal state of PG is i, OT is its output, fT is internal register, etc. It takes a number of steps to update the contents.F? Command, Z
r is an output command that processes output data within the same step, such as addition/subtraction or logical inversion.

That is, the output Ot is obtained by applying the output command y'r to the internal state ST of the ALPG, and OT = Pr (Sr)
is expressed as ). on the other hand,
The internal state ST+1 of the ALPG is obtained by applying an update command fr to the internal state ST one step before, and is expressed as ST+l = fr (ST) ---+21. Now, when there are N ALPGs, the internal state and output of each ALPG are the above il+, 12
+Instruction FT for executing the update command and output command in N units in parallel
, +31, +4 by replacing it with GT and changing it.
It is expressed as equation 1.

OT: GT (ST) f
3187++ = FT (ST) ---
--141Here, the output OT does not depend on the number of ALPGs, but is determined by the ALPG internal state STP at that time, so as can be seen from equation (3), GT=not,
It is sufficient to use the output command yT created for one ALPG as is.

On the other hand, from the relationship of equation (2), equation (4) is S-2+u=fT,000N-+ (ST+N-1)"JT+
I+-1°, /'T+N-2(ST+l+-2)"fT
−H4−+ ゛, h+to2 ゛ −−−−−fTH・
Expanded as fT(ST), Fr=JT+n-+・fτten2・----lfT+
+·fT−−−−−+51 is obtained. Here, (5)
The right side of the expression is an expression that means the accumulation of instructions. In other words, each processing instruction B'' assigned every N steps has accumulated (
Must be pretreated.

As a specific example, when N=4 units, fT+5, JT+2
．． JT-+-+.

Each gun is +1. +0. -1. In the case of an addition/subtraction instruction such as +1, the new instruction FT for executing the pot sequence performs iJ calculations on each, and FT=+1+row 1+1=1 is obtained.

From the above points, the second point of the present invention is that each of the plurality of ALs
Regarding the contents of the instructions assigned to the PG, regarding program processing, such as update instructions that control the registers that make up the arithmetic processing unit of each ALPG, those that involve accumulation at each step are newly assigned as accumulation instructions. On the other hand, instructions that simply control the hardware of the output section can be assigned as is.

[Effect]

As shown in Figures 1 and 2, ALP (:r) Taking two parallel executions as an example, we will explain how to expand the program and
The method of allocation to two PGs will be explained in detail. FIG. 1 (cL) is the same as FIG. 6. FIG. 1(b) shows an intermediate state in which the innermost loops L1 and L2 of tcL) are developed.

First, since the number of steps in the loop of Ll is 1, this is expanded to 2 steps, and the number of loops is halved from 32 to 16. From this K, processing step (2) can be executed alternately using two ALPGs (a) and (0). On the other hand, in L2, the number of steps in the loop is 3, so by expanding this to 2 times it becomes 6 steps, which is an integer multiple of 2 ALPGs (2 x 5
) is obtained, and alternate parallel execution becomes possible. however,
In this example of L2, the number of loops is 31, which is an odd number, so the number of loops after expansion is doubled to 15, and the remaining one loop processing section is placed as is at the beginning of L2'. Of course, at this time, it is also possible to take in all the data into L2 and perform the processing in the middle of the loop.

Next, the other outer loop L3' is expanded in the same way, but at this time, the number of steps within the loop in L3 includes the loop L2' that has been expanded inside, and the number of steps is taken into consideration. I have to throw it. That is, L
The number of steps in 3 is 4 + (6X15) + 1 =
Since the number of steps is 95, the relationship of integer multiples of two ALPo cannot be obtained, and the KII-order execution becomes impossible when the loop L3' returns. Therefore, the number of L3' steps is set to the number of ALPG (2
Figure 1 (tc) shows the result of expanding into 190 steps, which is doubled to be an integer multiple of (tc). The number of loops of loop H obtained as a result is 16 times, which is half of 62 times, since it has been expanded twice.

As shown in Figure 1 (C) of the program after the expansion described above, even if there is a loop, it is inconsistent (21 ALP
It can be seen from GK that it can be executed alternately and sequentially.

On the other hand, the remaining processing part for the number of registrations added to the beginning of L2' described in FIG. 1(b) is added to the four parts.

This is simply a consideration for ease of allocating programs to ALPG(a) and ((b)), and is not an essential requirement of the present invention.

Figures 2+a) and (b) show the steps in Figure 1(C) extracted for each ALPG and generated as new programs.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to FIGS. 7 and 8.

FIG. 7 is an overall diagram of an example of an IC testing device constructed from two ALPGs as described in the main points of the present invention.

In this figure, in contrast to the conventional system shown in Fig. 3, the pattern generator 2 section is sequentially selected and switched between the ALPG (a) 17, ALPGt port) 18, clock frequency division/distribution signal generator 21, and two ALPG outputs. AND gate 15'-1, 19-
This is a high-speed IC testing device that is replaced with a high-speed pattern generation section using a parallel execution method, which is configured with 2 and an OR gate 20.

The timing generator 6 uses a conventional method, but the basic operating clock 22 for operating the pattern generator 27 is used as the timing generator 6.
and outputs a timing signal 4 to the waveform generator and comparator. The clock frequency division/distribution signal generator 21 is A shown in FIG.
The distribution signals 24-1, 24-2 for the L P Ci operation clock 23, λL, PG (a) and ALPG (0) are generated by well-known techniques such as kakuntas and gates. The ALPG operation clock 26 is a pattern generator 27
is the velocity of Δ required as the output 26 of .

As shown in FIG.
The processing results of each microprogram executed synchronously and in parallel within LPG (a) and (b) are processed by arithmetic processing units 1 and 2.
It is output as 25-1.25-2.

Gate 19-1.19- for sequential selection switching of these outputs
The clock frequency division/distribution signal generator 21 and distribution No. 6 24-1.24-2 are input to 2, and ALPG high-speed read data 26 as shown in FIG. 8 is obtained.

The computer 1 executes a test pattern program for the pattern generator created for the conventional configuration shown in FIG. 3 before executing the test.
Analyze the program structure in advance, convert and create test programs for Al, l'G (a) and Af, PG (o), and test each hLP (a K-7'-Tapas 22
Transfer using . The computer 1 also sends various data to other parts of FIG.
We perform analysis work on internal data, but these tasks are performed using conventional IC
It is not particularly different from the test equipment.

As described above in this embodiment, a test pattern generation program that allows N ALPGs to operate in parallel is created by the function of the computer 1, and a data bus installed in the IC test equipment is used. By storing these in the ALPG instruction memory before test execution, each ALPG can operate at a clock speed N times slower than the minimum test cycle required for IC test equipment, making it possible to test the latest memory which is rapidly increasing in speed. ICs and LSIs that operate at a slower speed than those used in configuring the device
can be used, and has the effect of easily realizing a test device.

In this example, two ALPG test devices are shown, but of course, this number can be configured with any number N of 2 or more, and in FIGS. 1 and 2, the allocation will be explained later. A when returning from the loop to reduce the number of program steps.
As a method for ensuring the sequentiality of LPG % coverage, it is also possible to provide a configuration in which ALPG for correction is executed only at that time.

〔Effect of the invention〕

According to the present invention, conventionally, a high-speed method of sequentially switching and reading out each memory containing the test pattern itself (
In contrast to memory interleaving, we achieved high-speed execution by parallel operation of multiple ALPGs (named ALPG interleaving) without generating invalid cycles called dummy cycles, even for ALPGs that have their own decision function. (This made it possible to increase the operating speed of the pattern generator several times on the parallel side.

Even with the ultra-high speed of memories such as silicon bipolar and qcLAS, it is sufficient to use high-speed devices only for the AND and OR gate sections of the output section as the pattern generation section shown in Figure 7, and it is possible to use LSIs such as highly integrated CMO8. It becomes possible,
It is easy to implement the device in terms of device cost, mounting area, power consumption, etc.

On the other hand, since it is a method of expanding and allocating programs, the number of program steps required for each ALPG is somewhat small.
Since the number of commands increases or the operating speed can be slowed down, a relatively large capacity instruction memory can be used.

[Brief explanation of drawings]

Figures 1 and 2 show the main points of the present invention and the program development layout. Figure 3 is a schematic diagram of the conventional Memory Memory C test equipment. Figure 4 shows the pattern generator of Figure 3. Internal configuration diagram,
FIG. 5 is an example of a microprogram for generating a gearropping pattern, which is well known as a memory test pattern, FIG. 6 is a schematic diagram of FIG. 5, FIG. 7 is an embodiment of the present invention, and FIG. is a timing diagram of the main signals in FIG. 7; FIG. 9 is a diagram showing an operational expression for the internal configuration of ALPG. DESCRIPTION OF SYMBOLS 1... Computer, 2... Pattern generator, 6... Timing generator, 7... Sequence control section, 8...
Arithmetic processing unit, 9...instruction memory, 17.18...A
LPG (a), (b), 22... Clock frequency division/distribution signal generator, 22... Device bus, 26... ALPG
Operation clock, 24-1.24-2...ALGP distribution number, 25-1.25-2...ALPF output data, 26...ALPG high-speed output data. '-'''ko (. Agent Patent Attorney Katsuo Ogawa ゛- Departure 2A (α) (b), 4 LP6C 4 pieces V size σ block'am
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Claims (1)

[Scope of Claims] 1. N algorithmic pattern generation means that operate with synchronized clocks, switching means that can selectively switch the output of the algorithmic pattern generation means at a speed N times faster than the clock; means for generating a test waveform to be supplied to the IC under test based on the output of the algorithmic pattern generation means; means for comparing the output from the IC under test with an expected value; input to the synchronization clock and the switching means; a timing generating means for generating a signal, a clock of the waveform generating means and a timing signal to the comparing means, and a pattern program so that each of the algorithmic pattern generating means can generate a pattern in parallel, and the pattern program. An IC testing device comprising means for controlling the algorithmic pattern generating means based on the following. 2. The pattern program is generated by expanding the number of steps in a program portion having a repetitive structure such as a loop so that it becomes an integer multiple of the N pieces. IC test equipment. 3. The pattern program is generated by adding a step for obtaining the cumulative result for a part that involves accumulation in the steps of the program, and each of the algorithmic pattern generation means can operate independently and in parallel. Claim 1 characterized in that
The IC test device according to item 1 or 2.