JPS6334661B2 - - Google Patents

Info

Publication number
JPS6334661B2
JPS6334661B2 JP53091945A JP9194578A JPS6334661B2 JP S6334661 B2 JPS6334661 B2 JP S6334661B2 JP 53091945 A JP53091945 A JP 53091945A JP 9194578 A JP9194578 A JP 9194578A JP S6334661 B2 JPS6334661 B2 JP S6334661B2
Authority
JP
Japan
Prior art keywords
frequency
output
circuit
resistor
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53091945A
Other languages
Japanese (ja)
Other versions
JPS5566142A (en
Inventor
Shigenobu Aihara
Isao Haga
Motoo Mizumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9194578A priority Critical patent/JPS5566142A/en
Publication of JPS5566142A publication Critical patent/JPS5566142A/en
Publication of JPS6334661B2 publication Critical patent/JPS6334661B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【発明の詳細な説明】 本発明はSHFあるいはUHF帯において用いら
れる自動周波数制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic frequency control device used in the SHF or UHF band.

従来、SHF帯のような超高周波帯における発
振周波数は、基準周波数の高調波を逓倍器によつ
て形成し、これを安定化すべき電圧制御発振器
(以下VCOという)の発振出力と周波数混合して
中間周波数に変換したのち周波数弁別にかけて誤
差電圧をとり出し、それによつて上記VCOの発
振周波数を制御することにより安定している。
Conventionally, the oscillation frequency in ultra-high frequency bands such as the SHF band is determined by forming harmonics of the reference frequency using a multiplier, and frequency-mixing this with the oscillation output of a voltage-controlled oscillator (hereinafter referred to as VCO) to be stabilized. After converting to an intermediate frequency, frequency discrimination is performed to extract an error voltage, which is used to control the oscillation frequency of the VCO, thereby stabilizing the voltage.

しかしながら、このような構成では、VCO出
力と周波数混合すべき高調波信号の帯域が上記逓
倍器の帯域により制御されるので、自動周波数制
御装置の帯域が制限を受ける。これを避けるため
に逓倍器と帯域ろ波器(以下BPFという)との
組合せを多段接続したものが用いられているが、
装置全体がそのために複雑な構成となる。一方、
逓倍器の出力である高調波信号がダウンコンバー
タを通してVCOの出力に洩れて出力されること
があり信頼度が低い。
However, in such a configuration, since the band of the harmonic signal to be frequency-mixed with the VCO output is controlled by the band of the multiplier, the band of the automatic frequency control device is limited. To avoid this, a multistage combination of a multiplier and a bandpass filter (hereinafter referred to as BPF) is used.
The entire device therefore has a complex configuration. on the other hand,
The harmonic signal that is the output of the multiplier may leak into the VCO output through the down converter and be output, resulting in low reliability.

本発明の目的は、これらの問題点を解決し、広
帯域にわたつて使用できかつ構成が簡単な自動周
波数制御装置を提供することにある。
An object of the present invention is to solve these problems and provide an automatic frequency control device that can be used over a wide band and has a simple configuration.

本発明によれば、制御電圧に応答して変化する
周波数vの発振出力を生ずる電圧制御発振器
と;基準周波数xの高周波信号を生ずる高周波
信号源と;高周波信号に応答して、基準周波数
xの高調波成分nxを含むパルス列を発生するた
め、逓倍用ダイオードと;入力端が前記高周波源
に接続され、出力端が逓倍用ダイオードに並列に
接続され、並列接続点がそれぞれ抵抗を介して接
地されたトランスとを含む第1の回路と;逓倍用
ダイオードに並列に結合され、それぞれの結合点
が抵抗とコンデンサとの直列回路を介して接地さ
れた1対の直列の検波ダイオードを含み、直列の
検波ダイオード間の接続点に周波数vを入力し、
直列回路の抵抗とコンデンサとの接続点から高調
波成分nxと周波数vとの差成分を出力する第2
の回路と;この差成分の周波数変動を検出する周
波数弁別器と;この周波数弁別器の出力を制御電
圧として電圧制御発振器に供給する手段とを含
み、周波数vを安定化することを特徴とする自
動周波数制御装置が得られる。
According to the present invention, a voltage controlled oscillator that generates an oscillation output with a frequency v that changes in response to a control voltage; a high frequency signal source that generates a high frequency signal with a reference frequency x;
In order to generate a pulse train containing harmonic components nx of x, a multiplier diode is connected; a first circuit including a grounded transformer; a pair of series detection diodes coupled in parallel to the multiplier diode, each coupling point being grounded via a series circuit of a resistor and a capacitor; Input the frequency v at the connection point between the series detection diodes,
A second circuit that outputs the difference component between the harmonic component nx and the frequency v from the connection point between the resistor and the capacitor in the series circuit.
A frequency discriminator for detecting the frequency fluctuation of the difference component; and means for supplying the output of the frequency discriminator as a control voltage to a voltage-controlled oscillator to stabilize the frequency v. An automatic frequency control device is obtained.

以下、図面により本発明を詳細に説明する。 Hereinafter, the present invention will be explained in detail with reference to the drawings.

第1図は本発明の実施例のブロツク図を示す。
まず、水晶発振器11から供給される基準周波数
xの信号はパルス発生器12に供給され、くり
返し周波数xのパルス信号を形成する。このパ
ルス信号は周波数xの高調波成分nxを含んでい
る。このパルス信号はスイツチング回路13に供
給されて、VCO10の出力信号(周波数v)を
スイツチングする。したがつて、この出力波形は
くり返し周波数xで周波数vの信号を断続した
ものとなる。この出力信号には周波数Vと高周波
成分nxとの差周波数成分|nx−v|が含まれ
ている。なお高調波nxは周波数vに最も近い周
波数とし周波数成分|nx−v|は周波数xの1/
3以下に選ぶのが設計上適当である。この差周波
数成分|nx−v|は増幅器14により増幅さ
れ、周波数弁別器15に供給される。この周波数
弁別器15はもう一つの水晶発振器16の基準周
波数pを基準として差周波数成分|nx−v|の
周波数変動分を検出する。
FIG. 1 shows a block diagram of an embodiment of the invention.
First, the reference frequency supplied from the crystal oscillator 11
The x signal is fed to a pulse generator 12 to form a pulse signal with a repetition frequency x. This pulse signal includes a harmonic component nx of frequency x. This pulse signal is supplied to the switching circuit 13 to switch the output signal (frequency v) of the VCO 10. Therefore, this output waveform is an intermittent signal of frequency v at repetition frequency x. This output signal includes a difference frequency component |nx−v| between the frequency V and the high frequency component nx. The harmonic nx is the frequency closest to the frequency v, and the frequency component |nx−v| is 1/of the frequency x.
It is appropriate for the design to select 3 or less. This difference frequency component |nx-v| is amplified by an amplifier 14 and supplied to a frequency discriminator 15. This frequency discriminator 15 detects the frequency variation of the difference frequency component |nx-v| with reference to the reference frequency p of another crystal oscillator 16.

この周波数弁別器15は、特願昭52−27571に
説明されているようなデイジタル型周波数弁別器
であり、2つの入力波の位相差が0〜+180度お
よび0〜−180度に該当する期間、一定の波高値
の矩形波をそれぞれ出力するデイジタル的位相検
波器(例えば、NEC製μPC1008C)と、この各各
の出力を入力波とその高調波を阻止する2つの低
域ろ波器と、これら低域ろ波器の各出力の周波数
弁別特性の傾斜をつくる2つの高域ろ波器と、こ
れら高域ろ波器の2つの出力を整流してこれらの
差電圧をとり出す手段とから構成される。この周
波数弁別器はデイジタル回路から構成されるので
不要混合波に対しては応答せずに安定に動作する
ので、この実施例のように不要混合波を含む回路
に適している。
This frequency discriminator 15 is a digital frequency discriminator as described in Japanese Patent Application No. 52-27571, and is a period during which the phase difference between two input waves corresponds to 0 to +180 degrees and 0 to -180 degrees. , a digital phase detector (for example, μPC1008C manufactured by NEC) that outputs a rectangular wave with a constant peak value, and two low-pass filters that block the input wave and its harmonics from each output. Two high-pass filters that create slopes in the frequency discrimination characteristics of the respective outputs of these low-pass filters, and a means for rectifying the two outputs of these high-pass filters to extract a voltage difference between them. configured. Since this frequency discriminator is composed of a digital circuit, it operates stably without responding to unnecessary mixed waves, and is therefore suitable for a circuit including unnecessary mixed waves as in this embodiment.

この周波数弁別器からの差電圧は、VCO10
に供給されてその発振周波数を制御する制御電圧
となる。このVCO10の出力信号はスイツチン
グ回路13に帰還されて、自動周波数制御ループ
が構成され、周波数|nx−v|が基準周波数o
と一致するように制御されるので、VCOの出力
周波数vは安定化される。
The differential voltage from this frequency discriminator is VCO10
It becomes a control voltage that is supplied to the oscillator and controls its oscillation frequency. The output signal of this VCO 10 is fed back to the switching circuit 13 to configure an automatic frequency control loop, and the frequency |nx-v| is set to the reference frequency o.
The output frequency v of the VCO is stabilized.

第2図は、第1図のパルス発生器12およびス
イツチング回路13の具体的回路図である。
FIG. 2 is a specific circuit diagram of the pulse generator 12 and switching circuit 13 shown in FIG. 1.

パルス発生器12は逓倍用ダイオードD1と、
入力端20が高周波源(水晶発振器)11に接続
され、出力端が逓倍用ダイオードD1に並列に接
続され、この並列接続点がそれぞれ抵抗R1及び
R2を介して接地されたトランスT1から構成さ
れ、スイツチング回路13は、逓倍用ダイオード
D1に並列に結合され、この結合点がそれぞれ抵
抗R6とコンデンサC4および抵抗R5とコンデ
ンサC3の直列回路を介して接地された一対の直
列の検波ダイオードD2,D3から構成されてい
る。パルス発生器12およびスイツチング回路1
3は、抵抗R3,R4およびコンデンサC1,C
2を介して結合されている。上述の直列のダイオ
ードD2とD3との接続点に入力端21から抵抗
R7を介して周波数vを入力し、直列接続され
た抵抗R6およびコンデンサC4間から抵抗R8
を介して出力端22から高調波成分nxと周波数
vとの差成分を出力する。この具体例の周波数
関係は、周波数xが100MHz(すなわち、くり返
し周期10ns)周波数pが20MHz、周波数vが
7020MHz、逓倍数nが70となつている。まず、入
力端20に基準周波数(x)100MHzの信号が供給
されると、パルス発生器はトランスT1と逓倍用
ステツプリカバリーダイオードD1(例えば、NEC
製SV24B)とにより、このダイオードD1、のカ
ソード側に正のパルスを出力すると共にアノード
側に負のパルスを出力する。この具体例では、く
り返し周期10nsでパルス幅1〜2nsのパルスがみ
られた。
The pulse generator 12 includes a multiplier diode D1,
It consists of a transformer T1 whose input end 20 is connected to a high frequency source (crystal oscillator) 11, whose output end is connected in parallel to a multiplier diode D1, and whose parallel connection points are grounded via resistors R1 and R2, respectively. The switching circuit 13 is connected in parallel to the multiplier diode D1, and the coupling point is connected to a pair of series detection diodes D2 and D3 which are grounded through a series circuit of a resistor R6 and a capacitor C4, and a resistor R5 and a capacitor C3, respectively. It is configured. Pulse generator 12 and switching circuit 1
3 are resistors R3, R4 and capacitors C1, C
2. The frequency v is inputted from the input terminal 21 to the connection point between the series diodes D2 and D3 through the resistor R7, and the frequency v is inputted from the resistor R8 connected in series between the resistor R6 and the capacitor C4.
harmonic component nx and frequency from output end 22 via
Outputs the difference component with v. The frequency relationship in this example is that frequency x is 100MHz (i.e., repetition period 10ns), frequency p is 20MHz, and frequency v is
7020MHz, multiplication number n is 70. First, when a signal with a reference frequency (x) of 100 MHz is supplied to the input terminal 20, the pulse generator converts the transformer T 1 and step recovery diode D 1 (for example, NEC
SV24B) outputs a positive pulse to the cathode side of this diode D 1 and outputs a negative pulse to the anode side. In this specific example, pulses with a repetition period of 10 ns and a pulse width of 1 to 2 ns were observed.

正のパルスは、スイツチング回路13のダイオ
ードD3(例えば、NEC製ISS12)のアノード側に、
負のパルスはダイオードD2のカソード側に同時
に供給され、このパルスが供給されている間だ
け、これらダイオードD2,D3はONとなる。した
がつて、入力端21から供給されるVCOの出力
信号(7GHz)は、これらダイオードD2,D3
ONの間、抵抗R6とバイパスコンデンサC4との接
続点に出力される。この出力は、10ns周期で1〜
2ns幅の7GHz信号を含むパルス状波形であり、当
然差周波数成分|nx−v|、すなわち20MHzを
含んでおり、低周波成分であるこの20MHz信号は
コンデンサC4でバイパスされることなく出力端
子22に出力される。この20MHz成分は、増幅器
14で増幅され、水晶発振器16の基準周波数
20MHzを基準として周波数弁別される。
The positive pulse is applied to the anode side of the diode D 3 (for example, NEC ISS12) of the switching circuit 13.
Negative pulses are simultaneously supplied to the cathode side of diode D 2 , and these diodes D 2 and D 3 are ON only while this pulse is being supplied. Therefore, the output signal (7GHz) of the VCO supplied from the input terminal 21 is the output signal of these diodes D2 and D3 .
While ON, it is output to the connection point between resistor R 6 and bypass capacitor C 4 . This output changes from 1 to 1 with a period of 10 ns .
It is a pulsed waveform containing a 7 GHz signal with a width of 2 ns , and naturally contains a difference frequency component |nx−v|, i.e., 20 MHz , and this 20 MHz signal, which is a low frequency component, is bypassed with capacitor C 4 . The signal is outputted to the output terminal 22 without any interference. This 20 MHz component is amplified by the amplifier 14 and is then set to the reference frequency of the crystal oscillator 16.
Frequency discrimination is performed based on 20 MHz .

なお、パルス発生器の逓倍数nは、VCOの動
作する周波数可変範囲が狭い場合(例えば、上記
具体例ではv=7GHz±50MHz)には必然的にn=
70と定まるが、制御電圧の加わらない場合の
VCO発振周波数が7GHzに設定できる場合もn=
70と決定できる。
Note that the multiplier n of the pulse generator is necessarily n = when the frequency variable range in which the VCO operates is narrow (for example, in the above example, v = 7 G Hz ± 50 M Hz).
70, but when no control voltage is applied
Even if the VCO oscillation frequency can be set to 7 GHz , n =
It can be determined as 70.

この発明を構成するパルス発生器およスイツチ
ング回路は、帯域制限する要素をもたないので広
帯域であり、VCOの周波数vを変更する場合も、
水晶発振器11の周波数を変更するだけで任意の
周波数において使用することができる。またこの
発明の逓倍回路には多段のBPFが不要であり回
路構成が簡単になる。さらにスイツチング回路に
おいては、直列接続の検波ダイオードのアノード
側およびカソード側に正および負のパルスを、そ
れぞれ同時に供給する構成になつているので、周
波数vの近傍の周波数成分nxの動作レベルが従
来のミキサの動作レベルに比較して低レベルで動
作できるので、VCOの出力側に洩れる周波数成
分nxを少くでき、スプリアスの少い周波数出力
を得ることができる。
The pulse generator and switching circuit that constitute this invention have a wide band because they do not have any band-limiting elements, and even when changing the frequency v of the VCO,
It can be used at any frequency by simply changing the frequency of the crystal oscillator 11. Furthermore, the multiplier circuit of the present invention does not require a multi-stage BPF, which simplifies the circuit configuration. Furthermore, since the switching circuit is configured to simultaneously supply positive and negative pulses to the anode and cathode sides of the series-connected detection diodes, the operating level of the frequency component nx near the frequency v is lower than that of the conventional one. Since it can operate at a lower level than the mixer operating level, the frequency component nx leaking to the output side of the VCO can be reduced, and a frequency output with less spurious can be obtained.

以上説明したとおり、本発明の自動周波数制御
装置は周波数の広帯域化と回路構成の簡単化とに
より、SHF帯以上の超高周波帯の周波数安定化
に有効である。
As explained above, the automatic frequency control device of the present invention is effective for frequency stabilization in the ultra-high frequency band above the SHF band by widening the frequency band and simplifying the circuit configuration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例のブロツク図、第2図
は第1図の部分回路図である。図において、 10……VCO、11,16……水晶発振器、
12……パルス発生器、13……スイツチング回
路、14……中間周波増幅器、15……デイジタ
ル周波数弁別器、20,21……入力端、22…
…出力端、である。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a partial circuit diagram of FIG. In the figure, 10...VCO, 11, 16...Crystal oscillator,
12... Pulse generator, 13... Switching circuit, 14... Intermediate frequency amplifier, 15... Digital frequency discriminator, 20, 21... Input end, 22...
...is the output end.

Claims (1)

【特許請求の範囲】[Claims] 1 制御電圧に応答して変化する周波数v発振
出力を生ずる電圧制御発振器と;基準周波数x
の高周波信号を生ずる高周波信号源と;前記高周
波信号に応答して、前記基準周波数xの高調波
成分nxを含むパルス列を発生させるため、逓倍
用ダイオードと;入力端が前記高周波源に接続さ
れ、出力端が前記逓倍用ダイオードに並列に接続
され、並列接続点がそれぞれ抵抗を介して接地さ
れたトランスとを含む第1の回路と;前記逓倍用
ダイオードに並列に結合され、それぞれの結合点
が抵抗とコンデンサとの直列回路を介して接地さ
れた1対の直列の検波ダイオードを含み、前記直
列の検波ダイオード間の接続点に前記周波数v
を入力し、前記直列回路の抵抗とコンデンサとの
接続点から前記高調波成分nxと前記周波数vと
の差成分を出力する第2の回路と;この差成分の
周波数変動を検出する周波数弁別器と;この周波
数弁別器の出力を前記制御電圧として前記電圧制
御発振器に供給する手段とを含み、前記周波数
vを安定化することを特徴とする自動周波数制
御装置。
1. A voltage-controlled oscillator that produces an oscillation output with a frequency v that changes in response to a control voltage; a reference frequency x
a high-frequency signal source that generates a high-frequency signal; a multiplier diode for generating a pulse train including a harmonic component nx of the reference frequency x in response to the high-frequency signal; an input end connected to the high-frequency source; a first circuit including a transformer whose output end is connected in parallel to the multiplier diode, and each parallel connection point is grounded via a resistor; A pair of series detection diodes are grounded through a series circuit of a resistor and a capacitor, and the frequency v is connected to the connection point between the series detection diodes.
and a second circuit that outputs a difference component between the harmonic component nx and the frequency v from a connection point between the resistor and the capacitor of the series circuit; a frequency discriminator that detects frequency fluctuations of this difference component; and; means for supplying the output of the frequency discriminator to the voltage controlled oscillator as the control voltage;
An automatic frequency control device characterized by stabilizing v.
JP9194578A 1978-07-26 1978-07-26 Automatic frequency control unit Granted JPS5566142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9194578A JPS5566142A (en) 1978-07-26 1978-07-26 Automatic frequency control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9194578A JPS5566142A (en) 1978-07-26 1978-07-26 Automatic frequency control unit

Publications (2)

Publication Number Publication Date
JPS5566142A JPS5566142A (en) 1980-05-19
JPS6334661B2 true JPS6334661B2 (en) 1988-07-12

Family

ID=14040719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9194578A Granted JPS5566142A (en) 1978-07-26 1978-07-26 Automatic frequency control unit

Country Status (1)

Country Link
JP (1) JPS5566142A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS509360A (en) * 1973-05-23 1975-01-30

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS509360A (en) * 1973-05-23 1975-01-30

Also Published As

Publication number Publication date
JPS5566142A (en) 1980-05-19

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