JPS6334640A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate the reproduction of an LSI even when a fault in design is generated, by trapping an instruction by a specific condition, and executing an instruction group in a specific area. CONSTITUTION:At the time of detecting a trapping condition at a decoder 4 by the instruction set at an instruction register 1, the content of an instruction counter 9 is saved in a prescribed memory area, and a new value is taken out from the prescribed area, then it is set at the instruction register 9. In the above state, a device progresses in a trap mode, and the trap segment descriptor of a segment register 3 is used as an instruction segment. And since the combination of the instructions that substitutes the combination of another basic instructions for an instruction function in which a trap is generated, is set in the trap segment in advance, the instruction function in which the trap is generated, can be processed by branching control to the segments.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to avoiding design failures in LSI-based information processing devices.

(Prior art) When a design failure occurs in an LSI-based information processing device, there is a high probability that the LSI will need to be remanufactured to resolve the problem.On the other hand, the turnaround time is relatively short. Even if the gate array method is short,
LSI remanufacturing takes a longer time than SS engineering technology, and the impact on the device development and evaluation period is extremely large.

(Problems to be Solved by the Invention) As mentioned above, conventional LSI-based information processing devices require a long turnaround time. In order to proceed smoothly, there is a disadvantage in that the means to avoid design failures in the LSI hardware that require remanufacturing are indispensable.

An object of the present invention is to have a decoder that decodes instructions taken out from main memory, and the decoder recognizes that another specific instruction code is taken out following a specific instruction or code,
Can these specific instruction codes be set arbitrarily and the drawbacks mentioned above? An object of the present invention is to provide an information processing device configured to eliminate the problems and shorten the turnaround time.

(Means for Solving Problems) The information processing apparatus according to the invention is equipped with a decoder comprising instruction code condition detection means and instruction code setting means.

The instruction code condition detection means is for detecting that another specific instruction code is taken out following a specific instruction code.

The instruction code setting means is for arbitrarily setting all pairs of consecutive specific instruction codes using the random access memory.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an instruction control section of an embodiment of an information processing apparatus according to the present invention. In FIG. 1, l is an instruction register, 2 is an inch register, 3 is a segment register, 4 is a decoder, 5 is an address adder, 6 is a virtual address register, 7 is a TLB, 8 is a control circuit, 9 is an instruction counter, 10 is a counter, and 11 and 12 are switching circuits.

In FIG. 1, instruction register l is cache memory (
Not shown. This is an instruction register for setting the read data sound from ), and the inch register 2 is used for address modification when calculating an operand address according to the designation of the instruction word set in the instruction register 1. The segment register 3 stores a segment descriptor, and is used to calculate a virtual operand address according to the instruction word set in the instruction register 1.

The address adder 5 inputs the contents of the instruction register 11, index register 2, and segment register 3, and calculates a virtual address. The calculated virtual address is set in the virtual address register 6, converted to a real address by the TLB 7, and sent to the cache memory. The decoder 4 receives the instruction code set in the instruction register 1,
and the address calculation specification field to detect trap conditions.

Instructions are taken out according to the instructions of the instruction counter 9,
Each time an instruction fetch request is sent, the contents of the instruction counter 9 are incremented by 1 via the counters 10. When a branch instruction is executed or initialized, the instruction counter 9 is initialized by an arithmetic processing section (not shown).

When a trap condition is detected by the decoder 4 due to the instruction set in the instruction register 1, the contents of the instruction counter 9 are saved in a predetermined memory area after being corrected to specify all the next instructions. A new value is taken out from the specified area and set in the instruction counter 9.

In this state, the information processing device enters the trap mode, and the trap segment descriptor of the segment register 3 is used as an instruction segment. This discriminator is not used except in trap mode. Does the trap segment have a trap during initial configuration? Seven command combinations are prepared in which the next command function is substituted by a combination of other basic commands. Thereby, each mk branch to the above segment causes the tran 12 to process the generated instruction functionally.

On the other hand, when executing an instruction in a trap segment, it may be necessary to access the instruction segment of the trapped instruction as an operand. For this reason, a load instruction is added to extract an operand from the instruction segment. This instruction uses a trap-generated instruction segment discrettor as an operand segment discrettor. The operand segment descriptor can be accessed arbitrarily even in trap mode.

At the end of the trap segment command group, a refined command is prepared to take out the contents of the command counter 9 from the save area t and set it, as well as to set the trap mode t″m.

FIG. 2 is a block diagram showing the decoder 4 of FIG. 1 in detail. In FIG. 2, 19 is a condition setting circuit for setting specified condition t, 20 is a gate logic circuit, and 2
1 is a decoder, and 22 is a condition detection circuit.

The decoder 4 includes a gate logic circuit 2 () set in the instruction register 1 and accessed by the next instruction code, a decoding circuit 21 for decoding the field specifying the address modification set in the instruction register 1, and the decoding circuit 2
Trap condition by inputting all outputs of 1? and a condition detection circuit 22 for detection. Gate logic circuit 2
0 has a plurality of bits of entry corresponding to the instruction code, and in combination with the output of the decoding circuit 21, the gate logic port fI
? 520 random bit? If set, is the condition that another specific instruction code is retrieved consecutively to a specific instruction code?
can be detected.

FIG. 3 is a block diagram showing the condition detection circuit 22 in FIG. 2 in detail. In FIG. 3, 23 is a flip-flop, 24 to 27 are NAND gates, and 28 is an OR gate.
It is a gate. Signal lines 60 to 64 are output signal lines of gate logic circuit 20, and signal lines 71 to 73 are outputs of decoding circuit 21. NAND gates 25-27
outputs a trap condition IJ based on an output signal corresponding to a specific command sent via signal lines 62-64 and an address modification condition sent via signal lines 71-73.

The flip-flop 23 is set by the output of the gate logic circuit 20 corresponding to the most recently executed instruction, and the NA
The ND gate 24 detects specific instruction combination conditions. NAND gates 25-27 have similar configurations. The logical sum of these detected conditions is OR gate 2.
8 and is reported to the processor via signal line 74.

The contents of the gate logic circuit 20 are set as part of the initial setting when the device is turned on or reset, depending on the trap condition.

In non-implemented examples, the instruction code, address modification field,
Although trap conditions are detected by a combination of instructions and commands, it is clear that conditions such as master mode/slave mode can also be used.

In this embodiment, when a specific instruction and another specific instruction are consecutive, execution of the instruction in a specific area of the main memory is started, but the processing of the second specific instruction is the same as the first one. There is also a method of solving the problem by separating the processing from the instruction in time and restarting from re-fetching the second instruction in order to eliminate processing interference between instructions.

(Effects of the Invention) As explained above, the present invention traps instructions under specific conditions and executes them on a group of instructions in a specific area.
This has the effect that all design obstacles can be avoided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of an information processing apparatus according to the present invention. Figures 2 and 3 show details of the decoder shown in Figure 1.
FIG. l...Instruction register 2...Index register 3
...Segment register 4...Decoder 5...
・Address adder 6...Virtual address register 7...TLB8・
...Control circuit 9... is an order counter lO...Counter 11.12...Switching circuit 19...Condition setting circuit 20...Gate logic circuit 21...Decoding circuit 22...Condition detection Circuit 23...Flip-flops 24-27...NAND gate 28...OR gate

Claims (1)

[Claims] an instruction code condition detection means for detecting that another specific instruction code is taken out consecutively to a specific instruction code; and a pair of the slow specific instruction code is set as specified. 1. An information processing apparatus comprising: a decoder comprising an instruction code setting means for the information processing apparatus.