JPS63318822A - Echo canceler type 2-wire/4-wire canceler - Google Patents

Echo canceler type 2-wire/4-wire canceler

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Publication number
JPS63318822A
JPS63318822A JP15575687A JP15575687A JPS63318822A JP S63318822 A JPS63318822 A JP S63318822A JP 15575687 A JP15575687 A JP 15575687A JP 15575687 A JP15575687 A JP 15575687A JP S63318822 A JPS63318822 A JP S63318822A
Authority
JP
Japan
Prior art keywords
circuit
signal
echo canceller
echo
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15575687A
Other languages
Japanese (ja)
Inventor
Susumu Yasuda
晋 安田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15575687A priority Critical patent/JPS63318822A/en
Publication of JPS63318822A publication Critical patent/JPS63318822A/en
Pending legal-status Critical Current

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Bidirectional Digital Transmission (AREA)

Abstract

PURPOSE:To judge a trouble of an echo canceler or the disconnection of a line in a communication unable state by detecting only a pseudo echo in a look-back mode to confirm the normal working of an echo canceler. CONSTITUTION:In a loop-back mode a switch 3 is set at a ground level with a switch 7 connected to a bit inverting circuit 6 and an estimated coefficient is fixed by means of a switch 13. Under such conditions, a pseudo echo signal produced by an echo canceler is supplied to a subtraction circuit 4 and an inverted pseudo echo signal is supplied to a wave detecting circuit 5. The pseudo echo signal undergone the wave detection and binary coding through the circuit 5 is supplied to an interface part 8 after the bit inverted by the circuit 6. The part 8 compares the transmission signal with the received pseudo signal. Then the normal working of the echo canceler is decided when the coincidence is obtained between said both signals. Thus the loop-back mode is through and a normal working state is reset.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、データ通信におけるエコーキャンセラ方式2
線4線変換回路に関し、特にループバックによるエコー
キャンセラ機能のチェック方式に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an echo canceller method 2 in data communication.
The present invention relates to a four-wire conversion circuit, and particularly to a method for checking an echo canceller function using loopback.

〔従来の技術〕[Conventional technology]

従来のエコーキャンセラのブロック図を第3図に示す。 A block diagram of a conventional echo canceller is shown in FIG.

1は2線/4線変換用ノ・イブリッド回路、2はエコー
キャンセラー、4は受信信号から疑似エコー信号を差引
く減算回路、5は検波回路、8はインタフェース部、9
は送信信号路、10は2線信号路、11は受信信号路、
12はエコーキャンセラの収束を示す収束信号である。
1 is a hybrid circuit for 2-wire/4-wire conversion, 2 is an echo canceller, 4 is a subtraction circuit for subtracting a pseudo echo signal from the received signal, 5 is a detection circuit, 8 is an interface section, 9
is a transmission signal path, 10 is a two-wire signal path, 11 is a reception signal path,
12 is a convergence signal indicating convergence of the echo canceller.

インタフェース部8から送られた信号は送信信号路9を
通ってハイブリット回路1に入力される。
A signal sent from the interface section 8 is input to the hybrid circuit 1 through a transmission signal path 9.

ハイブリット回路1において、インピーダンス不整合に
よって送信信号の一部がエコー信号として受信信号路1
1に回り込む。一方エコーキャンセラ2は送信信号と予
測係数を用いて疑似エコー信号を作シ出し、減算回路4
に入力する。減算回路4の出力はエコー信号と疑似エコ
ー信号の差で、残留エコーと呼ばれ、エコーキャンセラ
2と検波回路5に入力される。エコーキャンセラは残留
エコー信号が小さくなるように予測係数を増減し、残留
エコーがあらかじめ設定した値よシ小さくなると収束し
たとみなして、収束信号12を出力する。したがって、
収束信号12によってエコーキャンセラ2は正常動作し
ているとみなされる。
In the hybrid circuit 1, due to impedance mismatch, a part of the transmitting signal is converted into an echo signal to the receiving signal path 1.
Go around to 1. On the other hand, the echo canceller 2 creates a pseudo echo signal using the transmission signal and the prediction coefficient, and the subtraction circuit 4
Enter. The output of the subtraction circuit 4 is the difference between the echo signal and the pseudo echo signal, which is called a residual echo, and is input to the echo canceller 2 and the detection circuit 5. The echo canceller increases or decreases the prediction coefficient so that the residual echo signal becomes smaller, and when the residual echo becomes smaller than a preset value, it is considered that convergence has occurred and outputs a convergence signal 12. therefore,
Based on the convergence signal 12, it is assumed that the echo canceller 2 is operating normally.

また、第4図に示す他の従来の回路ではインタフェース
部80入力として送信信号と検波回路5の出力のいずれ
かを選択するスイッチ15を送信信号側に接続すること
によってディジタル回路部ループバックを実行している
Further, in another conventional circuit shown in FIG. 4, loopback of the digital circuit section is executed by connecting a switch 15 for selecting either the transmitting signal or the output of the detection circuit 5 as the input of the interface section 80 to the transmitting signal side. are doing.

〔発明が解決しようとする間頂点〕[Apex while the invention is trying to solve]

上述した従来のエコーキャンセラの機能チェック方式で
は、適応動作の収束信号のみでエコーキャンセラの収束
を判断するため、実際にエコーキャンセラの動作が正常
に行なわれているかどうかは、通信を行なうまでわから
ない。したがって、通信不能の場合、エコーキャンセラ
動作が正常でないのか、線路の断線か、送信側の故障か
が特定できないという欠点があった。
In the conventional echo canceller function check method described above, convergence of the echo canceller is determined only by the convergence signal of the adaptive operation, so it is not known whether the echo canceller is actually operating normally until communication is performed. Therefore, when communication is impossible, there is a drawback that it is impossible to determine whether the echo canceller is malfunctioning, whether there is a break in the line, or whether there is a failure on the transmitting side.

また、ディジタル回路部のみのループバックでは、送信
側の故障かどうかの診断はできてもエコーキャンセラお
よび伝送線路の故障を診断することができないという欠
点があった。
Furthermore, loopback of only the digital circuit section has the disadvantage that although it is possible to diagnose whether or not there is a failure on the transmitting side, it is not possible to diagnose failures in the echo canceller or the transmission line.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の目的は通信障害が起った時、故障がディジタル
回路で発生したかエコーキャンセラ回路で発生したか、
線路上で発生したかを識別することができるエコーキャ
ンセラ方式2線4線変換回路を得ることにある。
The purpose of the present invention is to determine whether the failure occurred in the digital circuit or the echo canceller circuit when a communication failure occurs.
To obtain an echo canceller type two-line and four-line conversion circuit capable of identifying whether an echo has occurred on a line.

本発明によれば、2線式伝送路を用いてディジタル信号
の全二重通信をするためのエコーキャンセラ方式2線4
線変換回路において、2線4線変換用ハイブリット回路
と、エコーキャンセラー回路と、受信信号を検波する検
波回路と減算回路と、インターフェイス部とを有し、エ
コーキャンセラ回路のエコーキャンセル動作が収束後、
受信信号と疑似エコー信号の差をとる減算回路の入力を
疑似エコー信号のみとすることによって減算回路から擬
似エコーの反転信号のみを出力させ前記反転信号を検波
しビット反転した後に送信信号と照合するようにしたエ
コーキャンセラ方式2線4線変換回路を得る。
According to the present invention, an echo canceller system 2-wire 4
The line conversion circuit includes a hybrid circuit for 2-wire and 4-wire conversion, an echo canceller circuit, a detection circuit for detecting a received signal, a subtraction circuit, and an interface section, and after the echo canceling operation of the echo canceller circuit converges,
By inputting only the pseudo echo signal to the subtraction circuit that takes the difference between the received signal and the pseudo echo signal, only the inverted signal of the pseudo echo is output from the subtraction circuit, and the inverted signal is detected, bit inverted, and then compared with the transmitted signal. Thus, an echo canceller type 2-wire 4-wire conversion circuit is obtained.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。1
は2線/4線変換用ハイブリット回路、2はエコーキャ
ンセラ、3は減算回路4の入力を受信信号と接地レベル
のいずれかに切換えるスイッチ、5は受信信号を2(i
ifのディジタル値に変換する検波回路、6は5で得ら
れた2値データを反転するビット反転回路、7はインタ
ーフェース部8の入力信号を検波回路5の出力とビット
反転回路6のいずれかに切換えるスイッチ、9は送信信
号路、10は2線信号路、11は受信信号路、12はエ
コーキャンセラが収束したことを示す収束信号である。
FIG. 1 is a block diagram showing one embodiment of the present invention. 1
is a hybrid circuit for 2-wire/4-wire conversion, 2 is an echo canceller, 3 is a switch that switches the input of subtraction circuit 4 to either the received signal or the ground level, and 5 is a switch that switches the input of the received signal to 2(i
6 is a bit inversion circuit that inverts the binary data obtained in step 5; 7 is a detection circuit that converts the input signal of the interface section 8 into the output of the detection circuit 5 and the bit inversion circuit 6; 9 is a transmission signal path, 10 is a two-wire signal path, 11 is a reception signal path, and 12 is a convergence signal indicating that the echo canceller has converged.

13は減算回路4の出力をエコーキャンセラ2に入力す
るスイッチである。
13 is a switch for inputting the output of the subtraction circuit 4 to the echo canceller 2;

まず、エコーキャンセラの動作について説明する。スイ
ッチ3はハイブリット回路側に、スイッチ7は検波回路
側に接続し、スイッチ13を閉じる。送信信号路9から
送られた信号は)・イブリッド回路1の擬似線路インピ
ーダンスと、実際の線路インピーダンスの不整合によっ
て受信信号路11にエコー信号として回り込む。一方、
エコーキャ/セ:72は送信信号と予測係数を用いて凝
似エコ−信号を作り出し減算回路4に入力する。減算回
路4の出力はエコー信号と疑似エコー信号の差で残留エ
コー信号と呼ばれ、エコーキャンセラ2と検波回路5に
入力される。エコーキャンセラは残留エコー信号が小さ
くなるように予測係数を増減し、残留エコー信号があら
かじめ決められた値よシ小さくなると収束したとみなし
て収束信号12を出力する。
First, the operation of the echo canceller will be explained. Switch 3 is connected to the hybrid circuit side, switch 7 is connected to the detection circuit side, and switch 13 is closed. The signal sent from the transmission signal path 9 loops around into the reception signal path 11 as an echo signal due to the mismatch between the pseudo line impedance of the hybrid circuit 1 and the actual line impedance. on the other hand,
The echo signal generator 72 generates a simulated echo signal using the transmission signal and the prediction coefficient and inputs it to the subtraction circuit 4. The output of the subtraction circuit 4 is the difference between the echo signal and the pseudo echo signal, which is called a residual echo signal, and is input to the echo canceller 2 and the detection circuit 5. The echo canceller increases or decreases the prediction coefficient so that the residual echo signal becomes smaller, and when the residual echo signal becomes smaller than a predetermined value, it is considered that convergence has occurred and outputs a convergence signal 12.

次に、ループバックモードに設定する。スイッチ3を接
地レベルに、スイッチ7をビット反転回路6に接続する
。またスイッチ13を用いて予測係数を固定する。この
時、エコーキャンセラで作られた疑似エコー信号は減算
回路4に入力され、検波回路5には反転された疑似エコ
ー信号が入力される。一般に、エコー信号レベルは送信
信号レベルの−10−20dBでそれ自身で十分検波可
能である。検波回路で検波2値化された疑似エコー信号
はビット反転回路6でビット反転され、インタフェース
部8に入力される。インタフェース部では、送信信号と
受信された疑似エコー信号を比較し、等しければエコー
キャンセラが正常動作していると判断してループバック
を終了し各スイッチ3,7.13 を切換えて通常の動
作状態に戻る。
Next, set it to loopback mode. Switch 3 is connected to ground level, and switch 7 is connected to bit inversion circuit 6. Further, a switch 13 is used to fix the prediction coefficient. At this time, the pseudo echo signal produced by the echo canceller is input to the subtraction circuit 4, and the inverted pseudo echo signal is input to the detection circuit 5. Generally, the echo signal level can be detected sufficiently by itself at -10 to 20 dB of the transmitted signal level. The pseudo echo signal detected and binarized by the detection circuit is bit-inverted by a bit inversion circuit 6, and is input to an interface section 8. The interface unit compares the transmitted signal and the received pseudo-echo signal, and if they are equal, it is determined that the echo canceller is operating normally, ends the loopback, and switches each switch 3, 7, and 13 to return to the normal operating state. Return to

第2図は本発明の他の実施例を示すブロック図である。FIG. 2 is a block diagram showing another embodiment of the invention.

第1図と同じ機能のものは同一の番号で示す。14は検
波回路5の入力をエコーキャンセラ出力と減算回路出力
のいずれかに切換えるスイッチである。
Components with the same functions as in FIG. 1 are designated by the same numbers. 14 is a switch for switching the input of the detection circuit 5 to either the echo canceller output or the subtraction circuit output.

エコーキャンセラの収束手順は第1図の実施例と同じで
ある。エコーキャンセラが収束した後、スイッチ14を
切換えてエコーキャンセラ出力と検波回路の入力とを接
続する。またスイッチ13を開いて予測係数を固定する
。この時、疑似エコー信号は直接検波回路に人力され、
2値化された後にインタフェース部へ入力される。した
がって第1図の実施例におけるビット反転回路とスイッ
チ1コが不要となる。
The convergence procedure of the echo canceller is the same as the embodiment of FIG. After the echo canceller converges, the switch 14 is switched to connect the echo canceller output and the input of the detection circuit. Further, the switch 13 is opened to fix the prediction coefficient. At this time, the pseudo echo signal is directly input to the detection circuit,
After being binarized, it is input to the interface section. Therefore, the bit inverting circuit and one switch in the embodiment of FIG. 1 are not required.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、エコーキャンセラーの
ループバックモード時に、疑似エコーのみを検波するこ
とによってエコーキャンセラの正常動作を確認すること
ができるため、通信不能時にエコーキャンセラの故障で
あるか、線路の断縁であるかを確実に判断することがで
きる効果がある。
As explained above, the present invention makes it possible to confirm the normal operation of the echo canceller by detecting only pseudo echoes when the echo canceller is in the loopback mode. This has the effect of making it possible to reliably determine whether the line is broken.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示すブロック図、第2図は本
発明の他の実施例を示すブロック図、第3図は第1の従
来例を示すブロック図、第4図は第2の従来例を示すブ
ロック図である。 1・・・・・・2線74線変換ハイブリット回路、2・
・・・・・エコーキャンセラー、3,7,13,14.
15・・・・・・スイッチ、4・・・・−・減算回路、
5・・・・・・検波回路、6・・・・・・ビット反転回
路、8・・・・・・インタフェース部、9・・・・・・
送信信号路、10・・・・・・2線信号路、工1・・・
・・・受信信号路、12・・・・・・収束信号。
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing another embodiment of the invention, Fig. 3 is a block diagram showing a first conventional example, and Fig. 4 is a block diagram showing a second conventional example. FIG. 2 is a block diagram showing a conventional example. 1...2 wire 74 wire conversion hybrid circuit, 2.
...Echo canceller, 3, 7, 13, 14.
15...Switch, 4...--Subtraction circuit,
5...Detection circuit, 6...Bit inversion circuit, 8...Interface section, 9...
Transmission signal path, 10...2-wire signal path, engineering 1...
... Reception signal path, 12 ... Convergence signal.

Claims (3)

【特許請求の範囲】[Claims] (1)2線式伝送路と送信および受信信号路をもつ4線
式伝送路とを接続するハイブリット回路と、前記送信信
号路の信号を受けるエコーキャンセラ回路と、該エコキ
ャンセラ回路の出力と前記受信信号路の信号とを減算す
る減算回路と、該減算回路の出力で前記エコーキャンセ
ラ回路の出力を調節する手段と、前記減算回路の出力を
検波する検波回路とを含み、前記エコーキャンセラの出
力を調節する手段によって前記エコーキャンセラーの出
力を固定するとともに前記検波回路に前記エコーキャン
セラ回路の出力のみを直接又は減算器を介して加えるよ
うに切りかえる切り換え回路を有することを特徴とする
エコーキャンセラー方式2線4線変換回路。
(1) A hybrid circuit that connects a two-wire transmission path and a four-wire transmission path having transmitting and receiving signal paths, an echo canceller circuit that receives the signal of the transmitting signal path, and an output of the echo canceller circuit and the a subtraction circuit for subtracting a signal on a reception signal path; means for adjusting the output of the echo canceller circuit with the output of the subtraction circuit; and a detection circuit for detecting the output of the subtraction circuit; An echo canceller method 2 characterized in that it has a switching circuit that fixes the output of the echo canceller by adjusting the output of the echo canceller and adds only the output of the echo canceller circuit to the detection circuit directly or via a subtracter. 4-wire conversion circuit.
(2)前記切り換え回路は前記エコーキャンセラ回路の
出力のみを前記減算器に加えるとともに、前記検波回路
の出力を反転するように動作することを特徴とする特許
請求の範囲第1項記載のエコーキャンセラー方式2線4
線変換回路。
(2) The echo canceller according to claim 1, wherein the switching circuit operates to apply only the output of the echo canceller circuit to the subtracter and to invert the output of the detection circuit. Method 2 wire 4
Line conversion circuit.
(3)前記切り換え回路は前記エコーキャンセラ回路の
出力のみを前記検波回路に直接加えるように動作するこ
とを特徴とする特許請求の範囲第1項記載のエコーキャ
ンセラー方式2線4線変換回路。
(3) The echo canceller type two-line and four-line conversion circuit according to claim 1, wherein the switching circuit operates so as to directly apply only the output of the echo canceller circuit to the detection circuit.
JP15575687A 1987-06-22 1987-06-22 Echo canceler type 2-wire/4-wire canceler Pending JPS63318822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15575687A JPS63318822A (en) 1987-06-22 1987-06-22 Echo canceler type 2-wire/4-wire canceler

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15575687A JPS63318822A (en) 1987-06-22 1987-06-22 Echo canceler type 2-wire/4-wire canceler

Publications (1)

Publication Number Publication Date
JPS63318822A true JPS63318822A (en) 1988-12-27

Family

ID=15612726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15575687A Pending JPS63318822A (en) 1987-06-22 1987-06-22 Echo canceler type 2-wire/4-wire canceler

Country Status (1)

Country Link
JP (1) JPS63318822A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172411A (en) * 1990-03-27 1992-12-15 Siemens Aktiengesellschaft Two-wire/four-wire converter
US5175763A (en) * 1990-03-27 1992-12-29 Siemens Aktiengesellschaft Two-wire/four-wire converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172411A (en) * 1990-03-27 1992-12-15 Siemens Aktiengesellschaft Two-wire/four-wire converter
US5175763A (en) * 1990-03-27 1992-12-29 Siemens Aktiengesellschaft Two-wire/four-wire converter

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