JPS63317983A - Defect detection circuit for magnetic disk device - Google Patents

Abstract

PURPOSE:To attain sure data write/readout by detecting a defect caused later in a magnetic disk device using a data face servo system and informing the location of the defect caused later to a host circuit. CONSTITUTION:When a host circuit makes a start signal (b) active, a controller circuit 1 makes a count start signal (c) active. When the signal (c) is made active, a counter circuit 7 starts counting a reference clock (a). If a defect exists and a voltage difference signal (m) is active, the circuit 1 makes a defect signal (n) active to inform the presence of the defect to the host circuit and the circuit 1 outputs a write signal as a memory signal (o). When the write signal is outputted as the signal (o), a location signal being an output of the circuit 7 at that point of time, that is, a signal (r) representing the relative location of defect is stored in an address represented in the signal (o) by a memory circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a magnetic disk device having a function of detecting defects in a magnetic disk medium when using a data surface servo method.

(Prior art) Conventionally, magnetic disk drives using the data surface servo method write servo information on the entire surface of the magnetic disk medium during manufacture, inspect defective areas, and then store information about the defective areas in the magnetic disk drive. The user takes this defect information into consideration when formatting, and performs all data writing and reading.

(The problem to be solved by the invention) Conventional magnetic disk drives perform formatting by fully utilizing only the defect information created during manufacturing. Even if a late-onset defect was created due to such factors, information regarding the late-onset defect was not included. Therefore, since formatting is performed without taking late defects into consideration, there is a drawback that formatting completely fails and data cannot be written or read.

SUMMARY OF THE INVENTION An object of the present invention is to provide a defect detection circuit for a magnetic disk device that can perform formatting taking late-occurrence defects into consideration, thereby ensuring reliable data writing and data extraction.

(Means for Solving the Problems) In order to achieve the above object, a defect detection circuit for a magnetic disk drive according to the present invention provides a defect detection circuit for a magnetic disk drive that employs a data surface servo method. and a plurality of FV converter circuits that output voltages proportional to the frequencies of the pulse signals from each of the lead PLO circuits.

There is a defect in the comparator circuit that compares the outputs of the plurality of FV converters and outputs a voltage difference signal when there is a % voltage difference, and the counter circuit that starts counting the reference clock signal based on the start signal and outputs all position signals. A controller that sends a defect signal to the host device, outputs a write signal, and also outputs a read signal when it receives a voltage difference signal.
an o-ra circuit, and a memory circuit that, when receiving the write signal, stores a device signal constituted by a counter circuit at that time, reads out a position signal based on the read signal, and sends it to the host device. It is configured.

(Example) Next, the present invention will be explained with reference to all the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention in blocks. First, I will explain the connection.

The controller circuit 1 is connected to a higher level circuit (not shown) by a start signal b1, a comparison start signal d, a read signal p, a reference clock signal a and a defect signal n, and is connected to a comparator circuit 2 by a voltage difference signal m.

The comparator circuit 2 is connected to the controller circuit 1 by the comparator start signal f, and the FV is connected to the PLO voltage signal.
Connected to converter circuit wr3, and also PLO voltage signal! and is connected to the FV converter circuit 4.

The FV converter circuit 3 is connected to the lead PLO circuit 5 by a PLO signal i.

The F■ converter circuit 4 is connected to the lead PLO circuit 6 via the PLO signal j.

The read PLO circuit 5 is connected to a lower circuit (not shown) by a low read pulse signal g, and is connected to the controller circuit 1 by a PLO start signal e.

The read PLO circuit 6 is connected to a lower circuit (not shown) by a low read pulse signal, and is connected to the controller circuit 1 by a PLO start signal e.

The counter circuit 7 is connected to the above-mentioned upper circuit using the reference clock signal a, and is connected to the controller circuit 1 using the count start signal C.

Memory times %8 is connected to the counter circuit 7 by the position signal r, connected to the controller circuit 1 by the memory signal 0, and connected to the above-mentioned upper circuit by the defective position signal q.

Next, the operation will be explained.

When the upper circuit activates the comparison start signal d,
The controller circuit 1 activates the PLO start signal e. When the PLO start signal e becomes active, the read PLO circuit 5 starts following the constant track low read pulse signal g output from the lower circuit. Similarly, the read PLO circuit 6 starts following the low read pulse signal of another track output from the lower circuit. Further, the read PLO circuit 5 outputs a pulse signal synchronized with the low read pulse signal g as a PI, 0 signal t.

Similarly, the read PLO circuit 6 also outputs a pulse signal '((PLO signal j) synchronized with the low read pulse signal.

The FV converter circuit 3 outputs a voltage proportional to the PLO signal station wave number as a PLO voltage signal, and similarly, the FV converter circuit 4 outputs a voltage proportional to the PLO signal station wave number as a PL (J [pressure signal 1). .

Next, when the read PLO circuit 5 and the read PLO circuit 6 complete tracking, the controller circuit 1 activates the comparator start signal f.

When the comparator and start signal f become active, the comparator times w! r2 compares the PLO voltage signal and the PLO voltage signal 2, and if there is a difference in voltage, makes the voltage difference signal m active, and if there is no difference in voltage, makes the voltage difference signal mf inactive.

That is, when there is no defect, PLO signal 1 and P
LO signal signal station 1 frequency, PLO'll pressure signal k
(!: Since the PLO voltage signals are at the same voltage, the voltage difference signal m is inactive. Also, when a defect exists, the PLO signal signal station wave number changes,
As a result, a voltage difference occurs between the PLOII pressure signal and the PI, 0% pressure signal, so the voltage difference signal m becomes active.

When the upper circuit activates the start signal S, the controller circuit 1 activates the count start signal ci. When count start signal C becomes active,
The counter circuit 7 starts counting the reference clock a.

When a defect exists and the voltage difference signal m becomes active,
The controller circuit 1 notifies the higher-level circuit of the existence of a defect by activating the defect signal n, and
The controller circuit 1 outputs a write signal to the memory signal O.

When the write signal is output as the memory signal O, the memory circuit 8 outputs the position signal r (i.e., the signal indicating the relative position of the defect), which is the output value of the counter circuit 7 at that time, as the memory signal O. Store to the indicated address.

The above operation is performed every time the voltage difference signal m becomes active (
Repeat each time a defect exists. That is, the position of the defective portion expressed by the count value of the reference clock a is stored in the memory circuit 8.

When the upper circuit outputs a signal as a read signal p, the controller circuit 1 outputs a read signal as a memory signal O.

When the readout signal is output as the memory signal O, the memory circuit 8 outputs the data at the address indicated by the memory signal 0 (i.e., the defect position)'t-defect position signal, and outputs the data to the upper circuit (not shown). Send to.

(Effects of the Invention) As explained above, the present invention is configured to detect a late defect in a magnetic disk device using a data surface servo system and to communicate the position of the late defect to the upper circuit. The upper circuit can perform formatting in consideration of late defects based on the information sent from the present invention.
This has the effect that writing and reading of data can be performed reliably.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing, in block form, an embodiment of a defect detection circuit for a magnetic disk drive according to the present invention. 1... Controller circuit 2... Comparator circuit 3.4... FV converter circuit 5.6... Read PLO circuit 7... Counter circuit 8... Memory circuit

Claims (1)

[Claims] In a magnetic disk device that uses a data surface servo system, multiple lead PLs each output a pulse signal synchronized with a signal from a different track sent from a lower circuit.
O circuit, a plurality of FV converter circuits that output a voltage proportional to the frequency of each pulse signal from each lead PLO circuit, and the plurality of FV converter outputs are compared, and when there is a voltage difference, a voltage difference signal is output. a comparator circuit that starts counting the reference clock signal in response to a start signal and outputs a position signal; and a counter circuit that starts counting the reference clock signal in response to a start signal and outputs a position signal. a controller circuit that outputs a read signal and a read signal; and a controller circuit that stores a position signal output from a counter circuit when receiving the write signal, and outputs a position signal using the read signal. 1. A defect detection circuit for a magnetic disk device, comprising a memory circuit for reading data and sending data to a host device.