JPS63317859A - Control system for buffer storage way - Google Patents

Abstract

PURPOSE:To reduce the capacity of a buffer storage by using the encoding signal for comparison result of a tag part as a way reading address of the buffer storage. CONSTITUTION:The tag parts 2 corresponding to the ways 0-n of a buffer storage BS1 are retrieved by the values of the low-order bits (tag addresses) of a main memory address set at an MS address register 20. Then a comparator 21 performs comparison of high-order bits of a register 20. In case a block containing the data that gave an access to the BS1 exists (hit), the coincident output signal of the comparator 21 is encoded by an encoder 22. Then an encoding signal (1) is set at a part of a BS address register 23 together with the low-order bits of the register 20. Thus data are read out of the BS1. In such a constitution, no memory element is required for each way and a compact buffer register is obtained.

Description

[Detailed Description of the Invention] [Summary] (1) In a data processing device equipped with a pamphlet storage (BS) that stores a copy of a part of a storage device, a value ■ obtained by encoding a search result of a tag part is By providing a buffer storage (BS) address register for temporary storage, way data can be held in the address direction of the buffer storage (BS).

(2) In the buffer storage way control method described in (1), the way whose LRU is the latest is predicted and read at the same time as the tag section is searched, and set as part of the buffer storage (BS) address register described above. By providing a means to read the latest way indicated by the LRU in advance, and when the latest way indicated by the LRU and the search result of the tag section match, the data of the pre-read way is used. This is what I did.

[Industrial application field]

The present invention relates to a buffer storage way control method in a data processing device equipped with a buffer storage that stores a copy of a portion of a storage device.

With the recent remarkable progress in semiconductor technology, the main memory (
MS) is moving toward larger capacity, and central processing units (
Control devices such as CPUs are becoming faster and the speed difference is widening, and as a measure to absorb this speed difference, for example, relatively large capacity and medium speed global buffer storage (CBS) )and.

Fast but small local buffer storage (
A so-called two-layer cache memory system is increasingly being adopted.

On the other hand, in medium-sized computer systems, there is a strong demand for miniaturization of the entire system due to increased speed and economic efficiency.
CBS), etc., miniaturization is an essential condition.

However, while the tag section of the cache memory has a relatively small capacity, the data section has a large capacity as described above, so it is necessary to downsize the data section.

[Prior art and problems to be solved by the invention] Fig. 3 is a diagram explaining a conventional buffer storage way control system, in which (a) shows an example of the overall configuration, and (b) shows an operation time chart. It shows.

As mentioned above, in a high-speed data processing device, a copy of the main memory (MS) is stored at high speed in a small-capacity memory, that is, a buffer storage (hereinafter referred to as BS). It is a common technique to adopt a so-called cache memory method, which apparently aims to improve the access time for (MS).

Normally, in order to improve its effectiveness, the BS consists of a plurality of BS ways (0 to n) 1, as shown in this figure, and simultaneously reads out the plurality of BS ways (0 to n) 1. I do.

At the same time, the tag section (0-n) 2 corresponding to each way is searched, and comparators (0-n) are used to determine which way has a copy of the block to be accessed in the main memory if (MS).
Based on the matching signal of the comparator (0 to n) 21, data from each BS way (0 to n) 1 is selected and read out by the selection circuit 11.

(Refer to the time chart in figure (b)) Therefore, separate memory elements are required for the number of BSO ways (0 to n) 1, leading to an increase in the number of parts. There were problems that hindered the miniaturization of computer systems.

In view of the above conventional drawbacks, the present invention provides a computer system equipped with a buffer storage (BS) consisting of a plurality of ways, which has a relatively large capacity.
It is an object of this invention to provide a method of downsizing the buffer storage (BS) and increasing the speed by storing data of each way of S) in the address direction.

[Means for solving problems]

FIG. 1 is a diagram showing an example of the configuration of a buffer storage way control method according to the present invention.

In the present invention, (1) In a data processing device equipped with a buffer storage (BS) 1 that stores a copy of a part of the storage device, the encoded signal ■ of the comparison result of the tag section 2 is sent to the buffer storage described above. (BS) Configure so that way 1 is used as part of the read address.

(2) The encoded signal ■ of the comparison result of the tag part 2,
In the method of using the buffer storage (BS) 10 ways as part of the read address, LRU 28
Register 2 predicts the hitway from the value of and holds it.
5, and a means 26 for comparing the search result in the tag unit 2 and the hitway prediction result, and when the comparison result matches, the predicted way address ■ is stored in the buffer storage (BS) 1. The buffer storage (BS) 1 is read using the ways of the tag part 2 as part of the read address, and if the above comparison results do not match, the encoded signal ■ of the comparison result of the tag section 2 is read out from the buffer storage (BS) 1. BS) Configure so that way 1 is used as part of the read address.

[Operation] That is, according to the present invention, (1) In a data processing device equipped with a buffer storage (BS) that stores a copy of a part of a storage device, a value ■ that is an encoded result of a search in a tag section is encoded. By providing a buffer storage (BS) address register for temporary storage, way data is provided in the address direction of the buffer storage.

(2) In the buffer storage way control method described in (1), the way whose LRU is the latest is predicted and read at the same time as the tag section is searched, and set as part of the buffer storage (BS) address register described above. By providing a means to read the latest way indicated by the LRU in advance, and when the latest way indicated by the LRU and the search result of the tag section match, the data of the pre-read way is used. This is what I did.

Therefore, as in the past, a memory element for each way is no longer required, and the buffer storage (BS) can be made smaller.The latest way with a high hit rate can be predicted and the buffer storage (BS) ) has the effect of increasing speed.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing an example of the configuration of the buffer storage way control method of the present invention, where (a) shows an example of the basic configuration, and (b) shows how LRυ is used to select a buffer storage way. By logic, predict the latest way,
An example of reading out in advance is shown, and FIG. 2 is a time chart of the way selection operation according to the present invention, in which (a)
, (b) correspond to (a) and (b) in FIG. 1, and the encoder 22 . BS address register 23. and read way prediction circuit 24. Prediction way register 25. Comparator 26, selection gate circuit 27
are necessary and means for carrying out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the buffer storage way control method of the present invention will be explained with reference to FIGS. 1 and 2.

First, the basic operation of the buffer storage way control system of the present invention will be explained with reference to FIGS. 1 and 2(a).

In FIG. 1(a), from a processing device not shown,
Depending on the value of the lower bits (tag address) of the main memory address set in the MS address register 20, the BS
Tag part (0 to n) corresponding to each way (0 to n) of 1
2 is searched, and the comparator (0 to n) 21 compares it with the upper bits (comparison address) of the MS address register 20. (Refer to cycle 1.2 of the time chart in Figure 2 (a)) Here, if there is no address that corresponds to the tag part (0 to n) 2, it is considered a hit error and the address is not shown. A data block containing the relevant data is moved in from the main memory (MS) and registered in an empty block of BS1. At this time, if there is no free block in the BS 1, the oldest way is searched for using the known LRU mechanism 28, 29, and the move-in data is registered in the acid way.

If the tag part (0 to n) 2 contents (tag address)
matches the comparison address which is the upper bit of the MS address register 20, that is, if there is a block containing data accessed to BS 1 (hit), the comparator (0 to n) 21 The coincidence output signal of is encoded by the encoder 22, and the encoded signal {circle around (2)} is encoded along with the lower bits of the MS address register 20 as part of the BS address register 23 of the present invention (for example,
(lowest, highest, etc.). (Figure 2 (a)
)) Next, in cycle 3.4 shown in FIG. 2(a),
A read operation for BS l is performed and in cycle 4 the read data is passed to the processing unit.

As a result, the number of cycles for accessing BS 1 increases by one compared to the conventional method shown in the time chart of FIG. 3(b), but unlike the aforementioned global buffer storage (CBS), If the tag search time is short compared to the BS read time, this increase in the number of cycles is hardly a problem.

Furthermore, if the value of the old address register 20 is held in cycle 3.4 shown in FIG. can be read,
The number of bits of the BS address register 23 can also be reduced.

Next, as shown in FIG. 1 and FIG. 2(b), in the buffer storage control method of the present invention, the LRU logic is used to select the way of the buffer storage (BS).
An example of predicting the latest way and reading it in advance will be described.

First, in FIG. 1(b), the tag part (
0 to n) 2 and is compared with the upper bits (comparison address) of the MS address register 20 by the comparator (0 to n) 21. (See cycle 1.2 in FIG. 2(b)) In the cycle 1, the known LRU 28 is simultaneously read out, the read way prediction circuit 24 examines the latest way B
It is set in a part of the S address register 23 (the highest or lowest position, in this example, the lowest position).

Further, the output (2) of the read way prediction circuit 24 is stored in the prediction way register 25, and in cycle 2, the comparator 26 compares it with the search result of the tag unit 2.

If a match signal is obtained in this comparison operation, the read result of the buffer storage (BS) obtained in cycle 3 is sent to the processing device. (Refer to FIG. 2(b)(a)) However, if there is a mismatch in the above comparison operation, in cycle 2, the signal ■ The value of
BS address register 23 via selection gate circuit 27
The buffer storage (BS) 1 is reset to a part (for example, the lowest position) of the buffer storage (BS) 1 and read from the buffer storage (BS) 1 again.

Therefore, the read data of the buffer storage (BS) 2 in this case is obtained in cycle 4. (See Figure 2 (b) (b)) As mentioned above, by prediction using the well-known LRU logic, the way that hits the buffer storage (BS) 1 (the latest way) ■
By predicting and reading out the address, it is possible to increase the probability that the prediction will be correct, considering the locality of the address distribution.

As described above, the present invention provides, in a processing device equipped with a buffer storage (BS) consisting of a plurality of ways, the encoded result of the search result of the tag section as part of the address register of the buffer storage (BS). The buffer storage (BS) is configured to be read out, and the way data is held in the direction of the address, and
Using the known LRU mechanism, predict the latest way,
The acid way address is pre-read from the buffer storage (BS) as part of the address register, and if the search result of the tag section matches the prediction result, the pre-read is performed. The feature is that way data is used.

[Effects of the Invention] As explained above in detail, the buffer storage way control method of the present invention provides: (1) a data processing device equipped with a buffer storage (BS) storing a copy of a part of a storage device; In this method, a buffer storage (BS) address register is provided to temporarily store the value (2) obtained by encoding the search result of the tag section, so that way data is provided in the address direction of the buffer storage.

(2) In the buffer storage way control method described in (1), the way whose LRU is the latest is predicted and read at the same time as the tag section is searched, and set as part of the buffer storage (BS) address register described above. By providing a means to read the latest way indicated by the LRU in advance, and when the latest way indicated by the LRU and the search result of the tag section match, the data of the pre-read way is used. This is what I did.

Therefore, as in the past, a memory element for each way is no longer required, and the buffer storage (BS) can be made smaller.The latest way with a high hit rate can be predicted and the buffer storage (BS) ) has the effect of increasing speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a buffer storage way control method according to the present invention. FIG. 2 is a time chart of way selection operation according to the present invention. FIG. 3 is a diagram explaining a conventional buffer storage way control method. It is. In the drawing, 1 is buffer storage (IIS). 11 is a selection circuit; 2 is a tag unit (0 to nL; 21 is a comparator (0 to n); 22 is an encoder; 23 is a BS address register; 24 is a read way prediction circuit; 25 is a prediction way register; 26 is a comparator; 28 is LI?U. 27 is a selection gate circuit. 29 is a replace way control circuit. ■ is an encode signal. ■ is a predicted way address, the latest way, or a hit way.

Claims (2)

[Claims] (1) In a data processing device equipped with a buffer storage (1) that stores a copy of a part of the storage device, the encoded signal ([1]) of the comparison result of the tag section (2) is sent to the buffer storage ( A buffer storage way control method characterized in that the way of 1) is used as a part of the read address. (2) The encoded signal of the comparison result of the tag part (2) (
[1]) is used as a part of the address for reading the way of the buffer storage (1), which includes: a register (25) that predicts ([2]) the hit way from the LRU value and holds it; and a tag section. Means (26) is provided for comparing the search result in (2) with the hit way prediction result, and if the comparison results match, the predicted way address is transferred to the hit way prediction result in the buffer storage (1). is used as part of the read address to read out the buffer storage (1), and if the above comparison results do not match, the tag part (2
) The buffer according to claim 1, wherein the encoded signal ([1]) of the comparison result of the buffer storage (1) is controlled to be used as a part of the address for reading out the way of the buffer storage (1). Storage way control method.