JPS633164U - - Google Patents
Info
- Publication number
- JPS633164U JPS633164U JP1986096253U JP9625386U JPS633164U JP S633164 U JPS633164 U JP S633164U JP 1986096253 U JP1986096253 U JP 1986096253U JP 9625386 U JP9625386 U JP 9625386U JP S633164 U JPS633164 U JP S633164U
- Authority
- JP
- Japan
- Prior art keywords
- fuse pattern
- programmable array
- array logic
- processing device
- display screen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986096253U JPS633164U (pt) | 1986-06-24 | 1986-06-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986096253U JPS633164U (pt) | 1986-06-24 | 1986-06-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS633164U true JPS633164U (pt) | 1988-01-11 |
Family
ID=30961787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986096253U Pending JPS633164U (pt) | 1986-06-24 | 1986-06-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS633164U (pt) |
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1986
- 1986-06-24 JP JP1986096253U patent/JPS633164U/ja active Pending