JPS63316131A - Data processor - Google Patents

Abstract

PURPOSE:To prevent a dead clock state from being generated, by holding a branch destination address in a saving register transiently when no vacant instruction buffer which stores plural instructions based on the branching destination addresses exists. CONSTITUTION:In a data processor which pre-reads an instruction sequence and associates and outputs the branching destination address of a branching instruction in the instruction sequence, busy flags 1010-1030 go to 1 when no vacant instruction buffers 1002-1006 which store the plural instructions based on the branching destination addresses exist. Simultaneously, when a signal BrInst goes to an L at the time of decoding the branching instruction in which no hit of branching destination associative storage is performed, a holding instruction is outputted from instruction buffer control combination logic 1056, and the address of a following branching instruction is held at the saving register transiently, and the dead lock state where decoding is impossible due to the lack of the instruction buffer can be prevented from being generated. Also, similarly, the cancel of transient holding can be performed via the logic 1056.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and particularly to a data processing device that processes instructions including branch instructions.

[Conventional technology]

One of the things that speeds up the processing of branch instructions is branch destination associative memory. This is to input a prefetch address when prefetching an instruction string, and associatively output the branch destination address of a branch instruction (if any) included in the prefetched instruction string.

The branch destination associative memory associatively outputs the branch destination address (b
In the case (it), there is a branch instruction in the instruction string to be prefetched, and the next branch instruction is predicted to branch to the branch destination address output by the one-branch destination content addressable memory. At this time, when prefetching the next instruction, the processing of one branch instruction is sped up by prefetching the branch destination instruction string pointed to by this branch destination address instead of the instruction string immediately after the instruction string that has just been prefetched. Ru.

If the branch destination associative memory does not associatively output the branch destination address (nobit), there is no branch instruction in the prefetched instruction sequence, or even if there is, the branch instruction is expected not to branch. Ru. At this time, instruction prefetching is performed for the instruction immediately following the currently prefetched instruction sequence.

This technique is used, for example, in Computer Journal 15
(1972) pp. 42-50 (R,N, Ibbett.

The MU5 1nstruction pip
eline, The Computer Jout
nal 15) Feb, 1972), 42 50
)It is described in.

[Problem 3 that the invention seeks to solve Problems may occur when using branch destination associative memory.

Consider a case where there are three instruction buffers.

The instruction buffer normally uses one side to prefetch instructions. The prefetched instructions are sequentially read out from the instruction buffer and decoded. When an instruction of more than a certain number of bytes is decoded, a subsequent instruction is prefetched into an empty area (the area where the decoded instruction was located), so that instructions can always be prefetched.

When a branch instruction appears during instruction decoding, the branch destination instruction is stored in an instruction buffer different (in a different plane) from the instruction buffer in which the branch instruction was stored.

Even when the branch destination associative memory outputs a branch destination address, the instruction at one branch destination is stored in an instruction buffer different from the instruction buffer in which the branch instruction was stored.

When a branch instruction appears, multiple instruction buffers are temporarily used. However, when a decision is made regarding a 1-branch instruction, unnecessary instruction buffers are released. When the branch is not taken, the instruction buffer in which the branch destination instruction was stored is released, and when the branch is taken, the instruction buffer in which the branch instruction was stored is released. The freed instruction buffer is then used to store the branch target instruction when the branch instruction occurs.

A problem occurs with the instruction sequence shown in Figure 4.6 In Figure 4,
Branch instructions (B
Suppose that there is a command r), and one of the three instruction buffers is used to read ahead an instruction. 100 to 107
Assume that an instruction sequence at an address is prefetched and stored in the instruction buffer.

At this time, the branch destination associative memory is set to no bit. In other words, the 0 branch destination associative memory, which is expected to have no branch instruction in this instruction string, has no bit.
Next, the instruction string at address 108 and address 10F is prefetched and stored in the same empty part of the instruction buffer as above.

At this time, when prefetching the instruction sequence, the branch destination associative memory is bi
Suppose it becomes t. In other words, it is predicted that there is a branch instruction to branch in this instruction sequence.If the 0 branch destination associative memory outputs 200, the 0 branch destination associative memory is b.
Therefore, next, instead of the instruction sequence from addresses 110 to 117, the instruction sequence from addresses 200 to 207 is prefetched, which is different from the instruction buffer in which the instruction sequence from addresses 100 to 10F is stored. The instruction sequence from addresses 200 to 207 is stored in the instruction buffer.

At this time, that is, when the instruction sequence from address 200 to address 207 is prefetched, the branch destination associative memory is set to bits, and 52
Suppose that 0 is output. Since the branch destination associative memory is bit, it is 1
Next, the instruction sequence from address 520 to address 527 is prefetched,
It is stored in an instruction buffer different from the two-sided instruction buffer described above.

Now, assume that the instruction decoding from address 100 is progressing with all three instruction buffers in use. Then, the branch instruction at address 104 is decoded, but in order to complete the decoding of this branch instruction, an instruction buffer is required to store the instruction string of the branch destination of this branch instruction as a look-ahead. However, all three planes of instruction buffers are in use. Therefore, decoding of this branch instruction cannot be started, and in that case, decoding of the subsequent branch instructions at addresses 204 and 520 cannot be started either.

The determination of the branch instruction at address 520 is also not completed, and none of the three instruction buffers are released.

Therefore, decoding of the branch instruction at address 104 will not be completed forever, resulting in a deadlock state. This is a problem.

The purpose of the invention is to avoid this deadlock situation.

[Means for solving problems]

The above objective can be achieved as follows.

That is, it has one or more instruction buffers that prefetch and store one or more instructions before decoding and executing the instruction, stores the branch destination address of the branch instruction, and stores the branch destination address of the branch instruction before decoding and executing the branch instruction. a branch destination associative memory that outputs the branch destination address when it is predicted that there is a branch instruction to branch;
In a data processing device having a means for reading out one or more instructions at a branch destination based on a branch destination address outputted by the branch destination associative memory and storing it in an instruction buffer, a temporary save register is provided, when a branch instruction is read ahead.

If the above branch destination associative memory does not output the branch destination address, but all instruction buffers are in use when the instruction is found to be a branch instruction when decoding, the branch destination of the above branch instruction means for holding the address in the temporary save register and decoding the instruction subsequent to the branch instruction, and when the instruction buffer that was in use becomes unused;
It is sufficient to provide means for reading out a branch destination instruction sequence based on the branch destination address held in the temporary save register and storing it in the unused instruction buffer.

[Effect]

By newly providing the above means, when the branch instruction at address 104 mentioned in [Problems to be Solved by the Invention] is decoded, the branch destination address of this branch instruction is held in the temporary save register, Since the decoding of this branch instruction is completed and the subsequent instructions are decoded, there is no deadlock condition.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 6.

Figure 1 is a block diagram of the advance control device, Figure 2 is a diagram of the overall configuration,
FIG. 3 is a block diagram of a branch target associative memory, FIG. 4 is an example of an instruction sequence, and FIG. 5 is a block diagram of an instruction buffer control circuit combinational logic.
FIG. 6 is a time chart.

First, the overall configuration will be explained using FIG. 2.

The whole consists of the following four parts.

(1) Advance control bag [(2002): Advance reading of instructions), decoding of instruction word, calculation of address of memory referred to by instruction, activation of memory reference to main memory, activation of arithmetic unit 2 branch destination association Details of 6 for activating storage will be described later using FIG.

(2) Arithmetic device (2006): Started by the preceding control device to perform arithmetic operations. The signal line 20 is used for activation from the preceding control device.
22. When the activated instruction is a branch instruction, additional information is sent via the IBR# and DC# signals.

When a branch instruction is activated, the TKN signal line (when the judgment is true) or the NIKN signal line (when the judgment is not true) depends on the judgment result.
is set, and at that time, the additional information sent via the IBR# and DC# signal lines remains as IBR#'.

It is sent back on the DC#' signal line. Details of IBR# and DC# will be described later. Necessary memory data is main memory (2004)
Sent from. Since the interface related to data transfer from main memory is not directly related to the embodiments of the present invention,
It is only written as signal JQ2030.

(3) Main memory (2004): A memory that stores instructions and data. IFA signal line 2010. TA Shin% line 201
2. PTA'C'? When an address is sent from line 2016, a command string (8 bytes) from that address to address +7 is sent to IDATA signal line 2018. All command words are 4 bytes. Therefore, two commands are sent. At the time of sending.

TBR# when address is sent, IBRQ signal B20
TBR the value of 14 and the value of HT multiplied signal 2032 as is.
#', IBRIl', and HT' signal lines 2020. Since reference to data is not relevant to the description of the embodiment, only the signal line 2030 will be described as the data-related interface with the arithmetic unit.

(4) Branch destination associative memory (2000): This is an associative memory that stores a set of a branch instruction address and a branch destination address. Details will be described later using FIG. 3.

Next, the internal configuration of the advance control device will be explained using FIG.

1002, 1004, 1006 are three-sided instruction buffers (
3 sides x 16 bytes). The instruction buffer of each plane consists of a low order part (12) and a high order part (h) (8 bytes each). I
The command string (8 bytes) sent from the DATA signal line is stored in one of the lower or higher parts of these three planes. The location where the data is stored is sent from the IBR#' and EBRQ' signal lines 2020. The instruction buffer selection circuit examines it and stores it in one location where it should be stored. In addition,
At that time, when the HT" signal line is "1", the branch destination associative memory instruction buffer flag 1018 corresponding to the instruction buffer
, 1028.1038 (described later) is stored only when it is [1], and is not stored anywhere in the case of rOJ.

1042 is an instruction register l that holds the instruction currently being decoded.
R11044 and 1046 are registers D indicating from which side of the instruction buffer the instructions currently in the IR were extracted.
This is a register DCΔ indicating from which position (byte position) of the C# and instruction buffer is extracted.

The aligner 1008 extracts an instruction from the instruction buffer and stores it in an instruction register. The DC# signal 1072 determines from which instruction buffer the instruction is extracted, and the position from which the instruction is extracted is determined by the value obtained by multiplying the DCΔ signal by Not L. Gatsl 176 determines when the decoding of the previous instruction is complete (i.e. Br End+0th
er End), the value is given to the aligner.

The next instruction will not be stored in the IR until the decoding of the previous instruction is completed.

1050 is a branch instruction determination circuit; 1052 is an address calculator that calculates the memory address referenced by the instruction; 105
4 is a decoder that decodes instructions.

When the decoding of instructions other than branch instructions is completed, the decoder sets the 0ther End signal to "1".

1060 is an IFA register that holds the start address of the instruction string to be prefetched, and 1058 is an incrementer for that address. The incrementer outputs an increment value after two unit times.

The IBRn signal line 2014 becomes "1" when the instruction string read at the address of the IFA signal line 2010 is to be stored in the lower part of the instruction buffer. This signal is created by inverting the third bit of the IFA register.

This signal also becomes "1" when the branch destination associative memory hits L/.

The IBR# signal line will be described later. 1010-103
8 is a group of status flags for controlling the instruction buffer; 105
6 is a combinational logic for controlling the instruction buffer. The latter will be described in detail later using FIG. 5. The former will be explained below.

The status flag group for instruction buffer control consists of the following three types.

(1) Busy flag BSO, BS1. B52 (101
0, 1020, 1030,): There are three corresponding to the three-sided instruction buffer. When it is "1", it indicates that the instruction buffer is in use, and when it is "fO", it indicates that it is unused.

(2) Branch destination associative memory Hit flag Hog, HOh.

Hlfl, Hlh, H2Q, H2h (1012°1
014. 1022. 1024. 1032°103
4): There are six corresponding to the instruction buffer consisting of three planes, a low-order part and a high-order part. When it is "1", the branch destination associative memory is stored when the instruction string in that part of the instruction buffer is read ahead, and it
When it is "0", -(no bit
). It is "1" when it is predicted that there is a branch instruction in the instruction string read into that part of the instruction buffer.

(3) Branch destination associative memory instruction buffer flag TO9T1
．． T2 (1018, 1028, 1038)=There are three corresponding to the three-sided instruction buffer.

When it is "1", it indicates that the instruction buffer is an instruction buffer for storing an instruction sequence based on the branch destination address output by the branch destination associative memory. When it is "0", this is not the case; when a branch instruction is prefetched, the branch destination associative memory is not hit Lt, and during decoding it is found to be a branch instruction, and the branch destination instruction of the branch instruction is not hit. Indicates an instruction buffer used to store columns.

Furthermore, in the preceding control device, there is a temporary save register T A
qave9178 + selector 9180. S flag 91
86, Set TA 5ave signal line 9182,
Re5etS signal tfA9184. S Igo side line 9 [8
There are 8. The S flag is a flag that becomes "1" if the branch destination address is held in the temporary save register.

Next, the internal structure of the branch destination associative memory will be explained using FIG.

As described above, the branch destination associative memory stores a set of a branch instruction address and a branch destination address.

The branch instruction address is stored in P I C part 3002, and the branch destination address is stored in PIA part 3004. IFl, when the look-ahead address is sent from the 4th side line 2010, HitDe of the 1st branch destination associative memory is sent.
Tecter 3000 searches whether there is a branch instruction address of PICpart within the prefetched range (width 8 bytes) at that address, and if so, sends the HIT signal line 11.
72, and outputs the branch destination address corresponding to the branch instruction address to the PTA signal line 2016. If not, "0" is output to the HIT signal line.

While the PTA signal line is transferred to the main memory, it is also input to the Hit Detstar of the associative memory at one branch destination, so P
When the branch destination address is output to the TA signal line, the IF
The same operation as when a prefetch address is sent from the A signal line 2010 is performed.

The search that the branch destination associative memory performs with the Hit Detector can be configured using conventional technology, and the Hit Detector
Further detailed explanation of the branch destination associative memory including ter is omitted since it is not relevant to the explanation of the embodiment.

Next, the instruction buffer control combinational logic 1056 will be explained using FIG.

As inputs to this combinational logic, the three types of status flag groups for controlling the instruction buffer described above and the HIT signal line Br In
5t signal line, DC# signal line, DCΔ signal line, IBR12
Signal line, S signal line, TKN, NTKN, DC3', IB
There are R#' signal lines.

In this combinatorial logic, there is a truth table (“1” is true, “0” is true,
” means false, “-” means don't care) Logics 5000 to 5006 that describe their functions, and Logics 10008゜5010 to 502 that describe their functions using logical expressions.
2,10024.5026-5038.10040,5
There are 402 to 5054 degrees and 10056 to 10060 degrees. Below, they will be explained in order.

(1) 01. All BS generation logic (5000):
01 is Busy-7 Lug BSO, BSI, B52 (7)
The first number is "0". AllB5 indicates that all three busy flags are "1".

(2) 02, All Not T generation logic (50
00):02 indicates the last number which is "1" among the branch destination associative memory instruction buffer flags To, Tl, and T2. All Not T indicates that all three flags are rOJ.

(3) IBR# signal generation logic (5004): tBR#
is when the busy flag is newly set to "1", that is,
Set BSO, Set BS 1°5etB described later
When either S2 is "1", it indicates that number; otherwise, it indicates the value of the DC# signal line 1072.

(4) DCQ signal generation logic (5006): DCII.

Indicates whether the instruction currently stored in the instruction register IR is extracted from the lower part or the higher part of the instruction buffer. "1" indicates a low-order part, and "0" indicates a high-order part.

This signal is generated from the value of the DCΔ signal line indicating from which position in the instruction buffer the instruction currently in the IR is extracted.

(5) Set T A 5ave generation logic (1005
8): The 5etTAsave signal is a set pulse for the TA5ave register, which causes the TAsave register to hold the branch destination address of the branch instruction being decoded, and at the same time sets the S flag to "1".56tTA5ave
The signal becomes "1" when decoding a branch instruction for which the branch destination associative memory has no bits (Br In5t-■) and when there is no instruction buffer to store the branch destination instruction string of this branch instruction. (AIIBS).

(6) Set BSO, Set BSI, Set
BS2 generation logic (1008, 10024, 10040)
:Set BSO, Set BSI, Set BS
2 signal lines 1082.1102.1122 are set signals for busy flags BSO, BSI, and BS2.

This signal is generated with logic 10008, 10024.10040. The meaning of this logic is that the branch destination associative memory is hi
t, or when a branch instruction is being decoded and the branch instruction is prefetched, the branch destination associative memory is
When it is not set or when the S flag is "1" (i.e., when HiT+Br In5t-H+S)
, if there is an instruction buffer not in use (AIIBS), then the instruction buffer defined by 01 (01=O
then 1BRo, 01=1 then 1BR1, 01=2 then 1
BR2) can be assigned.

According to this logic, when one of the instruction buffers is no longer in use (AIIBS), if the temporary save register is holding the branch destination address (S), 5etBSO, 5etBS1, or 5etBS2 corresponding to the instruction buffer that is no longer in use becomes "1" and an instruction buffer is allocated.

Note that H here is created by H generation logic. D(
4 indicates the number of the instruction buffer in which the instruction currently being decoded is located, and DCQ is "1" if the instruction is in the lower part of the instruction buffer, and "0" if it is in the higher part. Therefore, the instruction currently being decoded is in the instruction buffer
゜2), H=HXD, -DCQ+HX
It becomes Q-DCQ. Furthermore, if the lower part of the instruction buffer is near, then I (= H
It represents whether L/takashi or not. Also, even if it is in the high-order part of the instruction buffer, H=HXh (X=0.1
+2), and H represents the same meaning.

(7) Re5et S generation logic (1, OO60)
: Re5et S signal 9184 is a signal that sets the S flag to "0". This signal indicates that the instruction buffer is allocated (Set BSO, Set BS 1 or 5et) while the temporary save register is holding the branch destination address (S).
It becomes "1" when BS2 is "1"). This signal also reaches the selector 9180, and the selector 9180 changes the value of the TA5ave register only when this signal is "1".
Send to A signal line. At this time, the "allocated instruction buffer number" and "1" are sent to the IBR# and IBRρ signal lines, and the one branch destination instruction string is stored in this instruction buffer.

(8) Re5et BSO, Re+qe
t B S 1, ! 1eset HS
2 generation logic (5010, 5026, 5042): R
, eset B S O, Re5et B S 1.
Re5et B S 2 is busy flag BSO, BS
L, BS2 IJ Shut. This signal is 501
It is generated with the logic of 0,5026°5042. For each logical expression, the branch judgment is made by the arithmetic unit, the branch is taken, and the instruction buffers in which the branch instruction was stored are the 0th, 1st, .
It was the second (T K N・(DC#“=O), T
KN・CDC1t' = 1), TKN・(DC#' =
2)) Or one branch is not taken, and the instruction buffer in which the branch destination instruction of that branch instruction is stored is 0. 1st
．． It was the second (NTKN・(IBR#'=O)
, N.T.K.N.

(IBR#' = 1), NTKN・(IBR#'
= 2)) then rlJ.

(9) Set HOQ, Set )IOh, Se
t HI Q, 5etH1h, Set H2O, Se
t H2h generation logic (5012, 501G, 5028,
5032゜5044.5048):Set HOQ,S
et HOh.

Set HI Q, Set Hl h, Set I
42Q, 5etH2h signal line is 1 branch destination associative memory 1 (
it flag HOA, HOh, HIQ, Hlh, H2O,
This is the H2h set signal. This signal indicates that the branch destination associative memory is a bit, and the instruction buffer in which the instruction to be read is stored corresponds to the branch associative memory Bit flag to be set.
Indicates the corresponding lower part or higher part.

(10) Reset HQ Q, Re5et HO
h, Re5et HI Q.

Re5ot H1h, Re5et H2f
l T Re5et H2h Generation logic (50
14,5018,5030°5034.50'46.5
050): Re5et HOQ.

Re5et HOh, Re5et HI Q
, Re5et)-I1h.

The Re5et H2Q and Re5et H2h signal lines are reset signals for the branch destination associative memory Hit flag.

This signal indicates that the branch target associative memory is at τ, and the instruction buffer storing the instruction to be read at that time is the instruction buffer corresponding to the branch target associative memory old t flag to be reset.

Indicates the corresponding lower part or higher part.

(11) Set T O, Set T 1, Set
T2 generation logic (5020, 5036, 5052):
Set T(J.

Set T 1 and Set T 2 are signals for setting branch destination associative memory instruction buffer flags To, Tl, and I2. This signal indicates that the branch destination associative memory is hit L/.
At that time, it indicates that the corresponding busy flag is being erased.

(12) Reset T O, Re5st T 1 ,
Re5et T 2 generation logic (5022, 5038,
5054): Re5etT O, Re5etT
1, Re5et T2 is To, Tl.

This is a reset signal for I2. This signal is generated when the corresponding busy flag is set to rlJ, and the branch instruction stored in the IR at that time is read, but if the branch destination associative memory is not hit L/( Br
InS-H-8etBSO9Br Ins? H-5et
B S 1 , Br In5t-H-5etBS2
), or if the corresponding busy flag is set to ``0'' (Reset B SO, Re5et B S 1
.

Re5et B S 2) “It becomes 1 no.

(13) Br End generation logic (10056): BrE
The nd signal indicates that decoding of the branch instruction is complete.

This signal is used to decode the branch instruction (Br In5t
) becomes “1”.

Next, the operation of the embodiment will be explained using the time chart of FIGS. 6A to 6D, taking as an example the case where the instruction sequence of FIG. 4 is processed.

First, the instruction string 4006 is in the instruction buffer IBROQ.

Assuming that the six or one branch destination associative memory is read out and processed by IBROh, the set (branch instruction address, branch destination address) is (IOC, 200).

Assume that two sets (204, 520) are stored.

Busy flag BSO is “1” and DC# is “0”
It is. Assume that 100 is stored in the IFA register at time To.

100 in main memory and branch destination associative memory via IFA signal.
is sent to the main memory, and simultaneously rOJ and rlJ are sent to the main memory via the IBH3°IBRQ signal line. The main memory is sent to I3 after 3 units of time from 100 to 10 through the IDATA signal.
Returns the instruction string at address 7, and at the same time IBR#', IBR
rOJ and rlJ are returned via the Q' signal line. The instruction buffer selection circuit 1000 looks at these rOJ and rlJ,
At time T4, this instruction sequence is stored in the instruction buffer I BROQ. On the other hand, the branch destination associative memory receives 100 on the IFA ID line, but since it does not store silk that has a range of 100 to 107 as a branch instruction address, ``O''
to be sent back.

At this time, in the preceding control device, the logic 5014 becomes "1", so HOQ becomes "0" from time T2.

100 in the IFA register is incremented by 8 by the incrementer 1058, and 108 is stored in the IFA register at time 12.

108 to main memory and branch destination associative memory via IFA signal.
is sent, and IBR# is simultaneously stored in main memory.

rOJ and rOJ are sent via the IBRcL signal line.

The main memory returns the instruction sequence from address 108 to IOF via the IDATA signal line at T5 after 3 unit time, and at the same time
rOJ and rOJ are returned via the R#' and IBRQ' signal lines. The instruction buffer selection circuit 1000
, rOJ and stores this instruction sequence in the instruction buffer IBROh at time T6. On the other hand, branch destination associative memory is IF
108 is sent on the A signal line, but since it has a set of branch instruction addresses (IOC, 200) in the range of 108 to IOF, rlJ is sent via the HiT signal line and PTA signal line.
200 will be returned.

At this time, the preceding control device uses the 5etBS1 signal line.

Since the 5etT1 signal line and the 5etI(Oh signal line become "1", BSI, Tl, and HOh become "]" at time T4.

The PTA signal line 200 is sent to the main memory and the branch target associative memory from time T3, and the main memory simultaneously receives IBR# and IBR#.
“1” via the BRQ and HT signal lines.

“1” and “1” are sent. Main memory is T after 3 units of time
6, the instruction string at addresses 200 to 207 is returned via the IDATA signal line, and at the same time IBR#'.

rlJ, rlJ via TBRQ', HT' signal lines
.

Return "1". The instruction buffer selection circuit 1000 sees the value "1" of these "rl", "rl", "rl" and T1,
At time T7, this instruction sequence is stored in the instruction buffer IBRLQ. On the other hand, 200 is sent to the branch destination associative memory via the p''rAm line.

Since the branch destination associative memory has a set of addresses (204, 520) for branch instructions in the range 200 to 207, rlJ, 520 is returned via the HiT signal line and PTA signal line.

520 on the PTA signal line is sent to the main memory and branch destination associative memory from time T4, and the main memory simultaneously receives IBR#, IBR
Q, "2" via the HT signal line.

rl'' and rlB are sent.

At this time, the preceding control device uses the 5etBS2 signal line.

Since the 5etT2 signal line and the SetHIM signal line are rlJ, BS2. T2. HIQ becomes "1" at time T5.

Since BSO, BSI, and BS2 all become "1" at time T5, the -AIIBS signal also becomes "1". On the other hand, To, T
l and T2 are rOJ and rlJ, respectively.

Since it is "1", the All Not T signal is rOJ, 02
The signal will be 2.

Now, it is assumed that the instructions in the instruction sequence 4006 before address 100 are stored and decoded in the instruction register IR before time T5. Then, at time T5, the instruction at address 100 is stored in IH and decoded, and at time T6, the branch instruction at address 104 is stored in IR. At this time, the CDI signal is O and the DCΔ signal is 4.

Since it is a branch instruction, the Br In5t signal will be "1".
For this branch instruction, the branch destination associative memory has no bits, so H is 0, and the instruction buffer is not empty (AIIBS), so Set T A 5ave
The signal becomes "1". As a result, 800 output from the address calculator is stored in the TA 5av6 register, the S flag becomes "1", the Br End signal is rlJ, and the DCEnd signal also becomes "1".

As a result, the next instruction after the branch instruction is stored in the IR and decoding is started.

Further, DC8 becomes "0" and DCQ becomes "4".

In this way, the branch instruction at address 104 is completely decoded and no deadlock condition occurs.

It is assumed that this branch instruction is determined at time T8 and the TKN signal becomes "1". At this time, DC#" becomes "0".

As a result, the Re5et B SO signal becomes "1", and the BSO becomes "0" from time T9.

Since S'75g is "1" and BSO is rOJ, 5etBSO is "1" from T9 and ResetS is also "
1”. Since 36tBSO is “1”, IBR# is “
0".

Due to Re5et S, the S flag is set to rOJ from time TIO.
Therefore, from time T9, the value of the TAsave register is 80.
0 is sent on the TA signal line. Since IBR# is rOJ, the instruction string read based on the TA signal line will be stored in IBRO.When the instruction buffer that was in use becomes unused, it will be stored in the temporary save register. The instruction string is read based on the held branch destination address, and the instruction string is stored in the unused instruction register.

This method of using temporary save registers can also be applied to data processing devices that do not use branch destination associative memory.

Assume that all instruction buffers are being used to store the instruction sequence of the branch destination of the preceding branch instruction, and decoding of another branch instruction is started while the decision on that branch instruction has not been made. Even if the decoding of this branch instruction is suspended, it will not result in a deadlock condition 1 (because the judgment of the preceding branch instruction will always be negative), but there is a problem that the decoding process will stop while it is suspended. At this time, as described above, the address of the branch destination of this branch instruction is held in the temporary save register, the decoding of the one branch instruction is completed, and the subsequent instruction is decoded. When one of the branch instructions is determined and one of the instruction buffers is no longer in use, the branch destination instruction sequence can be read out using the branch destination address in the temporary save register and stored in the instruction buffer.

This method of providing a temporary save register can be used even when the branch target associative memory hits and outputs the branch target address, and there is no instruction buffer to store the branch target instruction sequence based on this. .

At this time, the branch destination address can be held in the 11 save registers, and when one of the instruction buffers is no longer in use, the branch destination instruction string can be read out using the branch destination address in the temporary save register. .

The explanation will be given below using Nos. 7 to 1014.

FIG. 7 is a modification of FIG. 1, and shows the S flag 111.
86. Set PTA signal line 11182°Re5et
S signal line 11184. An S signal line 11188 is newly added. The S flag is a flag that becomes "1" when the branch destination address is held in the temporary save register.

Figure 8 is a modification of Figure 2.
”A, Re5et S signal line 1.1182,11
184 new members have been added.

FIG. 9 is a modification of FIG. 3, in which the temporary save register PTAsave register 3006 and selector 3008
This is a new addition.

FIG. 10 is a modification of FIG. 5, and the logical formula 140
08,14024,14040,14056%Formula% 5056 has been modified, and logical formula 14058°14
060 is new.

According to logic 14058, when the branch destination associative memory bit and outputs the branch destination address, there is no instruction buffer to store the branch destination instruction string based on this bit (Hit A
ll B S), Set PTA signal is “1”
become. At this time, the 5etPTA signal is the PTA register 13.
The set pulse becomes 006, and the PTA register holds the branch destination address output from the branch destination associative memory. At the same time, set the S flag to "1".

Logic 14008, 14024, 14040 indicates that one of the instruction buffers is no longer in use (AIIBS
), if the temporary save register is holding the branch destination address (S), 5etBSO, 5etBSI, or 5etBS2 corresponding to the instruction buffer that is no longer in use becomes "1".
” and an instruction buffer is allocated. At that time, logic 14060 sets Re5et S signal 11184 to "1".
” and set the S flag to “0”. At the same time, Re5et
The S signal has reached the selector 13008, and the selector 13008 selects PTAsav only when this signal is "1".
Since the value of the e register is sent to the PTA signal, the branch destination address is sent to the main memory.

Therefore, when any of the instruction buffers is no longer in use, the branch destination instruction string can be read out using the branch destination address in the temporary save register.

Although the above embodiment uses a temporary save register, there is also a method that does not use it. In other words, when all the instruction buffers are in use, the branch destination associative memory becomes high when an instruction is prefetched.
tL/When a branch instruction that was missing is attempted to be decoded, the instruction buffer that has already been reserved to store the branch destination instruction string read out based on the branch destination address output from the one-branch destination associative memory is preempted. That's what I do. This stolen instruction buffer is used to store the branch destination instruction sequence of the branch instruction being decoded.6 This will be explained below with reference to FIGS. 11 and 12.

11 is a diagram obtained by removing unnecessary parts from FIG. 1, and FIG. 12 is a diagram obtained by adding changes to FIG. 5.

In FIG. 11, the TA 5ave register 9178. which was in FIG. Selector 9180. S flag 9186,
Set TA 5ave signal line 9182°Re5et
S signal line 9184 is gone.

In FIG. 12, the logic in FIG. 5 is 10008°10024.
10040.10056 is logical 500B, 5024.5
04-0.5056, Set TA 5
ave generative logic 1. OO58.

Re8et, S generation logic 1.0 O60 is deleted.

Of the logic that has been changed, 5008゜5024.5
040 are Set BSO, 5etBSI, respectively.
This is the generation logic of 5etBS2. Each logical expression is a logical sum consisting of two terms. In the first term, if the instruction buffer is not all in use (AIIBS) when the branch target associative memory is bit (HiT), the instruction buffer that is not in use is selected by 01 (jBRo if 0=0, 01=1
If 0L=2, then 1BR1, then 1BR2) is assigned. In the second term, a branch instruction is being decoded, and when the branch instruction is prefetched, the branch destination associative memory is hit L/
It wasn't. (Br In5t-H) Sometimes, if the instruction buffer is not all in use (AIIBS),
Allocates an unused instruction buffer selected by 01, and all instruction buffers are in use (Al1138
), if there is an instruction buffer reserved for storing the branch destination instruction string read based on the branch destination address output from the branch destination associative memory (All Not T). .

Allocating an instruction buffer defined by 02.

With this change, all instruction buffers are in use (AII
BS), the branch destination associative memory is hit L when the instruction is prefetched.
/If a branch instruction that was not present is attempted to be decoded (t
If there is an instruction buffer reserved for storing the branch destination instruction string read out based on the branch destination address output from the one-branch destination associative memory (Ar In5t-π), then
Not T), its instruction buffer (if instruction buffer O is then 02 = 0, if instruction buffer 1 is then 0
2=1 and instruction buffer 1 then 02=2) corresponding to 5etBSO or 5etBS1 or 5e
Since the generation logic of tBS2 becomes "1", that instruction buffer is allocated.

Also, the remaining one of the changed logics 5056
Then, when a branch instruction is decoded, if the branch target associative memory is hjt when the branch instruction is read ahead (H), or when the branch target associative memory is hit when the branch instruction is read ahead.
(H), but when any of the instruction buffers can be allocated during decoding (Set B S
O+Set B'S 1 +5etBS2) to Br
The End signal becomes "1". With this change, the decoding of this branch instruction is completed and the decoding of the next instruction is started, so that deadlock does not occur.

In the above embodiment, a data processing device using a branch target associative memory that outputs a branch target address was shown, but even if a branch target associative memory that directly outputs one branch target instruction sequence is used, Since the instruction buffer is used or reserved in advance before decoding, there is a possibility of a deadlock situation, so this invention is effective.

In the above embodiment, when the branch target associative memory is hit L/not present, the instruction buffer used to store the branch target instruction sequence read based on the branch target address output by the branch target associative memory is read-ahead. It was used to store the instruction sequence of the branch destination of the branch instruction.

There is always one instruction buffer whose branch destination associative memory is hj, t
There is also a method of reserving it for storing the instruction sequence of the branch destination of the branch instruction that did not reach L. In other words, the branch destination associative memory is hj,
t and outputs the branch destination address, if there is no instruction buffer remaining for storing the branch destination instruction string of a branch instruction that has not hit the branch destination associative memory that may appear later, the output of the branch destination associative memory The instruction buffer is not used to store the instruction sequence of the branch destination address. If you do this,
Since the branch destination associative memory has at least one instruction buffer for storing the instruction sequence of the branch destination of the branch instruction that is not available, a deadlock condition does not occur.

Figure 13 is a modification of Figure 2, and is based on the logical formula 70.
Only 08.7024 and 7040.7000 differ from those in FIG.

By logic 7000, 0nly One Not B
The S signal is "0" only when there are two or more rOJ busy flags, and is "1" otherwise.

The 01 signal indicates the first number whose busy flag is rOJ.

Due to logic 7008.7024.7040, the branch destination associative memory was hit (IIj, T = r L J)
Sometimes "Oj has more than one busy flag"
ly One Not BS = r I J), the busy flag set signal Set BSO,S
et BS 1゜5et BS2 becomes “IJ.

In this way, even when the branch destination associative memory outputs the branch destination address by hj,t, if two or more instruction buffers remain, that instruction buffer will not be used. A deadlock situation will not occur if the system is left unchecked.

Moreover, FIG. 14 is a modification of FIG. 13, and only the logical formulas 8008, 8024, and 8040 are different from those in FIG.

According to logics 8008, 8024, and 8040, if the branch destination association is hit L, (HiT = rlJ), and all the busy flags are (all three) rl, and r
There are two busy flags (Onl, yOne).
(Not BS - All BS), and all but one (that is, one) of the instruction buffers with the busy flag that is "1" store the instruction string of the address of the output branch destination from the branch destination associative memory. It is set to "1" in order to

+T1)+BS1・BS2・(T1+T2)+B52-
When B S 0-(T 2 +T O)), 5et
BS○.

The Set B S 1 and Set B S 2 signals are “
1" is a Ll.

Therefore, even if the branch destination associative memory outputs the branch destination address with a hit L/, if there are two or more instruction buffers remaining, or if there is only one instruction buffer remaining, the branch destination address is When there is an instruction buffer for storing the instruction sequence of the branch destination of a branch instruction that has not been hit by the associative memory of the branch destination, rather than the instruction sequence of the address corresponding to the branch destination output by the associative memory, the instruction buffer is used. Even in this case, the branch destination associative memory is stored, and all branch instructions that are not tt are decoded, and if the judgment is made, the instruction buffer storing the branch destination instruction sequence of that branch instruction or the branch instruction The stored instruction buffer is no longer in use. Therefore, putlock does not occur.

[Effects of the Invention] According to the present invention, decoding of a branch instruction for which the branch destination associative memory does not hit L is not completed because there is no instruction buffer to store the branch destination instruction sequence of the branch instruction. There is no such thing as a put-lock condition.

[Brief explanation of drawings]

Figure 1 is a block diagram of the advance control device, Figure 2 is a diagram of the overall configuration,
FIG. 3 is a block diagram of a branch target associative memory, FIG. 4 is an example of an instruction sequence, and FIG. 5 is a block diagram of an instruction buffer control circuit combinational logic.
Figure 6 is a time chart, Figures 10, 12, and 13.
14 are block diagrams of the instruction buffer control circuit combinational logic of the modified example, FIGS. 7 and 11 are block diagrams of the advanced control device of the modified example, FIG. 8 is an overall block diagram of the modified example, and FIG. The figure is a configuration diagram of a branch destination associative memory of a modified example. 1002-1006...Instruction buffer, 1042...
・Instruction register, 1052...Instruction buffer control circuit combinational logic, 1010, 1020.1030...Busy flag, 2000...Branch destination associative memory, 2002...
・Advance control device, 2004 ・Main memory, 2006・
...Arithmetic device.

Claims (1)

[Claims] 1. It has one or more instruction buffers that prefetch and store one or more instructions before decoding and executing the instructions, and stores branch destination addresses of branch instructions, and stores branch destination addresses of branch instructions. When it is predicted that there is a branch instruction to branch before decoding, a branch destination associative memory outputs the branch destination address, and one of the branch destinations is selected based on the branch destination address outputted by the branch destination associative memory. In a data processing device having means for reading the above instructions and storing them in an instruction buffer, a temporary save register is provided, and when a branch instruction is read ahead, the branch destination associative memory does not output the branch destination address, but the branch destination address is not output. If all instruction buffers are in use when it is found to be a branch instruction during decoding, the branch destination address of the branch instruction is held in the temporary save register, and the instructions following the branch instruction are decoded. When the instruction buffer that was in use becomes unused, the instruction sequence of the branch destination is read based on the address of the branch destination held in the temporary save register, and the instruction that has become unused is read out. A data processing device comprising means for storing data in a buffer. 2. In a data processing device that has one or more instruction buffers that prefetch and store one or more instructions before decoding and executing the instruction, there is a temporary save register and a buffer that stores the instruction when it is a branch instruction. means for holding the branch destination address of the branch instruction in the temporary save register and decoding an instruction subsequent to the branch instruction if all instruction buffers are in use; When the previously used instruction buffer becomes unused, means for reading out a branch destination instruction string based on the branch destination address held in the temporary save register and storing it in the unused instruction buffer. A data processing device comprising: 3. It has one or more instruction buffers that prefetch and store one or more instructions before decoding and executing the instructions, stores the branch destination address of the branch instruction, and stores the branch destination address of the branch instruction before decoding and executing the branch instruction. When it is predicted that there is a branch instruction to be branched, the branch destination associative memory outputs the branch destination address, and one or more branch destination instructions are read out based on the branch destination address outputted by the branch destination associative memory. It has means for storing in an instruction buffer, or one of the branch destinations of a branch instruction.
A branch destination associative memory that stores one or more instructions and outputs one or more instructions at the branch destination and stores it in an instruction buffer when it is predicted that there is a branch instruction to branch before decoding the branch instruction. In the data processing device, the instruction buffer corresponds to each of the instruction buffers, and is in use for storing a branch destination instruction based on a branch destination address output from the branch destination associative memory, or The branch destination associative memory stores the branch destination address or one or more of the branch destinations when prefetching the branch instruction. If no instruction is output, but when the instruction is found to be a branch instruction when decoded and all instruction buffers are in use, one of the instruction buffers in the above state is selected, means for releasing the instruction buffer and storing the branch destination instruction of the branch instruction being decoded in the instruction buffer; a temporary save register; When all the buffers are in use, the branch destination address is held in the temporary save register, and when the instruction buffer that was in use becomes unused, the address is held in the temporary save register. A data device comprising means for reading out a branch destination instruction string based on a branch destination address and storing it in the unused instruction buffer. 4. It has one or more instruction buffers that prefetch and store one or more instructions before decoding and executing the instructions, stores the branch destination address of the branch instruction, and stores the branch destination address of the branch instruction. When it is predicted that there is a branch instruction to be branched, the branch destination associative memory outputs the branch destination address, and one or more branch destination instructions are read out based on the branch destination address outputted by the branch destination associative memory. It has means for storing in an instruction buffer, or one of the branch destinations of a branch instruction.
A branch destination associative memory that stores one or more instructions and outputs one or more instructions at the branch destination and stores it in an instruction buffer when it is predicted that there is a branch instruction to branch before decoding the branch instruction. In the data processing device, the instruction buffer corresponds to each of the instruction buffers, and is in use for storing a branch destination instruction based on a branch destination address output from the branch destination associative memory, or The branch destination associative memory stores the branch destination address or one or more of the branch destinations when prefetching the branch instruction. If no instruction is output, but when the instruction is found to be a branch instruction when decoded and all instruction buffers are in use, one of the instruction buffers in the above state is selected, A data processing device comprising means for releasing the instruction buffer and storing a branch destination instruction of the branch instruction being decoded in the instruction buffer. 5. Has one or more instruction buffers for prefetching and storing one or more instructions prior to decoding and executing instructions, storing branch destination addresses of branch instructions, and prior to decoding and executing branch instructions. When it is predicted that there is a branch instruction to be branched, the branch destination associative memory outputs the branch destination address, and one or more branch destination instructions are read out based on the branch destination address outputted by the branch destination associative memory. It has means for storing in an instruction buffer, or one of the branch destinations of a branch instruction.
A branch destination associative memory that stores one or more instructions and outputs one or more instructions at the branch destination and stores it in an instruction buffer when it is predicted that there is a branch instruction to branch before decoding the branch instruction. In the data processing device, the instruction buffer corresponds to each of the instruction buffers, and is in use for storing a branch destination instruction based on a branch destination address output from the branch destination associative memory, or The branch destination associative memory stores the branch destination address or one or more of the branch destinations when prefetching the branch instruction. If no instruction is output, but when the instruction is found to be a branch instruction when decoded and all instruction buffers are in use, one of the instruction buffers in the above state is selected, means for releasing the instruction buffer and storing a branch destination instruction of the branch instruction being decoded in the instruction buffer; when the branch destination associative memory outputs a branch destination address or a branch destination instruction; When there is only one unused instruction buffer, that instruction buffer contains the branch destination instruction based on the branch destination address output from the branch destination associative memory or the branch destination instruction output from the branch destination associative memory. A data processing device comprising means for preventing storage. 6. Has one or more instruction buffers for prefetching and storing one or more instructions prior to decoding and executing instructions, storing branch destination addresses of branch instructions, and prior to decoding and executing branch instructions. When it is predicted that there is a branch instruction to be branched, the branch destination associative memory outputs the branch destination address, and one or more branch destination instructions are read out based on the branch destination address outputted by the branch destination associative memory. It has means for storing in an instruction buffer, or one of the branch destinations of a branch instruction.
A branch destination associative memory that stores one or more instructions and outputs one or more instructions at the branch destination and stores it in an instruction buffer when it is predicted that there is a branch instruction to branch before decoding the branch instruction. In the data processing device, the instruction buffer corresponds to each of the instruction buffers, and is in use for storing a branch destination instruction based on a branch destination address output from the branch destination associative memory, or The branch destination associative memory stores the branch destination address or one or more of the branch destinations when prefetching the branch instruction. If no instruction is output, but when the instruction is found to be a branch instruction when decoded and all instruction buffers are in use, one of the instruction buffers in the above state is selected, means for releasing the instruction buffer and storing a branch destination instruction of the branch instruction being decoded in the instruction buffer; when the branch destination associative memory outputs a branch destination address or a branch destination instruction; When there is only one unused instruction buffer and all the status display means except for one in use indicate the above status, the unused instruction buffer has the following information: A data processing device comprising means for preventing storage of a branch destination instruction based on a branch destination address outputted by the branch destination associative memory or a branch destination instruction outputted by the branch destination associative memory.