JPS63314893A - High speed booster circuit - Google Patents

Abstract

PURPOSE:To obtain a high H-level boosting signal at a high speed with consumption of low power by controlling the transistor of a first booster circuit, and then controlling the transistor of a second booster circuit by using a boosting signal output slightly delayed from the control of the first booster circuit to output a high power voltage. CONSTITUTION:Transistors(TR) 1, 4 of the bootstrap circuit 100 and a driver 200 of first and second booster circuits are turned ON by a precharge voltage P, and nods E, C are precharged. When all L-level input LIN is applied, a TR 3 is turned OFF, and a node A becomes a power voltage VCC or higher through a capacitor C1. The TR 8 of the circuit 200 is turned ON with this voltage, the voltage of a node B slowly rises to turn ON TRs 8, 9, 17, the voltage of a node F rises to turn ON a TR 5, thereby setting a node C to 'L'. Thus, a TR 6 is turned OFF, the voltage of a node D rises, the node B becomes the voltage VCC or higher by a capacitor C2, and the output VOUT of the voltage VCC becomes a high power voltage VGG through a TR 9. The load of the high power supply is moderated by the two stage voltage rise to obtain a boosting signal at a high speed with low power.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed booster circuit, and particularly to a high-speed booster circuit used in a MOS type integrated circuit or the like.

[Prior Art] FIG. 3 is a circuit diagram showing a conventional high-speed booster circuit. In the figure, the circuit connects a first power supply Vss (for example, chosen to be the ground voltage), a second power supply Vcc (chosen to be higher than the voltage of the first power supply Vss), and a second power supply Vcc (chosen to be higher than the voltage of the first power supply Vss) 3 power supply VGG (selected to have a higher voltage than the second power supply Vcc), a bootstrap type inverter (hereinafter referred to as bootstrap circuit) 100, and a drive circuit 200. 1
In response to input signal φ being input to input signal line LIN of drive circuit 200, output signal line LOUT of drive circuit 200
A signal φ having approximately the same level as the voltage of the third power supply VGG is outputted at high speed. Note that capacitance ff1c3 is the load capacitance of the output signal line Lo LI T.

Next, the operation of the above conventional circuit will be explained. Although FIG. 2 is a waveform diagram for explaining the operation of an embodiment of the present invention to be described later, the waveforms of the input signal φ, precharge signal P, and node A are the same for the circuit in FIG. As for the output signal φ, the waveform of the circuit in FIG. 3 is shown by a dotted line, so the operation of the conventional circuit will be explained with reference to FIG.

Before the input signal φ is input to the input signal line LIN, that is, when the gate voltage of the transistor 3 is at the "H" level, all of the transistors 1 to 3 are on, and the node A is at the "L" level. ``It's kept at a level. When an "L" level input signal φ is applied to the input signal line LIN in this state, the transistor 3 is turned off and the voltage at the node A rises rapidly. As a result, the gate voltage of transistor 2 is boosted to a voltage higher than the voltage of second power supply Vcc due to the boosting action of capacitor C1, and transistor 2 is strongly turned on. Therefore, the drain of transistor 2 -
The source-to-source impedance is extremely low, and the voltage at node A is boosted to approximately the same level as the voltage of the second power supply Vcc.

Node A is at the same level as the second power supply Vcc, that is, “H”
When the level is reached, transistor 8 in drive circuit 200 turns on and starts charging node B. In response, transistor 9 is turned on and output signal 7 slowly begins to rise to the "H" level.

When the output signal T rises, transistor 5 is turned on, so node C is discharged and transistor 6 is turned off. As a result, node D begins to attain the "H" level, and node B is boosted to a voltage level higher than the voltage level of second power supply Vcc through capacitor C2. As a result, transistor 9 is strongly turned on and the voltage level of third power supply VGG appears in output signal φ.

[Problems to be Solved by the Invention] In the conventional circuit as described above, a voltage VGG higher than the second power supply Vcc is obtained by boosting the voltage of the second power supply Vcc on the semiconductor chip, and this voltage By using VGG, an output signal φ having a voltage level higher than the voltage of the second power supply Vcc is generated. Therefore, the third power supply VGG is provided on the semiconductor chip as an internal power supply, and conventionally, a power supply as shown in FIG. 4, for example, has been used as this internal power supply. The internal power supply shown in FIG. 4 includes three inverters 12a to 12C, two transistors 13 and 14, and two capacitors C.
4 and C5. However, the internal power supply as described above generally has extremely high impedance and therefore has a weak current supply capability. Therefore, there is a problem that the "H° level voltage of the output signal 7 may decrease depending on the load capacity WC3 of the output signal line LoυT and the frequency of the input signal φ."

This invention was made in order to solve the above-mentioned problems, and can reduce the burden on the third power supply VGG (internal power supply), and can generate sufficiently high "H°" with low power and high speed.
It is an object of the present invention to provide a high-speed booster circuit that can obtain a level external pressure signal.

[Means for Solving the Problems] A high-speed booster circuit according to the present invention controls the first transistor with a boost signal generated in the first booster circuit to directly apply the second power supply voltage to the output signal line. Along with communicating,
In the second booster circuit, the second transistor is controlled by a boost signal generated a little later than that in the first booster circuit, and the third power supply voltage is transmitted to the output signal line.

[Operation] In this invention, the output signal line is charged by the second power supply until the voltage of the output signal reaches the second power supply voltage, and after the output signal exceeds the second power supply voltage, the output signal line is charged. By charging the line using the third power source, the burden on the third power source provided as an internal power source is reduced.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, parts similar to those of the conventional circuit of FIG. 3 are given the same reference numerals. In this embodiment, transistors 15 to 18 are added to the configuration of the conventional circuit shown in FIG. The details of the circuit configuration of this embodiment will be explained below.

First, the bootstrap circuit 10 which becomes the first booster circuit
0 is composed of transistors 1 to 3 and a capacitor C1. Transistors 2 and 3 are connected in series and inserted between the second power supply Vcc and the first power supply Vss. A connection point (node A) between transistor 2 and transistor 3 is connected to one electrode of capacitor C1. The gate of the transistor 2 is connected to the second power supply Vcc via the transistor 1, and is also connected to the node E.
It is connected to the other electrode of the capacitor C1 via. The gate of the transistor 1 is given a precharge (M number P. The gate of the transistor 3 is given the input signal line LI
An input signal φ is applied via N.

The transistor 15 (first transistor) is controlled by the boost signal of the bootstrap circuit 100 and the second transistor
The voltage of the power supply Vcc is transmitted to the output signal line LOUT. Therefore, this transistor 15 is interposed between the second power supply Vcc and the output signal line LouT, and its gate is connected to the other electrode of the capacitor C1 via the node E. The transistor 16 is a transistor for discharging the node E, and is inserted between the node E and the first power supply Vss. Transistors 17 and 18 cooperate with drive circuit 200 to configure a second booster circuit. These transistors 17 and 18 are connected in series and interposed between the second power supply Vcc and the first power supply Vss.

The drive circuit 200 includes transistors 4 to 11 and a capacitor C2. Transistors 4 and 5 are connected in series and interposed between the second power supply Vcc and the first power supply Vss. The precharge signal P is applied to the gate of the transistor 4. The gate of transistor 5 is connected to node F, which is the connection point between transistors 17 and 18. A node C connecting transistors 4 and 5 is connected to the gate of transistor 6. Transistors 7 and 6 are connected in series and inserted between the second power supply Vcc and the first power supply Vss. Node D, which is the connection point between transistors 7 and 6, is connected to one electrode of capacitor C2. The gate of transistor 7 is connected to node B. This node B is connected to the gates of transistors 17 and 9 (second transistors), and is also connected to the other electrode of capacitor C2. Furthermore, a transistor 8 is interposed between the node B and the second power supply Vcc. The gate of this transistor 8 is connected to the node A.

Transistor 10 is interposed between the other electrode of capacitor C2 and first power supply Vss. Transistors 9 and 11 are connected in series and interposed between the third Ti source VGG and the first power source Vss.

The input signal line L is connected to the gates of transistors 10 and 11.
An input signal φ is applied via IN. A connection point between transistors 9 and 11 is connected to an output signal line Lou□.

Note that in the above embodiment, transistors 1 to 11°15 to
18 are all MOS field effect transistors, but of course bipolar transistors may be used for these transistors.

FIG. 2 is a diagram showing each signal waveform and voltage change at each node in the embodiment of FIG. 1. The operation of the above embodiment will be explained below with reference to FIG.

First, transistors 1 and 4 are turned on by precharge signal P, and nodes C and E are precharged to the "H" level (ie, the voltage level of second power supply vCC). In this state, when the input signal φ of “L” is applied to the input signal line LIN, transistor 3 is turned off and the voltage at node A begins to rise. As a result, transistor 2 turns on strongly and the voltage at node A rises to the level of second power supply Vcc.
The voltage is increased to approximately the same level as c, and the transistor 15 is also strongly turned on. Therefore, this transistor 15
The voltage of the second power supply VCC is transmitted almost unchanged to the output signal line LO1jT via the second power supply VCC, and the voltage of the output signal line is rapidly increased to the level of the second power supply VCC.

On the other hand, the voltage at node A is transmitted to the gate of transistor 8, turning it on. As a result, the voltage at node B begins to rise slowly, turning on transistor 7.9.17. When the transistor 17 is turned on, the voltage at the node F increases, so the transistor 5 is turned on and the node C is discharged to the ``L°L° level, that is, the voltage level of the first power supply VSS. Therefore, transistor 6 is turned off and the voltage at node D increases.

When the voltage at node D increases, transistor 16 turns on and discharges node E. Therefore, the voltage at node E drops and transistor 15 is turned off.

This allows the output signal line LOU to be connected to the second power supply Vcc.
The charging path to T is cut off. This is because the output signal line Lo using the third power supply VGG is performed after this time.
By charging the UT, the second
This is to prevent charges from flowing back to the power supply Vcc.

On the other hand, when the voltage at node D increases as described above, the voltage at node B increases to a second level due to the boosting effect of capacitor C2.
The voltage level of the power supply Vcc is increased to a level higher than that of the power supply Vcc. Therefore, the transistor 9 turns on strongly and transmits the voltage of the third power supply VGG almost unchanged to the output signal lines t, oUT. As a result, the voltage level of the output signal φ changes to the third power supply VG.
It quickly rises to the voltage level of G.

When the input signal φ goes to “i” again after boosting the output signal 7 and rises to the level, transistors 10, 11 and 18 are turned on and the voltages of the nodes B, F and the output signal T are set to “L”.
``Get down to the level.

Incidentally, the boosting operation in the capacitor C1 is performed immediately after the input signal φ falls to the °L" level.
The boost operation in capacitor C2 is performed by transistor 8.1.
7. This is done after the on or off operation in 5.6, so
This will be slightly delayed compared to the boosting operation in capacitor C1. Therefore, the transistor 9 is connected to the second power supply V
After cc charges the output signal line LOUT via the transistor 15, it is strongly turned on. Therefore, the output signal line LOUT is first charged by the second power supply Vcc to the voltage level of the second power supply, and then the output signal line LOUT is charged to the voltage level of the second power supply VCC.
It will be charged by G. As a result, the burden on the third power supply VGG can be reduced, and a boosted signal of a sufficient level can be generated quickly with low power.

[Effects of the Invention] As described above, according to the present invention, the output signal line is boosted to a predetermined voltage by the second power supply and then further boosted to a higher voltage by the third power supply, so that the internal power supply The load on the third power supply provided as a third power source can be reduced, and a boosted signal of a sufficient level can be generated at low power and at high speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing the waveforms of each signal and voltage changes at each node in the circuit of FIG. 1. FIG. 3 is a circuit diagram showing a conventional high-speed booster circuit. FIG. 4 is a circuit diagram showing an example of a third power supply VGG provided as an internal power supply. In the figure, 100 is a bootstrap circuit, 200 is a drive circuit, LIN is an input signal line, LOUT is an output signal line, 1 to 18 are MOS) transistors, C1 and C2
is the boost capacitor, C3 is the output signal line, LOU
The load capacity of T, Vss is the first power supply, VCC is the second power supply, and VGG is the third power supply.

Claims (2)

[Claims] (1) A first power supply set to a first voltage level, a second power supply set to a second voltage level higher than the first voltage level, and a second power supply set to a second voltage level higher than the second voltage level. a third power supply set to a high third voltage level, an input signal line, and an output signal line, the voltage level of the output signal line being adjusted in response to an input signal supplied to the input signal line; a high-speed booster circuit that quickly raises the voltage to approximately the same level as the third voltage level, the booster circuit that quickly generates a boost signal at a level higher than the second voltage level in response to the input signal; a booster circuit; a first transistor that receives the boost signal of the first booster circuit at its gate and transmits the voltage of the second power supply to the output signal line; provided in association with the first booster circuit; The boost signal is generated in the first boost circuit, and the second boost signal is generated a little later than the boost signal in the first boost circuit.
a second booster circuit that generates a boost signal at a higher level than the voltage level of the second booster circuit; and a second booster circuit that receives the boost signal of the second booster circuit at its gate and transmits the voltage of the third power supply to the output signal line. 2, a high-speed booster circuit equipped with a transistor. (2) A third transistor for discharging, which is inserted between the output terminal of the first booster circuit and the first power supply and turns on in response to the generation of the boost signal in the second booster circuit. The high-speed booster circuit according to claim 1, further comprising: