JPS6331425A - Electric source delay circuit - Google Patents
Electric source delay circuitInfo
- Publication number
- JPS6331425A JPS6331425A JP61173118A JP17311886A JPS6331425A JP S6331425 A JPS6331425 A JP S6331425A JP 61173118 A JP61173118 A JP 61173118A JP 17311886 A JP17311886 A JP 17311886A JP S6331425 A JPS6331425 A JP S6331425A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- delay circuit
- pair
- side terminal
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Networks Using Active Elements (AREA)
- Supply And Distribution Of Alternating Current (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 し産業上の利用分野〕 本発明は電源遅延回路に関する。[Detailed description of the invention] Field of industrial use] The present invention relates to a power supply delay circuit.
従来の電源遅延回路は、電源と負荷の間に直列に接続し
たリレーと電源と並列に接続される抵抗とコンデンサに
よる遅延回路とリレーを駆動する駆動回路から構成され
ている。A conventional power supply delay circuit includes a relay connected in series between a power supply and a load, a delay circuit including a resistor and a capacitor connected in parallel with the power supply, and a drive circuit for driving the relay.
上述した従来の電源遅延回路は、リレーをｆ受用してい
るため、駆動回路が必要である欠点と、メカニカル部品
であるリレーを使用しているため信頼度が低い１寸法が
大きい、消費電力が大きいという欠点がある。The above-mentioned conventional power supply delay circuit uses relays, so it requires a drive circuit, and has low reliability because it uses relays, which are mechanical components.It has large dimensions and high power consumption. It has the disadvantage of being large.
本発明の電源遅延回路は、電源側端子対の一方および負
荷側端子対の一方にそれぞれソース、トレインを接続し
たＭＯＳ−ＦＥＴと、一端を前記電源側端子対の一方に
接続し他端を前記ＭＯＳ−ＦＥＴのゲートに接続したコ
ンデンサと、一端を前記コンデンサの他端に接続し他端
を前記電源側端子対の他方および前記負荷側端子対の他
方に接続した抵抗とを具備することを特徴とする。The power supply delay circuit of the present invention includes a MOS-FET whose source and train are respectively connected to one of a pair of power supply side terminals and one of a pair of load side terminals, one end of which is connected to one of the pair of power supply side terminals, and the other end of which is connected to one of the pair of power supply side terminals. It is characterized by comprising a capacitor connected to the gate of the MOS-FET, and a resistor having one end connected to the other end of the capacitor and the other end connected to the other of the power supply side terminal pair and the other of the load side terminal pair. shall be.
第１図は本発明の一実施例である。この電源遅延回路は
、電源側端子対４の一方および負荷側端子対５の一方に
それぞれソース、ドレインを接続したＭＯＳ−ＦＥＴＩ
と、一端を電源側端子対４の一方に接続し他端をＭＯＳ
ＦＥＴＩのゲートに接続したコンデンサ３と、一端
をコンデンサ３の他端に接続し他端を電源側端子対４の
他方および負荷側端子対５の他方に接続した抵抗２とを
具備する。FIG. 1 shows an embodiment of the present invention. This power supply delay circuit is a MOS-FETI whose source and drain are respectively connected to one of the power supply side terminal pair 4 and one of the load side terminal pair 5.
, one end is connected to one of the power supply side terminal pair 4, and the other end is connected to the MOS
It includes a capacitor 3 connected to the gate of the FETI, and a resistor 2 having one end connected to the other end of the capacitor 3 and the other end connected to the other of the power supply side terminal pair 4 and the other of the load side terminal pair 5.
電源側端子対４に電源が接続されていない場合、遅延用
コンデンサ３には電荷か充電されていないので遅延用コ
ンデンサ３の両端の電位差は無く、ＭＯＳ−ＦＥＴＩは
ＯＦＦとなっている。次に電源側端子対４に電源を接続
すると遅延用抵抗２を通じて遅延用コンデンサ３に電荷
が充電され遅延用コンデンサ３の両端に電位差が生じる
。そこで遅延用コンデンサ３の両端の電位差がＭＯＳ−
ＦＥＴ１のしきい値を越えるとＭＯＳ−ＦＥＴＩはＯＮ
Ｌ負荷側端子対５に電圧が発生する。When the power supply side terminal pair 4 is not connected to the power supply, the delay capacitor 3 is not charged with electric charge, so there is no potential difference between both ends of the delay capacitor 3, and the MOS-FETI is turned off. Next, when a power source is connected to the power supply side terminal pair 4, the delay capacitor 3 is charged through the delay resistor 2, and a potential difference is generated between both ends of the delay capacitor 3. Therefore, the potential difference across the delay capacitor 3 becomes MOS-
When the threshold of FET1 is exceeded, MOS-FETI turns ON.
A voltage is generated at the L load side terminal pair 5.
以上説明したように本発明は、リレーの替りにＭＯＳ−
ＦＥＴを使用し、駆動回路を省略したことにより、電源
遅延回路を小型化低消費電力、高信頼度化する効果があ
る。As explained above, the present invention uses MOS-
By using FETs and omitting the drive circuit, the power supply delay circuit can be made smaller, consume less power, and have higher reliability.
第１図は本発明の一実施例の回路図である。
１・・・ＭＯＳ−ＦＥＴ、２・・・遅延用抵抗、３・・
・遅延用コンデンサ、４・・・電源側端子対、５・・・
負荷側端子対。FIG. 1 is a circuit diagram of an embodiment of the present invention. 1...MOS-FET, 2...Delay resistor, 3...
・Delay capacitor, 4... Power supply side terminal pair, 5...
Load side terminal pair.
Claims (1)
れソース、ドレインを接続したＭＯＳ−ＦＥＴと、一端
を前記電源側端子対の一方に接続し他端を前記ＭＯＳ−
ＦＥＴのゲートに接続したコンデンサと、一端を前記コ
ンデンサの他端に接続し他端を前記電源側端子対の他方
および前記負荷側端子対の他方に接続した抵抗とを具備
することを特徴とする電源遅延回路。A MOS-FET whose source and drain are connected to one of the pair of power supply side terminals and one of the pair of load side terminals, and one end connected to one of the pair of power supply side terminals and the other end connected to the MOS-FET.
It is characterized by comprising a capacitor connected to the gate of the FET, and a resistor having one end connected to the other end of the capacitor and the other end connected to the other of the power supply side terminal pair and the load side terminal pair. Power delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61173118A JPS6331425A (en) | 1986-07-22 | 1986-07-22 | Electric source delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61173118A JPS6331425A (en) | 1986-07-22 | 1986-07-22 | Electric source delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6331425A true JPS6331425A (en) | 1988-02-10 |
Family
ID=15954472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61173118A Pending JPS6331425A (en) | 1986-07-22 | 1986-07-22 | Electric source delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6331425A (en) |
-
1986
- 1986-07-22 JP JP61173118A patent/JPS6331425A/en active Pending
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