JPS6331221A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To realize a wide frequency pulling-in range with a circuit operation at a comparatively low S/N by fetching the result of deciding of quadrant to the titled phase locked loop circuit. CONSTITUTION:The output of a low pass filter 8 is nearly 0 at the non-phase synchronizing state and a threshold value deciding circuit 9 turns on a switch 10. In such state, a quadrant deciding circuit 3 integrates an integrator 6 at every one cycle slip and the control voltage of a variable frequency oscillator 4 is controled in a direction to decrease the frequency difference between the input and local frequencies. As a result, a phase locked loop is locked and the relation of phase between the input and local signals resides around the boundary between the quadrants I and IV. In such state, the output of a filter 8 produces a prescribed DC voltage and the output of the circuit 9 turns off the switch 10. Thus, with the S/N decreased, the state of the quadrant II or III is outputted regardless of the synchronization, control is applied to the integration device 6 to prevent the increase in jitter in comparison with conversional PLL opration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase-locked circuit, and particularly to a phase-locked circuit having a wide frequency pull-in range.

[Conventional technology]

As a first example of a conventional phase-locked circuit, there is a digital phase-frequency detector as a detector sensitive to frequency differences, which is widely used in synthesizers and other devices, and has a relatively high S/N ratio. It works. A second example of a conventional phase-locked circuit operates at a relatively low S/N.
There is a combination of a discriminator and a PLI-.

The first example is Phase Lock Techniques Second Edition (FM Gardner: “P
h a s e l o c k T e c h
ni q IJes”2nd Edition
John Wiey & 5ons) 12
Details are given on pages 1-124. The second example is
Phase Lock Technics 2nd Edition (
FM Gardner: “Phase 1ockTe
chniques”2nd EditionJ o
h n W i I e y & S o n
s), pages 84-85, and Improving Frequency Acquisition of the Acostus Loop (Charles R, Cahn: 'Nmpr.

ving Frequency Acquisit
ion of a Co5tas Loop”
TEF, E Transaction on c
.

mmunicatjons VOI-, C0M-2
5No,] 2. December 1977)
detailed in.

The second example is shown in FIG. In the figure, the output of the orthogonal signal demodulation circuit 1 is a delay circuit 322, a multiplication circuit 33. Delay circuit 341 Multiplication circuit 35. The signal is then sent to a delayed detection type layer wave number detection circuit constituted by an adder circuit 40, and the frequency difference between the voltage controlled oscillation circuit 4 and the input is detected. Proportional control circuit 36. The integral control circuit 37 forms a secondary loop, the output of which is input to the input terminal of the voltage controlled oscillator 4, forming a normal secondary phase-locked loop. The frequency difference detection output is added to the loop by an adder 38 to expand the pull-in range of the phase locked circuit.

[Problems to be solved by the invention] IIF The phase frequency difference detector as the first conventional example is as follows:
A logic level signal passed through a limiter is used as the input, and when the input S/N decreases (below 1-Od B), the noise level may exceed the input signal level, resulting in an erroneous zero-crossing signal. In this case, the conventional digital phase frequency difference detection circuit determines that there is a frequency difference and produces a large phase error output even though the phases are synchronized.

Therefore, a threshold effect occurs in the phase locked circuit, and jitter increases rapidly.

On the other hand, in the combination of discriminators as the second conventional example, it is difficult to adjust the characteristics of the discriminators so that when the frequency difference is O, the demodulated output is zero.

The discriminator also determines the frequency within the demodulation range and low C/
It is relatively difficult to suppress the threshold effect at N, and especially when the C/N is low, the DC demodulated output may fluctuate, making it difficult for the phase synchronization system to pull in.

Means for Solving Problems] The phase-locked circuit of the present invention has a function of performing orthogonal demodulation, a function of performing quadrant determination based on the output thereof, and a function of detecting the direction of frequency offset based on a change in the state of the output. ,
It has a function to integrate the detection result into an integral control term.

[Example] FIG. 1 shows an example of the present invention. Orthogonal signal demodulation circuit 1
In this case, two in-phase orthogonal demodulated outputs are obtained from the input signal and the local signal. This demodulated output is subjected to sign determination by a limiter 2 and is input to a quadrant determination circuit 3. This quadrant determination circuit 3 performs sampling at a sample rate of 1 cycle/4 samples or more with respect to the assumed maximum slip frequency. Numbers 4.5A and 5 in the same figure
B.

As shown in 6.7.11, it is assumed that the phase-locked system is ultimately stable at the boundary between the ■ and ■ quadrants, where the orthogonal component and the in-phase component of O1 have a positive value.

In this case, assuming that there is no noise when synchronized as a phase synchronized system, between quadrants ■ and ■, between quadrants T and H, and quadrant I11.
．． No inter-IV quadrant changes occur. For this reason, as an example, we will focus only on the change between quadrants ■ and 11, and when this change occurs, the value of the in-phase component will be positive/corresponding to the direction from quadrant ■ to ■ or from quadrant ■ to ■. Apply a suitable negative coefficient to the coefficient unit 5
The value multiplied by A and 5B is added to the integrator 6 via the adder 11 as -5=.

On the other hand, those indicated by symbols 4 to 7 constitute a normal phase-locked circuit, in which 4 is a variable frequency oscillator, 5 is a coefficient unit for appropriate scaling, 6 is an integrator, and 7 is an adder. .

Condition B where phase synchronization is not performed (slip)
The output of the low-pass filter 8 is almost 0 at
The threshold value determination circuit 9 turns on the switch 10. In this state, the quadrant determination circuit 3 performs integration in the integrator 6 for each cycle of slip, and as a result, the control voltage of the variable frequency oscillator 4 is controlled in a direction that reduces the frequency difference between the input and local frequencies.

In this state, the result integrated by the integrator 6 through the coefficient multiplier 5B is approximately O during one cycle of slip, and the pull-in operation as a phase-locked loop is extremely weak.

When the frequency difference between the input and the local signal decreases due to the control effect of the integrator 6, the phase-locked loop becomes synchronized, and the phase relationship between the input and the local signal becomes near the boundary between quadrants I and M. In this state, the output of the low-pass filter 8 produces a constant DC voltage, and the output of the threshold determination circuit 9 sets the switch 10 to 017F. For this reason, when the S/N decreases, the state of ■ or In is output despite being synchronized, control is applied to the integrator 6, and the ratio vejitter increases compared to normal P L I- operation. It is possible to prevent this.

[Effects of the Invention] As explained above, the present invention can operate at a relatively low S/N and realize a wide frequency pull-in range by incorporating the quadrant determination results into the phase locked circuit.

In addition, since it has a frequency discrimination function, A, M or P
When tracking M-modulated signals, the risk of side band pseudo-synchronization can be eliminated.

The present invention is suitable for digitalization and can be easily implemented using a signal processing processor or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
It is an explanatory diagram showing operation of a figure. FIG. 3 is a block diagram of a conventional example. 1... Orthogonal signal demodulation circuit, 2... Limiter, 3...
・Quadrant determination circuit, 4...Variable frequency oscillator (VCO)
, 5... Coefficient unit, 6... Integrator, 7... Adder,
8...Low pass filter, 9...Threshold value judgment circuit, 10...Switch turned ON10FF by the output of 9, 11...Adder. Chut Figure 1... Liao Qi's Redemption Code 2. Sus''=/9 3
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Claims (1)

[Claims] A phase-locked circuit that has a function to perform orthogonal demodulation, a function to perform quadrant judgment based on its output, a function to detect the direction of frequency offset based on a change in the state of the output, and a function to integrate the detection result into an integral control term. .