JPS6331025B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an automatic transmission control device for an automobile, and more particularly, the present invention is equipped with an abnormality detection means for detecting an abnormality in a signal pick-up line, a processing circuit, etc. used for determining a speed change. The present invention relates to an automatic transmission control device that performs set abnormality protection. A normal automatic gear shift control system has a control circuit that receives a vehicle speed response signal and a signal corresponding to engine output torque or a throttle opening response signal as input signals, compares and calculates these two signals, and outputs a transmission gear shift operation control signal. . This vehicle speed response signal is supplied, for example, by a known reed switch type vehicle speed sensor that detects the rotation speed of the drive shaft. This reed switch type vehicle speed sensor uses a magnet MG that rotates according to the rotation of the drive shaft.
It operates ON-OFF, and a constant voltage is applied between both terminals, emitting constant voltage pulses at a frequency that corresponds to the drive shaft rotation speed. This vehicle speed sensor is placed near the drive shaft or inside the speedometer, and the output signal line leading to the control circuit may be disconnected. In this case, the same output signal as when the vehicle is stopped is usually generated. For example, in the case of a reed switch with one end connected to the body ground and the other end connected to a constant voltage circuit, a constant voltage non-pulse continuous signal is generated, which is the same signal as when the vehicle is stopped. In such a case, the control circuit of the automatic transmission control system will determine that the vehicle has stopped.
A transmission control signal is issued to shift the gear to the gear shift position (for example, 1st gear) at low speeds, but if the vehicle is traveling at high speed and is suddenly downshifted to 1st gear, sudden and rapid engine braking may occur. is activated,
The shock is large and dangerous, and there is a risk of transmission or engine failure. Japanese Patent Laid-Open No. 52-94975 discloses that when a vehicle speed pulse is missing for more than a first variable time period, the transmission is forcibly locked in a safe speed gear, and when the vehicle speed pulse reappears after a second fixed time period, the vehicle speed is changed. A control circuit is disclosed that sets the transmission to a speed gear corresponding to the automatic transmission, and when the vehicle speed pulse is interrupted, the automatic transmission is set to the safe speed gear. If the vehicle speed pulse signal system is normal but the vehicle speed pulse signal is interrupted due to a special driving condition due to wheels locking during sudden braking, etc., the abnormality detection will be canceled when the wheel rotation is restored. The automatic transmission is set to a speed gear corresponding to the vehicle speed at that time. However, abnormality detection is performed based on the vehicle speed pulse signal, and abnormality detection is not performed in the vehicle speed information processing circuit that generates the vehicle speed signal referred to in shift control based on the vehicle speed pulse signal. Therefore, even if the vehicle speed pulse signal system is normal, if the vehicle speed information processing circuit is abnormal, there is a risk that the wrong speed gear will be set based on the wrong speed information. SUMMARY OF THE INVENTION An object of the present invention is to lock an automatic transmission to a safe speed gear in response to an abnormality in a vehicle speed pulse signal system and a vehicle speed information signal system, and to automatically release the lock in response to the signal system returning to normal. In order to achieve the above object, the automatic transmission control device of the present invention includes: a vehicle speed detection means that generates a pulse signal corresponding to the vehicle speed; a vehicle speed processing means that generates vehicle speed information based on the pulse signal; and a differential value of the vehicle speed information. a differentiating means for obtaining the differential value, a comparing means for comparing the differential value with a set value to detect a decrease in the vehicle speed information by more than the set speed, and when the comparing means detects a decrease by more than the set speed, abnormality detection information is generated and retained. Abnormality detection means consisting of a holding means; a gear change control means that determines the speed stage of the automatic transmission in response to an engine power index signal such as an engine output torque corresponding signal and a throttle opening signal, the vehicle speed information and the abnormality detection information; and a reset means for releasing the holding of the holding means in response to the pulse signal. As a result, when an abnormality occurs in the vehicle speed detection means that generates a pulse signal corresponding to the vehicle speed, the vehicle speed processing means that generates vehicle speed information based on the pulse signal, and the signal line between them, the vehicle speed information is The displayed vehicle speed shows a sudden decrease,
The differentiating means for obtaining the differential value of the vehicle speed information detects this, the comparing means generates abnormality detection information, the holding means holds this, and the shift control means responds to this abnormality detection information to safely operate the automatic transmission. Forcibly locks into speed gear. When the pulse signal appears again,
Since the reset means resets the holding means, the abnormality detection information of the holding means disappears, and the gear stage is set according to the driving condition. Even if the automatic transmission is forcibly locked in a safe speed gear in extremely special driving situations such as wheels locking due to sudden braking, the lock is automatically released when wheel rotation is restored. The present invention provides a differentiating means for obtaining a differential value of vehicle speed information, a comparing means for comparing the differential value with a set value to detect a decrease in the vehicle speed information by more than the set speed, and when the comparing means detects a decrease in the vehicle speed by more than the set speed. Abnormality detection means consisting of a holding means that generates and holds abnormality detection information, and detects not an abnormality in the pulse signal itself but a sudden decrease in vehicle speed information generated based on the pulse signal. Since the abnormality detection information is set by using the system, it is possible to detect not only an abnormality in the vehicle speed detection means that generates a pulse signal corresponding to the vehicle speed and the signal line connected thereto, but also an abnormality in the vehicle speed processing means that generates the vehicle speed information used for determining the speed change. is also detected, so there is a higher probability of preventing shift control errors, especially shift control errors due to abnormalities in the vehicle speed information processing system, than when abnormalities are detected based on the pulse signal itself, and safety is correspondingly higher. . Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In this case, a vehicle speed sensor 31 is a vehicle speed response signal generating means, an FV (frequency-voltage) converter 32 is a vehicle speed signal processing device, a throttle opening detection circuit 33,
The abnormality detection circuit 40, the reset circuit 41, and the shift control device 42 constitute the automatic shift control device of the present invention, which controls the gear position of the automatic transmission 45. Each part shown in FIG. 1 will be explained in detail below. Reed switch of reed switch type vehicle speed sensor 31
The + side of the LSW is connected to the input terminal of the FV conversion circuit 32, and one terminal is grounded to the vehicle body.
The magnet MG rotates according to the rotation of the drive shaft, and the reed switch LSW turns ON and OFF at a frequency that responds to the vehicle speed.
A constant wave high pulse signal appears at the terminal L of the FV conversion circuit 32 due to the circuit configuration in which the reed switches LSW are connected in parallel corresponding to 4. The FV conversion circuit 32 is well known, and detailed explanation will be omitted.
Transistors Tr1 to Tr3, diodes D1 to D
4. Consisting of resistors R1 to R10 and capacitors C1 to C4, it has a shaping, differentiation, integration, and buffer circuit sequentially from the signal input terminal side, and its output terminal connects the resistor R10 to the + side V _S2 terminal that is common to the control circuit. It consists of the emitter terminal A of a pnp type transistor Tr3 (for buffer, collector grounded) connected through. Note that one terminal of the FV conversion circuit 32 is grounded to the body. The + terminal (output terminal) of the reed switch of the vehicle speed sensor 31 is connected to the diode D1 terminal in the FV conversion circuit 32 as an input terminal. The output terminal A of the FV conversion circuit 32 is
It is connected to the − input terminal of the comparator IC1 of the comparison circuit 43. The throttle opening detection circuit 33 has signal pressures V _B , V _C , V _D corresponding to three stages of throttle opening, respectively.
It has OR circuits D7 to D9 on its output end side for selectively supplying signal voltages V _B , V _C , and V to the comparator IC1 of the comparison circuit 43 via diodes D9, D8, and D7, respectively. _D is the second stage constant voltage V _S2
and the ground terminal with two resistors R25 and R2, respectively.
6. The pressure is divided by R21 and R22, R14 and R15. However, each voltage dividing terminal is connected to a comparator via resistors R17, R24, and R28, respectively.
Connected to output terminal G of IC1 (positive return ring)
Therefore, each divided voltage terminal voltage V _B , V _C , V _D is determined by three resistors R25, R26, R28; R21, R22, R
24; Generates three different signal pressures of V _B < V _C < V _D basically defined by R14, R15, and R17. Among these three throttle opening response pressure output terminals B, C, and D, terminal B is only connected to ground via resistor R26, but terminal C (throttle opening second stage) is composed of transistor TR5. The bias voltage input terminal C' of the switch circuit SW1 is connected to the ground via the switch circuit SW1 which conducts to ground when closed, and the bias voltage input terminal C' of the switch circuit SW1 is connected to the ground via the throttle opening detection switch VSW (for example, a vacuum switch for detecting negative pressure in the engine intake system). Grounded, and connected to the constant voltage circuit (hereinafter referred to as + side) via the other resistor R18
Connected to V _S2 . Terminal D, like terminal C, is connected to ground via switch circuit SW2.
Switch circuit SW consisting of transistor Tr4
The bias voltage input terminal D' of No. 2 is connected to ground via another throttle opening detection switch ASW (for example, an accelerator position detection switch or a switch with a different operating point of the same type as VSW), and is connected to the + side via the other resistor R11. Connected to V _S2 . A Zener diode DZ (reverse direction) is connected to the ground in parallel with the capacitor C5 to the + side V _S2 of the output torque corresponding signal E〓 forming circuit 33. Switch circuit SW1 is the npn type transistor
The emitter of Tr5 is grounded, and the collector is connected to the voltage dividing terminal C. Base is diode D6
(in the opposite direction), the capacitor C7 and the resistor R20 are connected in parallel to ground, and the other hand is connected to the terminal C' via the resistor R19, and further via the resistor R18 to the +
Connected to side V _S2 . The switch circuit SW2 is
It consists of an npn type transistor Tr4, whose collector is connected to the voltage dividing terminal D, and whose base is connected to the terminal D' via R12 and the + side V _S2 via the resistor R11, while the diode D5 and capacitor C6
and a resistor R13 connected in parallel. The outputs of the diodes D7 to D9 constituting the OR gate are applied to the comparator 43 as the throttle opening signal E. Switch ASW, VSW is shown in Table 1 below.
This shows the relationship between the opening and closing of and the voltage level of E〓.

[Table] The - input terminal of the comparator IC1 of the comparator 43 receives the output of the FV conversion circuit 32, that is, the vehicle speed signal V _A
However, the throttle opening signal E is applied to the + input terminal. Output terminal G of comparator IC1 is + side
V _S2 via a resistor R30 (hereinafter referred to as the second stage + side V _S2 ), and this second stage + side V _S2 is further connected in series to the first stage + side V _S1 via a resistor R31.
On the other hand, a diode D12 and a resistor R32 are connected to the + side (first stage) V _S1 in parallel with the series resistors R30 and R31 of the solenoid driver 44. In addition,
The conventional + side or constant voltage circuit V _S2 is connected to this resistor R
It is connected to the output terminal K of 31. Further, this first stage + side V _S1 is connected to a + constant voltage power supply via a diode D16. The collector terminal of an npn type transistor Tr6 is connected to the output side of the diode D16, which is the first stage + side, through series resistors R33 and R34, the emitter terminal is grounded, and the base terminal is connected to the resistor R32 through the diode D13.
and the diode D12. The base terminal of transistor Tr6 is also connected to resistor R35.
The collector terminal thereof is connected to the base terminal of an npn transistor Tr7 via a resistor R34. The emitter terminal of the transistor Tr7 is connected to the first stage + side V _S1 , and the collector terminal is connected to the diode D17 and the automatic transmission 45.
The coils of the shift solenoid valve SSV are connected in parallel and the other ends of these are grounded. The automatic transmission 45 is a known solenoid-controlled two-speed transmission. Next, the abnormality detection circuit 40 will be explained. In the abnormality detection circuit 40, a capacitor C9 differentiates the vehicle speed analog signal V _A , and the differential signal is sent to a comparator.
Give it to the - input terminal of IC2. On the other hand, V _S2 is R36,
It is applied to the series circuit of R37 and R38, the divided voltage (constant voltage) of R38 is applied to the capacitor C10, and the voltage of the capacitor C10 is applied to the comparator IC.
It is applied to the + input terminal of 2. Comparator IC2
Since the sum of the voltage drops of resistors R37 and R38 is applied to the - input terminal of , via resistor R39, the voltage at the - input terminal of comparator IC2 is normally higher than the voltage at the + input terminal, and the output of comparator IC2 is at a negative level and the output transistor Tr8 is off. During normal acceleration/deceleration, the rate of change in vehicle speed is small, so the rate of change in vehicle speed signal V _A is small, and capacitor C9 does not substantially generate a differential signal. However, when the reed switch LSW is disconnected or shorted, or when the wheels lock due to sudden braking on a low-friction road, the driving response pulse is interrupted, so the vehicle speed signal
V _A decreases at the fastest speed determined by the time constants of resistors R8 and R9 and capacitors C3 and C4 of the FV conversion circuit 32, and at this time, the potential of the comparator IC2 side electrode of differential capacitor C9 decreases, and the output of comparator IC2 becomes positive. level, and the transistor Tr8 becomes conductive. When Tr8 becomes conductive, resistance R4
0 and the comparator through diode D18
The negative input terminal of IC2 is held at a low potential, so that the output of the comparator IC2 remains at a positive level and the transistor Tr8 remains on (abnormality detection state). Since the collector of the transistor Tr8 is connected to the base of the transistor Tr6 of the solenoid driver 44 via the diode D19, the transistor Tr6 is connected to the base of the transistor Tr6 of the solenoid driver 44 through the diode D19.
is locked off. To summarize the above, the gear settings of the automatic transmission 45 are shown in Table 2 below.

[Table] The reset circuit 41 connects the collector of the transistor Tr1 of the FV conversion circuit 32 and the abnormality detection circuit 40.
A capacitor C11 and a diode D19 are connected in series between the negative input terminal of the comparator IC2.
, bias diodes D20 and D21, and capacitor C to raise the voltage at the negative input terminal of comparator IC2 higher than the voltage at the positive input terminal.
It is composed of eleven charge discharge diodes D22. The vehicle speed response pulse (this is an inverted waveform of the pulse applied to the L terminal) appearing at the collector of transistor Tr1 is always connected to capacitor C.
11, and is applied to the - input terminal and the + input terminal of the comparator IC2 via the capacitor C11 and the diodes D19, D20, and D21, but at the - input terminal, the voltage drop of one diode D19 is applied. However, at the + input terminal, a voltage drop equivalent to the voltage drop of the two diodes D20 and D21 occurs, so a higher voltage is applied to the - input terminal than the + input terminal, so the high level of the vehicle speed response pulse While the signal is "1", the output of the comparator IC2 becomes a negative level and the transistor Tr8 is turned off. Therefore, when the transistor Tr8 is on in the abnormal set state, when the vehicle speed response pulse appears, the transistor Tr8 is turned off and the loop of the resistor R40 and the diode D18 becomes a positive level, which causes the comparator to
The - input terminal of IC2 becomes a positive level, and the output of the comparator IC2 is maintained at a negative level. In other words, the abnormal state is reset. Even in the low level section of the vehicle speed response pulse, the + input terminal of the comparator IC2 is grounded via the diode D22 and the transistor Tr1 of the circuit 32, so the output of the comparator IC2 becomes negative as well.
Transistor Tr8 is turned off. Therefore,
A reset voltage is applied to the comparator IC2 every time a vehicle speed response pulse appears.
In the event of an abnormality, the vehicle speed response pulse disappears, so the anode of diode D22 becomes the voltage of R38,
Circuit 41 applies a voltage lower than the voltage across R38 minus the voltage drops across diodes D22 and D19 to comparator IC2. However, since a higher voltage is applied to the negative input terminal of IC2 through resistors R36 and R39, even if the vehicle speed response pulse disappears, the voltage at V _A will drop at a predetermined speed or higher, and the potential at capacitor C9 will rise. If it does not drop, the comparator
The potential at the negative input terminal of IC2 does not drop enough to make its output positive. Therefore, when V _A rapidly decreases, the output of comparator IC2 becomes positive, turning on transistor Tr8, which causes the abnormality detection latch loop of transistor Tr8 - diode D18 - resistor R40 - comparator IC2 to reach the abnormality detection level ( However, when a vehicle speed response pulse appears and a voltage (reset voltage) at an inverted level (positive) is applied to this loop, the abnormality detection latch loop returns to the normal level (positive). Note that this reset voltage is the comparator IC - transistor Tr.
The voltage may be applied to any part of the abnormality detection latch loop including 8. However, when applying between the comparator IC and the transistor Tr8, the reset voltage polarity is reversed. As shown in Table 2, the reason why the gear stage is set to 2nd speed when an abnormality is detected is that if a wire breakage or short occurs between the terminal L and the sensor 31 during high-speed driving (2nd speed), This is because if the speed is increased, the vehicle speed changes greatly, which is dangerous to the driver, and may also cause a large impact to the clutch system, engine system, and vehicle drive system. Even if the gear shifts from the first gear to the second gear in the event of a failure or sudden braking, the engine load will increase, so the coupling ratio will be lowered in the clutch control system to prevent a large shock from occurring. FIG. 2 shows another embodiment of the invention. In this case, an electromagnetic induction type vehicle speed sensor 31 is used as a vehicle speed response signal generating means, and a pulse shaping circuit 32a, a counter/latch circuit 32b, and a timer circuit 32c are used as vehicle speed signal processing devices.
In addition, the speed change control device 42 is composed of a microprocessor (1-chip microcomputer) 46 and a solenoid driver 44, and the microprocessor 46 is commonly used as abnormality detection means and reset means. In the vehicle speed sensor 31, a magnetic core around which a sensor coil is wound is arranged opposite to a magnet MG that rotates in accordance with the rotation of the drive shaft. It consists of When the magnet MG rotates, an alternating voltage is induced in the sensor coil, which is transmitted to the pulse shaping circuit 32.
applied to a. In the circuit 32a, the first operational amplifier OP1 inverts and amplifies the input alternating voltage,
The second operational amplifier OP2 performs inverting amplification and level shift adjustment, and the first and second transistors
T _r1a and T _r2a perform binarization and inversion amplification. As a result, a vehicle speed response pulse having a frequency and a pulse width corresponding to the rotational speed of the magnet MG is applied to the mono-multivibrator MM1. The mono-multivibrator MM1 is triggered by the rising edge of the speed detection pulse and outputs a high-level "1" pulse with a constant short width. As a result, the output of the mono-multivibrator MM1 produces a vehicle speed detection pulse having a constant pulse width and a frequency proportional to the vehicle speed.
The vehicle speed detection pulse is applied to the counter latch circuit 32b via the NAND gate NA1.
The counter/latch circuit 32b includes 4-bit counters CO1, CO2, latch LA1, and an OR gate.
The counter CO1 counts the vehicle speed detection pulses, and the counter CO2 counts the carry pulses of the counter CO1. That is, counters CO1 and CO2 constitute an 8-bit counter. The count codes of counters CO1 and CO2 are updated and stored in latch LA1 at a predetermined period, and the counters CO1 and CO2 are
is cleared. Therefore, the memory data of latch LA indicates the number of vehicle speed detection pulses during a predetermined period, that is, the vehicle speed. A timer circuit 32c controls updating of the memory of latch LA1 and clearing of counters CO1 and CO2. In the timer circuit 32c, the oscillation pulse of the pulse oscillator OSC is divided by a counter CO4 and NAND gates NA2 and NA3 to form a latch instruction pulse and a counter clear instruction pulse, and the counter clear instruction pulse is short-widthed by a monomultivibrator MM2. Latch LA1 is activated as a pulse (memory update)
Then, counters CO1 and CO2 are cleared momentarily. The pulse that clears the counters CO1 and CO2 is applied as a timing pulse A to the computer 46 together with the vehicle speed response pulse B, and the latch code of latch LA1 is applied to the computer 46 as the vehicle speed instruction code _VCO . The input port of the microcomputer 46 is
Switch ASW for throttle opening detection and
VSW is connected. The ROM of the microcomputer 46 contains program data and programs that perform operations similar to those of the throttle opening detection circuit 33, comparator 43, abnormality detection circuit 40, reset circuit 41, etc. in the embodiment shown in FIG. Constant data to be referenced in the execution is stored in advance. FIG. 3 shows the control operation of the microcomputer 46 based on the program data. The control operation of the microcomputer (hereinafter referred to as microcomputer) 46 will be explained with reference to FIG. 3. When the timing pulse A arrives, the microcomputer 46 reads the speed data V _CO Read the data to V _CO1 and compare it with the data stored in the speed register, V _CO1 −
If V _CO ≧a, that is, if the speed signal level drops abnormally during one cycle of timing pulse A, it is assumed that the signal line is malfunctioning (including wheels locking during sudden braking), and the solenoid driver 44 is Automatic transmission 4 is set by setting low level "0" to the output port and turning off transistors Tr6 and Tr7.
5 to the second speed, set the abnormality flag, and update the speed register with the vehicle speed data V _CO that has just been read (the above is abnormality detection and setting of the abnormality detection state). Then return to the main routine and pulse A.
When the timing pulse A arrives, the process returns to the beginning of the flow shown in FIG. 3 and waits for the arrival of the timing pulse A. When pulse A arrives, since the abnormality flag has been set (abnormality flag present?=YES), the system waits for the arrival of vehicle speed response pulse B, during which time _t1 is counted (timer _t1 ). When the vehicle speed response pulse arrives during _t1 , the vehicle speed response pulse B is determined to be normal and the abnormality flag is reset, V _CO is stored in the speed register, the process returns to the main routine, and the pulse A is returned.
When the timing pulse A arrives, the process returns to the beginning of the flow and waits for the arrival of the timing pulse A. In normal cases,
V _CO −V _CO ≧a? = NO, is there an abnormality flag?
= NO, read the open/close states of the switches ASW and VSW for detecting the throttle opening, and generate constant data V _B , V _C , V _D corresponding to those open/close states, similar to circuit 33 in Fig. 1. is read from the ROM and compared with V _CO , and based on the magnitude relationship between the two, a high level "1": 1st speed designation signal or low level "0": 2nd speed designation signal is set at the output port to the solenoid driver 44. Then, it memorizes V _CO in the speed register and returns to the main routine. At the timing when pulse A appears, it returns to the beginning of the flow in Figure 3 and waits for the arrival of timing pulse A. step settings). In this embodiment, as described above, the main part of the automatic control device is the microcomputer 46, the abnormality detection means is also the microcomputer 46, and the reset means is also the microcomputer 46.
It is said to be 6. Although the above two embodiments have been illustrated and described, the present invention is not limited only to these embodiments and may be implemented in other embodiments. For example, a potentiometer type or absolute encoder type throttle opening sensor may be used instead of ASW or VSW, and furthermore, it can be used not only for throttle opening signals but also for intake manifold negative pressure signals, fuel injection amount signals, and other signals. An engine power indicator signal such as a signal corresponding to engine output torque may also be used.
Furthermore, although the automatic transmission has two speeds, it may have three or more speeds, and furthermore, the gear position can be determined using ROM based on the throttle opening and vehicle speed, for example.
It may also perform other logic, such as accessing and reading gear instruction data. As described above, the automatic transmission control device of the present invention includes a differentiating means for obtaining a differential value of vehicle speed information, a comparing means for comparing the differential value with a set value to detect a decrease in the vehicle speed information by more than the set speed, and the comparing means the vehicle speed generated based on the pulse signal rather than the abnormality of the pulse signal itself. Abnormality detection information is set by detecting a sudden drop in speed, so not only is there an abnormality in the vehicle speed detection means that generates a pulse signal corresponding to the vehicle speed and the signal line connected to it, but also the vehicle speed used for determining the speed change is detected. Abnormalities can be detected not only in the vehicle speed processing means that generates information and the signal line connected to it, but also in the vehicle speed processing means that generates the vehicle speed information used for shifting judgment, so abnormalities can be detected based on the pulse signal itself. The probability of preventing a shift control error, especially a shift control error due to an abnormality in the vehicle speed information processing system, is higher than that in the case where the vehicle speed information processing system is not operated, and the safety is correspondingly higher.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a block diagram showing another embodiment of the present invention, and FIG. 3 is a flowchart showing the control operation of the microcomputer 46 shown in FIG. SW1, SW2: Switching circuit, ASW,
VSW: Throttle opening detection switch, IC1: Comparator, 31: Vehicle speed sensor (vehicle speed detection means), 32, 32a to 32c: (vehicle speed processing means),
C9: Capacitor (differentiation means), IC2: Comparator (comparison means), (Tr ₈ , D ₁₈ , R40: holding means), 40: Abnormality detection circuit (abnormality detection means), 4
2: Speed change control device (speed change control means), 41: Reset circuit (reset means), 46: Microcomputer (abnormality detection means, reset means).

Claims (1)

[Scope of Claims] 1. Vehicle speed detection means that generates a pulse signal corresponding to the vehicle speed; Vehicle speed processing means that generates vehicle speed information based on the pulse signal; Differentiation means that obtains a differential value of the vehicle speed information; Abnormality detection means comprising a comparison means for detecting a decrease in vehicle speed information of more than a set speed by comparing it with a set value, and a holding means for generating and holding abnormality detection information when the comparison means detects a decrease of more than the set speed; A shift control means that determines the speed stage of the automatic transmission in response to an engine power index signal such as an engine output torque corresponding signal and a throttle opening signal, the vehicle speed information, and the abnormality detection information; and a shift control means that responds to the pulse signal. an automatic transmission control device, comprising: a reset means for releasing the holding of the holding means;