JPS63308583A - Interface scan tester - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION With the development of surface mount devices, application-oriented integrated circuits (ASICs) and double-sided boards, board level testing is rapidly becoming a major problem. As densities become higher and higher, the cost of testing increases rapidly.

One approach used in IC design to improve testability and reduce test costs is to partition the main logic circuit into modules that are tested separately. This section consists of shift register latches (SR
This is done by surrounding the module with a boundary scan ring, using either a scan register (SR) or a scan register (SR). Even at the boundary of any logical block that is clearly defined,
The same method can be used. Utilizing boundary scan techniques around the IC's I10 structure provides similar benefits at the board level as well as at the IC level.

Traditionally, systems using boundary scan techniques have made a trade-off between the length of the scan and the number of connectors required to interface with the SRL.

If a minimum number of connectors are used (ie, only those needed to scan the test data/results input/output), the length of the scan can be enormous. No matter how small the number of points tested, the length of the scan remains the same. Alternatively, the scan length can be divided into smaller segments, but with a proportional increase in access lines (connectors).

Due to the constant scan length constraint, in conjunction with system level testing (i.e., large number of TCs), consider adding boundary scan tests inside the IC that can test logic blocks. was not practical. As a result, separate test methods have had to be used for the IC and the board or system.

MEANS AND USE FOR FURTHER SUMMARY OF THE INVENTION The present invention provides the following advantages: 1. Means and Uses for Further Amplifying the Problem The present invention provides the following advantages: 1. The high-speed scanning (FSCAN) method is
A simple theory called device selection module (+) S M )'fg! It is configured using stage W1.

FSCAN is used to select or deselect devices connected to the serial f-tar ring, allowing the serial path to pass through or bypass the internal scan path of the device. Furthermore, using FSCAN in IC design,
Sections of the core logic circuitry can be partitioned for internal scan testing. The advantages of FSCAN over conventional scan paths include reduced test time required to load and unload the scan path, and the need for additional IC pins and board I10 connectors for separate device scan enable control signals. It is.

Another advantage of the FSCAN approach is that it tends to make the scan path more tolerant to failures. For example, if a scan ring connected to a main scan path becomes shorted or opened, rendering the remaining scan paths inoperable, it can simply be deselected using ESCAN's Device Selection Module (DSM). Once the DSM is deselected, the main scan path simply bypasses that subring.

The purpose of this invention is to minimize the number of connectors required for testing.

It is an object of the present invention to enable boundary scan testing to be performed on portions of individual equipment, entire individual equipment, or groups of equipment and systems.

Another object of the invention is to minimize scanning time.
The goal is to allow for variable scan lengths.

Another object of the invention is to provide a higher degree of fault tolerance.

Both of the above and other objects include a plurality of logic devices having input and output lines for selectively sending and receiving data, the first and second of which are both further comprising a logic core and a scan cell having a plurality of pill locations, the scan cell being logically disposed between the logic core and the input and output lines of the first and second logic devices; Selected bits of the plurality of bit positions are selectively substituted for the data under control, and each of the first and second logic devices a device selection module coupled to each scan cell of the logic device, the device selection module of the first logic device also coupled to a first bus for receiving test data bits; A device selection module of the device is also coupled via a second bus, the device selection module of the first logical device receiving the selected test data.
- selectively loading selected bits of the test data bits into a scan cell connected to a device selection module of the first logic device in response to a data bit;
sending other selected test data bits to a device select module of the second logic device via the second bus;
This is accomplished by a boundary scan tester to which the device selection module controls the displacement of data by connected scan cells.

Embodiments Although the device selection module (DSM) can be used for other types of scan designs, the presently preferred embodiment uses the DSM for boundary scan. Boundary scan uses logic elements (
The element(s) are surrounded by a scanning path through which the element(s) can be controlled and observed. Boundary scan cells are typically constructed of serial shift registers. During testing, each shift register bit can output data to or load data from the elements surrounded by the boundary scan. In normal operation, each bit of the shift register has bypass capabilities that allow system inputs and outputs to propagate unhindered through the shift register. Such boundary scan cells are known to those skilled in the art.

To explain FIG. 1, the logical device 1 is the logical core 10
2, and this logic core has boundary scan cells 101 and 10
Surrounded by 3. Normal incoming data on bus 105 can be captured by scan cell 101 or passed onto bus 106 which feeds logic core 102. Alternatively, the data stored in scan cells 101 may be provided on bus 106 for transmission to logic core 102. Similarly, data output from logic core 102 on bus 107 can be captured by scan cell 103 or passed onto bus 108. Data can also be output from scan cell 103 onto bus 108 .

Logic devices 2 and 100 have scan input cells 121 and 131.
, input buses 108, 112, internal input buses 109.11
3. Logic cores 122, 132, internal output buses 110, 1
It is similar to logic device 1 in that it has output buses 111 and 115. Logical units 1.2 and 100 are DSM
104, 124° 134, DSM external scan data input bus 150° 153.157, DSM external scan data output bus '153.1.56, 160. DSM external control input bus 180, DSM internal scan data output bus 151゜1
54.158, DSM Internal Scan Data Input Bus 152.
155, 159, DSM internal 1ilJIlI output bus 1
81, 182, 183, and internal scan cell connection bus 16
I also have 1,162,163.

This invention applies to Device Selection Module (DSM) 104.12.
4.134, along with external control bus 180, external scan data input bus 150, 153, 157 and output bus 153, 156 . '160 is a mechanism that allows the primary scan ring configured with 160 to select and access an embedded scan ring at a lower level. Thus, the primary scan ring can be expanded to include one or more sub-rings attached to the primary scan ring. Each subring attached to the primary scanning ring can select and access the next level of subrings in turn, thus creating a hierarchy of scanning subrings. After the access to the subring is complete, the primary scan ring can be compressed to normal length by deselecting the selected subrings.

A subring to be deselected is selected by setting its DSM to a logic one during a scan operation. A selected subring is deselected by setting its DSM to logic O during a scan. The scan used to select or deselect DSMs is called a mapping scan.

At power up or reset, all subring DSMs are initialized to a deselected state.

In addition to providing a hierarchical scan ring structure, the DSM can be used to gate control signals for each subring in the scan network. Scanning cells 101, 103,
121, 123, 131.133 have control inputs that enable them to perform scanning and testing operations.

If a DSM is selected, it allows these control signals to be passed to the scan cells. When deselected, the control signal is gated off.

There are two main advantages to using DSM. , the first is
By not having to clock serial data over the entire length of the extended scan path, access time to the selected subring is reduced. Second, opening of one or more subrings does not disable the entire scan ring.

In a typical boundary scan system, bus 150 connects scan cell 1
01, scan cell 103 is coupled to bus 153, bus 153 is coupled to scan cell 121, scan cell 123 is coupled to bus 156, bus 157 is coupled to scan cell 131, scan cell 133 is coupled to A control bus 180 (scan clock, scan enable and other necessary control inputs) is coupled to bus 160 and connects all scan cells 101, 103, 12.
1,123,131.133. Therefore, data to be loaded into scan cell 131 must first pass through scan cells 101, 103, 121, and 123. Furthermore, since there is no way to deselect logical units, 1
Even if only one device is of interest, all devices will shift data from their respective scan cells at the same time. This means that for any scan, data must be scanned into all scan cells.

As an example of how long a conventional scan load operation takes, consider the following case.

1. Assume there are 100 logical devices (in FIG. 1 this would be logical devices 1, 2, . . . 100).

2. Each scan cell is a 100-bit shift register (in FIG. 1, these are scan cells 101 and 103).
, 121.123...131 and 133).

3. Also assume that the scan clock rate (ie, how fast data can pass through the scan cells) is 1 MHz.

Therefore, the length of time for the operation is Device Scanning Cell/Device Bit Position/Cell (100) x
2 x (100) clock speed / 1,000,000 = 0.02 seconds This amount of time may not seem particularly long, but each logic device requires , it must be kept in mind that it is necessary to pass through thousands of test patterns. In contrast, the present invention allows this time to be significantly reduced. DSM104,124,
134 allows the scan cells 101, 103, 121, 123, 131, 133 of each logic device @1, 2...100 to be selected or deselected, thus changing the length of the scan path. The overall functionality of the DSM will now be described.

Two scans are required to insert data into a scan cell. The first scan is used to select which DSM to place in the scan path (and thus which scan cell).

If a DSM is selected, it passes the data through its associated scan cell, otherwise it passes the data. A second scan is used to insert data into and extract data from the selected scan cells. An example of this is shown below.

1. 100 logical units (in Figure 1, this is logical unit 1
, 2...100).

2. Each scan cell is a 100-bit shift register (in FIG. 1, these are scan cells 101 and 103).
, 121, 123...131 and 133).

3. Reverse the assumption that the scan clock rate (ie, how fast data can pass through the scan cells) is 1 MHz.

4. Assume that logic device 5o is to be loaded with data from the input of its scan cell.

Therefore, the length of time for this operation is equal to the number of DSMs in the first scanning system.
/ 1,000,000-o, 0001
Number of second scan DSMs selected device 100 + (1)
x bit position / 3f1 selected device clock speed (200) / 1,000,000-0
．． The total J1 time required when using the present invention is 0.0004 seconds, as opposed to 0.02 seconds using the conventional method. In a typical operation of i,ooo scan cycles,
Note that the conventional method takes 20 seconds.

In this invention, the last data scan is used to
Since the SM can be deselected, the first scan (ie, the mapping scan) only needs to be done once, resulting in a time of 0.3001 seconds.

FIG. 2 shows one preferred embodiment DSM 104 (from FIG. 1). A preferred embodiment includes AND gates 201, 202, NAND gates 203, 207,
It includes an inverter 208, a latch 206, a dual port flip-flop 205, and a 2-to-1 multiplexer 204. These individual structures may be of known type.

FIG. 3 shows the presently preferred embodiment of the dual boat flip-flop 205 used in FIG. This embodiment includes a D-type flip 70 tube 251 and a 2-to-1 multiplexer 250.

The action of the multiplexer 250 is the Noritsubu flop 25
1 D input is selected. When multiplexer select input SEL is low, DO is connected to the D input of 7-rip 70-tube 251.

When multiplexer input 5EI- is high, Dl is connected to the D input of flip-flop 251.

1 and 2, the inputs to the DSM 104 (CTLIN, CKIN, ENAIN, R3T
, INI and lN2) and the output from DSM104 (
CTLOUT, GKOUT, ENAOUT, 0UT
2 and OUTUT) are buses 150, 151, 152, 1
53,180.181. Input CTLIN, 0
KIN, ENAIN- and R8T- are control inputs;
Both reach DSM 104 via bus 180. Input INI is the scan data input and reaches DSM 104 via bus 150. Input IN2 comes from scan cell 103 via bus 152. Output CTLOUT, 0KO
UT and ENAOUT- enter both scan cells 101.103 via bus 181. Output 0UT2 is bus 1
51 into the scanning cell 101. 0UT2 is the beginning of the internal data scan path, which passes through scan cell 101, through bus 161, through scan cell 103, and back from bus 152 to input IN2 of DSM 104.

Output 0UT1 is output from DSM 104 via bus 153.

CKIN is the clock used for scanning. As can be readily seen, this clock is not communicated to the scan cell (output signal CKOUT) unless the DSM is selected due to AND gate 202 (by the action of latch 206). Similarly, for AND gate 201 and NAND gate 203, if DSM is not selected, signal CT
LOUT and ENAOUT- are not sent to the scan cell.

The signal CTLIN is used (possibly passed as the output signal CT L OUT) to inform the scan cell that it should perform the following operation. In the presently preferred embodiment, this signal is used to latch data into the scan cells by conventional means. In some cases, extra lines may be used as more control is required.

ELAIN- is an inverted (ie, active low) signal that is used to scan data into and out of the scan cell and DSM. As mentioned earlier, the DSM
is not selected, the corresponding output signal (ENAO
UT-) is not output to the scan cell.

Latch 206 is configured such that when input G (from NAND gate 207) is high, data present at the input appears as an output at 02. When input G is low, output Q2 does not change.

Double boat control flop 205 beam [Jtsuk input CLK, selector SEL for selecting which input D1 or input DO is coupled to output Q1, and clear manual CL
It is configured to have R.

Note that the input CLR is connected to R2H-Power of DSM 104.

R2H- is an inverted signal and is used to globally reset (deselect) the DSM. DSM10 in Figure 2
4 will be used as an example to explain how to do this. R
2H-When the signal is triggered (i.e. pulled low), the signal CLR is connected to the double boat flip-flop 205
given to.

This causes 01 to output low. This causes O to be the input D1 of the double boat flip 70 knob 205, the input of the latch 206, and the input MO of the multiplexer 204.
appears in The output of NAND gate 207 is ENAI
High regardless of what N- is. Since G is high (i.e. high from NAND gate 207), the output Q
2 is low because D is low. This allows D.S.M.
is deselected. After RS T-power returns to its normal high state, inputs CKrN and ENAIN- remain inactive, CKIN is low and inactive, and ENAI
If N- is high, the DSM 104 remains deselected.

The DSM is in two states: selected or deselected. In each of these two states, the DSM can be either idle (ie, scanning is disabled) or active (ie, scanning is enabled). DS
The human power ENAIN- of M determines the idle or active state for both states. Next, when discussing the state of the DSM, we will refer to l) S M of the preferred embodiment shown in FIG.
See 104.

If Ql and Q2 are low, ENAIN- is high, and R2H- is high, the DSM is deselected and idle. In this state, the latch 206 is activated (G is 1% due to the action of the NAND gate 207), and since the Ql from the double boat flip-flop 205 is low,
Since D is low, Q2 is low. Output Q1 is low and remains low regardless of any clock input of input CLK from CKIN due to the feedback path from Ql to Ql via Dl (Di is ENATN-
Is it because SEL is high because it is high? (and selects to return to Ql). Multiplexer 204 connects Ql to 0UT1 since CTRL is low because Q2 is low. Additionally, with Q2 low, all control outputs (CTLOUT, CKOUT and ENAOUT
”) are disabled. Since Ql is low, the scan data outputs (OUTI and 0UT2) are also low.

When Q2 is low, ENAIN- is low, and R2H- is high, the DSM is deselected and activated. When in this state, latch 206 is disabled (G is low due to the action of NAND gate 207).

Q2 remains low regardless of the logic level of 1]. 2
The input Do of the heavy boat flip-flop 205 is EN
Since AIN- is low, it is directed to Ql by the effect of 5EL- being low. The multiplexer 204
is low, so CNTRL is low, so Ql is
"Connect to ri. In this format, INl to Do, 2
01 through the ffl port Noritub flop 205,
Ql to MO, 0UT1 through multiplexer 204
There is a scanning path leading to.

With Q2 low, the control output (CTLOLJT
, GKOUT and ENAOUT > are disabled. While CKOUT is inactive, external scan operation between 0UT2 and IN2 is inhibited, thus deselecting any external scan path from the DSM.

Ql and Q2 are high, ENAIN- is high, R
If 2H- is high, the DSM is selected and idle. In this state, the latch 206 is enabled (G is high due to the action of the NAND gate 207), and the 2
Since 01 of heavy boat flip-flop 205 is high, Q2 is high because D is high. Output Q1 is high and remains high regardless of any clock input of human power OL-K from CKIN due to the feedback path from Ql through Dl back to 01 (because ENAIN- is high) With SEL being high, Dl is selected back to 01). Multiplexer 204 turns IN2 to O
Connect to IJ'r 1. This is because Q2 is high, so CTRL is high. With ENAIN- high, the control outputs CTLOU and CKOU
T is enabled and FNAOUT- is disabled (forced high). This format uses a feedback connection (
01) from Ql through Dl inhibits the scanning operation through the double boat flip-flop 205, and externally FNAOUT (external scanning surface control)
Disabled by IN- being high (i.e.
forced high). However, when in this state, DSM=23- and output clock signals CT LOLJ T and CKO
The attached scan cell can be passed through the UT to perform test operations.

When Q2 is high, ENAIN- is low, and R3T- is high, the DSM is selected and activated. When in this state, launch 206 is not enabled (G is low due to the action of NAND gate 207) and Q2 remains high regardless of the logic level of D. double bow 1
~・The input DO of the Noritsubu flop 205 is ENAIN
Since - is low, J: is directed to Ql due to the effect that S E L is low. Multiplexer 204 is
Connect N2 to 0UT1. This is because CNTRL is high because Q2 is high. In this format,
INl to Do, 2 city port flip-flop 205
There is a scan path through Ql, from Ql to 0UT2. From 0UT2 through an externally connected scan path from 1N2, IN2 to Ml of multiplexer 204, from Ml to 0UT1. With Q2 high, the control output (CT
L OUT, CKOUT and ENAOUT) are enabled and control inputs (CTLIN, CKIN and ENAI
N) can pass through the DSM and out to externally connected scan cells.

There is one scan bit overhead for each DSM. This bit is a double boat flip-flop 205
and is used to control the state (ie, selection or deselection) of the DSM. ENAIN- goes high (signals end of scan cycle, forces “idle”)
The last bit clocked into a previously activated DSM (selected or deselected) determines the next state of the DSM (selected or deselected). For example, referring to FIG. 2, the DSM 104 is in the active state (Q2
is high and ENAIN- is low), then the last scan bit clocked by CKIN into the 02 of latch 206 after G is driven high by signaling and idles DSM). Last pick 1~ (Ql)
If is 1, Q2 remains 1 and the DSM is in the selected state and idle (Ql, Q2 and ENAIN- are all high)
Stay in. If the bit after R (Ql) is 0, Q2
changes to 0 and the DSM is in the deselected state and idle (Q
l and Q2 are low and FNAIN- is high). While in idle, either in the selected or deselected state, Ql, and therefore Q2, cannot change state (unless RST - goes low) and therefore cannot be used for the next active scan cycle ( ENAIN- goes low) begins in the state the DSM assumes after the last active scan cycle.

When a DSM is selected and active, subsequent data is clocked into the scan loop associated with this DSM before being output to any other DSM (as well as its loop). Referring to Figure 1, this means (assuming DSM 104 is selected) that data coming in from bus 150 passes through 08M104.
Go to bus 151, pass through scanning cell 101, go to bus 161
, passes through scan cell 103 , and from bus 152 to 0
This means passing through 8M104 and exiting to bus 153. When a DSM is deselected and active, subsequent data is clocked through the internal IP of this DSM before being output to any other DSM (as well as its loop). To explain Figure 1 again, this is (0
8M104 is deselected), bus 15
The data coming in from 0 enters 08M104 and DSM
This means exiting from 08M104 via bus 153 through the double boat flip-flop of .

The preferred embodiment DSM shown in FIG.
It goes without saying that while Noritub flops, latches and other logic gates are used, this is only one illustration. Those skilled in the art will be able to make various different modifications within the scope of this invention.

The invention is not limited to having one DSM per IC. This hierarchical scanning can be used to test individual logic blocks within a single IC, or it can be used in larger formats such as scanning logic blocks comprised of multiple ICs. be able to. Predetermined DSM
may have a series of other DSMs within the selectable scan path. These DSMs may also have further series of DSMs within their respective selectable scan paths. Therefore, a truly hierarchical scanning path structure can be created. Any one or more DSM (
and its associated scanning path), the length of the load to be tested is
It can be made shorter or longer as needed.

Furthermore, the invention is not limited to use in IC scanning designs. The DSM can be configured similarly to the ICs used in the board design to create the same hierarchical scan structure at the board level as at the IC level. DSM
When the IC is used in this manner, the board scan path is
It can be selected or deselected in the same way as the internal scan path of C.

Separate any ring 111'! 1', the present invention can test the area even if there is a complete open circuit in the ring. Additionally, -type tests can be used to isolate faults within the IC1 circuit, board, and system. This greatly reduces test redundancy, increases failure certainty, and significantly reduces test time and costs.

Although certain preferred embodiments of the invention have been described, there is no intent to limit the invention thereto. It is to be understood that the scope of the invention is limited by the scope of the claims.

In connection with the above description, the following sections are further disclosed.

(1) Each has a plurality of logic devices having input and output lines for selectively sending and receiving data, the first and second of the logic devices further comprising a logic core and a number of bits. a scan cell having a position, the scan cell being logically disposed between the logic cores of the first and second logic devices and the input and output lines, and under control. , selected bits of the plurality of bit rows are selectively substituted for the data, and each of the first and second logic devices further includes a respective one of the first and second logic devices. a device selection module connected to a scan cell of the first logic device, the device selection module of the first logic device also being coupled to a first bus for receiving test data bits; module is also coupled via a second bus, the device selection module of the first logic device responsive to the selected test data bit;
selectively loading selected bits of the test data bits into a scan cell connected to a device selection module of the first logic device; Boundary scan test equipment transmits selected bits of the data via the second bus to a device selection module of the second logic device, the device selection module controlling redemption of data by connected scan cells.

(2) In the boundary scan test apparatus described in paragraph (1), the selected logic device is a discrete integrated circuit.

(3) A boundary scan test device according to paragraph (1), in which the selected logic device is composed of a plurality of integrated circuits.

(4) In the boundary scan test device described in paragraph (1), the first and second logic devices are arranged on a common substrate.

(5) In the boundary scan test device described in item (1), the boundary scan test device includes a scan cell composed of a serial shift register.

(6) In the boundary scan test device described in paragraph (1), the first and second buses are serial data buses.

(7) In the boundary scan test device described in paragraph (1), the device selection module is
Boundary scan test equipment including 0 tubes.

(8) a first device selection module having a first input coupled to a bus for receiving test data bits from an external source; and a plurality of tests each having at least a first input and a first output. a second device selection module having a first input coupled to a first output of a selected test cell, the selected test cells being connected in series, and a second device selection module having a first input coupled to a first output of a selected test cell; The test data bits can be passed from the one test cell to the another test cell by connecting a first input of a cell to a first output of another test cell. , the first device selection module has an IC first output coupled to a first input of a selected test cell, and the second device selection module has an IC first output coupled to a first input of a selected test cell; a first output coupled to a first input of a cell, the first device selection module having a second input coupled to an output of a selected test cell; the first device selection module, the selected series-connected test cell, the second device selection module;
A first test ring is formed consisting of a device selection module and another selected series connected test cell, said second device selection module having a first input of a selected one test cell. and a second input coupled to the first output of one test cell to form a second test ring, wherein the first device selection module has a second output coupled to the first output of the test cell, forming a second test ring; selectively passing a selected one test data bit received from a bus through the first ring; the second device selection module responsive to a selected test data bit from the first test ring; A hierarchical test device selectively passing selected test data bits received through the second test ring and then through the first test ring.

(9) A hierarchical test device according to paragraph (8), wherein the device selection module includes a dual port flip-flop.

(10) having a plurality of test rings, each test ring comprising a device selection module having first and second inputs and first and second outputs; an output is coupled to an input of a plurality of test cells, a first output of the device selection module is coupled to an output of the plurality of test cells, and a first output of the device selection module is coupled to an output of the plurality of test cells; are coupled to each other by serially coupling the inputs and outputs of the devices, the device selection module selectively gates selected inputs from a second input of the device selection module to a second output of the device selection module. A variable length test scanning device configured to pass through the plurality of test cells.

(11) The variable length test scanner of paragraph (10), wherein the device selection module includes a dual port flip 70 tube.

(12) In the method of performing a test using a plurality of test circuits, at least one test circuit having a test cell and gate means for allowing test data to enter the test cell, a first set of data bits for selectively activating and disabling gating means, and a second set of data bits being loaded into said test circuit, wherein the data indicates that the associated gating means is activated; How to ensure that it is loaded only into the test cell.

(13) The method described in paragraph (12), wherein the gate means includes a dual port flip 70 tube.

(14) A method of testing a circuit includes a serial scan path 151, 152, 161, 154° 162.15 through a logic circuit.
A series of shift registers or latches 103,101.121,123,1 forming 5,158,163,139
This is done using a scan design consisting of 31.133. The scan path can be used to observe and control the logic devices 102, 122, 132 in this design through serial scan operation. The present invention is configured such that the scan path passes only through the desired logic element(s) to be tested.
Allows the continuous scan path to be compressed or expanded. Devices connected to the serial scan path (or ring) are selected or deselected 104, 124, 134, thus allowing the serial path to pass through or bypass the internal scan path of a given logic circuit. Using this invention,
Primary scanning ring 150, 153, 156, 157, 16
0 can be created, and from this primary scanning ring a number of scanning sub-rings 151, 1
61,152,154,162゜155.158,16
3.159 can be accessed.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating a number of logic blocks surrounded by boundary scan cells each controlled by a DSM, FIG. 2 is a detailed logic diagram of the DSM of the presently preferred embodiment of the invention, and FIG. 1 is a logic diagram of a dual boat flip 70 tube of the presently preferred embodiment; FIG. Explanation of main symbols 1.2.100: Logic device 101.103, 121, 123° 131.133: Scanning cell

Claims (1)

[Claims] (1) a plurality of logic devices each having input and output lines for selectively sending and receiving data; the first and second of the logic devices further include a logic core and a number of bits; a scan cell having a position, the scan cell being logically disposed between the logic cores and the input and output lines of the first and second logic devices, and under the control of the scan cell; Selected bits of the plurality of bit positions are selectively substituted for the data, and each of the first and second logic devices further includes a respective scan of the first and second logic devices. a device selection module connected to the cell;
a device selection module of the logic device is also coupled to the first bus for receiving test data bits and is also coupled via a second bus to the device selection module of the second logic device; A device selection module of the first logical device selectively selects other selected bits of the test data bits from the device selection module of the first logical device in response to the selected test data bits. and transmitting other selected bits of the test data bits to a device selection module of the second logic device via the second bus to load a scan cell connected to the device selection module. Boundary scan test equipment in which the module controls the displacement of data by connected scan cells.