JPS63308409A - Soft start solid switch - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to control circuits for controlling the conduction of loads, in particular incandescent lamps, electric motors with viscous loads, or similar loads whose impedance changes non-linearly upon turn-on. The present invention relates to a circuit for controlling the flow of current through a semiconductor device coupled to the device.

BACKGROUND OF THE INVENTION In many applications, control circuits used to control incandescent lamps or other loads that have nonlinear impedances during turn-on or warm-up require power transistors (e.g., n-channel metal oxide A semiconductor device such as a silicon field effect transistor (MOSFET) is used.

The drain of one power n-channel MOSFET can be connected to a power source with a positive voltage +VDD, and the source can be connected to one terminal of an incandescent lamp. The second terminal of the incandescent lamp is connected to ground potential. The gate of the MOSFET is coupled through a switch, a manual switch in many applications, to a positive voltage source, typically with a potential level of +VDD, or in many cases +2DD. When the switch is turned on, the MOSFET is enabled (turned on), creating a current path from VDD through the MOSFET and the incandescent J to ground. The electrical characteristics of an incandescent lamp are that while it is incandescent or cold, its resistance value (“cold”
resistance value) is relatively small. When an incandescent lamp starts conducting, J,/l is applied and its resistance increases non-linearly, with the "hot" resistance being much larger than the "cold" resistance.

The MOSFET used has a large current spike when the incandescent lamp is turned on, and a significant portion of the voltage from the power supply, or the relatively small "cold" resistance of the incandescent lamp, is connected between the MOSFET's drain and source. Therefore, the design must be such that a relatively large amount of power can be dissipated.

Figure 1 shows an incandescent lamp, expressed in milliseconds (mS) on the 1 is a graph showing incandescent lamp current in amperes over time (1); Between 1=0+ and t-2m5, the incandescent lamp carries a peak current of 42 amps, and this current decreases to reach a steady state current of 6 amps at approximately t=40 mS. Figure 2 shows milliseconds (ms) on the X-axis.
), take the time (1) expressed as MO in series with the incandescent lamp.
2 is a graph showing the junction temperature in degrees Celsius of the SFET on the y-axis. The temperature of the junction rises rapidly from O′C at 1=0 to about 205°C at t=9ms, then at t=40m
The temperature drops to 95°C by s. The thermal constant of a MOSFET determines the rate at which its temperature rises. many MOSFEs
The desired maximum temperature of T is about 160°C. For this reason,”
In the condition described in 2, there is a risk that the MOSFET may be damaged. One solution to this problem is MOSFE
By increasing the area of T and keeping the temperature from exceeding 160℃,
It is to be able to handle a peak current of 42 amps. A MOSFET with a large area is
This solution is undesirable from an economic point of view, as it requires more silicon and therefore higher production costs.

One conventional solution to the junction temperature problem is to pulse the voltage at the gate of the power MO5FET,
The idea is to only turn on for a short period during each cycle. This limits the average current during one cycle and reduces the temperature rise of the MOSFET. One problem with this method, sometimes referred to as PWM (Pulse Width Modulation), is that it generates multiple relatively large current spikes that can quickly become noise to other circuits using the same power supply. There is a risk that they will be combined. This is highly undesirable in applications such as automobiles, where turning on a turn signal causes a series of loud noises on a radio or tape player.

It would be desirable to be able to turn on a load whose impedance increases non-linearly during turn-on using a moderate cost control circuit that includes a power transistor without introducing large repetitive noise signals. .

SUMMARY OF THE INVENTION The present invention relates to a circuit that can be connected to a load whose impedance increases non-linearly upon turn-on. The circuit includes a device (e.g., a power MOSFET) having a control terminal and first and second output terminals, a first biasing means selectively coupled to the control terminal of the device, and a control terminal of the device. and detection and coupling/decoupling means coupled to a second output terminal of the device. A first biasing means, when coupled to a control terminal of the device, biases the device on to facilitate current flow through the device. A second biasing means, when coupled to a control terminal of the device, biases the device on so as to facilitate a greater current flow through the device than through the first biasing means. The sensing and coupling/decoupling means effectively exposes the impedance of the load, and when the impedance of the load is at or below a preselected level, the first biasing means is coupled to a control terminal of said device; , decoupling the second biasing means from the control terminal of the device. If the impedance of the load is higher than the preselected level, the detection and coupling/decoupling means couples the second biasing means to the control terminal of the device and the first biasing means to the control terminal of the device. Decouple from.

In one embodiment, the first biasing means is a substantially constant current generating means that biases the control terminal of the device such that a substantially constant current flows through the device. In another embodiment, the first biasing means is a substantially constant current means, which biases the control terminal such that a substantially constant current flows into the control terminal of the device, so that, along with the current passing through the device, the control terminal so that the bias increases over time. In either embodiment, the second
The biasing means biases the device strongly on so that the device is substantially fully on and the resistance of its output is the lowest possible value.

In the present invention, the magnitude of the current spike produced by the series combination of a transistor and a load whose impedance increases non-linearly upon turn-on is such that a relatively low level of current flows through it. It has been found that a noticeable reduction can be achieved by first biasing the device. This low level current flow warms up the load (eg, a light) and increases its resistance. After the resistance of the device increases to a preselected level, the biasing action is significantly increased. This allows the load to fully turn on and cause the "high temperature" that occurs during steady-state operation.
A (high) resistance state is reached.

By reducing the magnitude of the current spike, it is possible to significantly reduce the area of the transistor and thus reduce its cost.

The present invention will be better understood from the following detailed description of the drawings.

DETAILED DESCRIPTION In FIG. 3, a soft start solid state switch 10 is shown within the dashed box. This switch is an n-channel metal oxide silicon field effect transistor (MOS).
FET) 12 (also called a device), n-channel MO5FET 14°16.60 (also called a switching device), operational amplifier 18.2, human power comparator 2
0, logic circuit 22, voltage multiplier circuit 24, resistor 26, first
The reference voltage source (Vrefl) 2g and the second reference voltage source (Vref2) 30 are configured. A non-linear load 32 (eg, a light) is coupled to the drain of transistor 12 and terminal 34. A second terminal 35 of load 32 is coupled to power supply VSS, which is typically at ground potential. A switch 36 is coupled to one input terminal 38 of logic circuit 22 . A first terminal of switch 36 is coupled to a first terminal 40 of resistor 42 .

A second terminal 44 of resistor 42 is coupled to power supply +VCC. When switch 36 is closed (its wiper arm connects terminals 40 and 38), soft start solid state switch 10 initially causes a relatively small, substantially constant current to flow through load 32.

The impedance of load 32 increases as it warms up by having current flow through it. After the impedance of the load reaches a preselected value, switch 10 acts to allow the current through load 32 to be increased significantly.

The load 32 conducts much more current until it reaches a "hot" (high impedance level) operating condition, during which the current flowing through it is significantly less than the magnitude of the highest level reached at turn-on. A low steady state level is reached.

As will become apparent from the discussion below, switch 10 initially limits the current through load 32 to a relatively small, substantially constant level. This relatively small, substantially constant current flowing through load 32 warms it up and increases its impedance. When a low level, approximately constant current increases the temperature and impedance of load 32, switch 1 is turned off until a pre-blocked level of impedance is created.
0 senses the impedance of the load 32. At that point, switch 10 biases transistor 12 fully on. The current through transistor 12 and load 32 increases significantly and the impedance of load 32 continues to increase until it reaches its "hot" (high) impedance level associated with steady state operation. The initial heating of the load 32 (called preheating) by a constant current flowing through it increases its impedance and thus
When biasing switch 10 or transistor fully on, the resulting load 32 and transistor 1
The current spike through 2 is much smaller than if no low current preheating were used. This causes transistor 12 to be biased fully on from the beginning, allowing transistor 12 to conduct as much current as required by the initial "cold" impedance.
2 can be made into a transistor with a smaller area.

Transistor 12 is typically a large MOSFET, which requires a large amount of silicon area compared to all other components, devices and circuitry of switch 10. Therefore, being able to keep the area of transistor 12 to a relatively moderate level significantly reduces the overall size and therefore cost of the silicon integrated circuit chip on which switch 10 is fabricated.

The gate of transistor 12 is coupled to the sources of transistors 14, 16, the drain of transistor 60, and node 46. The drain of the transistor 16 is the operational amplifier 18
is coupled to the output of and node 48. The output terminal of voltage multiplier circuit 24 is coupled to the drain of transistor 14 and node 15. The source of transistor 60 is connected to VSS and terminal 3
5. Voltage multiplier circuit 24 and transistor 1
2 trains are coupled to power supply +VDD and terminal 11. l.runcistor 12 has two sources. A first source is connected to terminal 34, load 32, a first terminal of resistor 26, a first terminal of voltage reference source 28, and a first terminal of comparator 20.
(positive) terminal.

! - the second source of transistor 12 is connected to the second terminal of resistor 26, the first (negative) input terminal of operational amplifier 18 and node 5;
Combined with 0. A second terminal of voltage basis source 28 is coupled to a second (voltage) input terminal of operational amplifier 18 and node 52 . An output terminal of comparator 20 is coupled to a second input terminal of logic circuit 22 and node 54 . A first output terminal of logic circuit 22 is coupled to the gate of transistor 60 and node 62 .

A second output terminal of logic circuit 22 is coupled to the gate of transistor 14 and node 56. A third output terminal of logic circuit 22 is coupled to the gate of transistor 16 and node 58 . ' Assume that switch 36 is initially open (the position shown in FIG. 3) and load 32 is off for a period of time. terminal 3
4 is approximately zero, and the output of comparator 20 is a logic zero, typically at or near ground potential. After this, switch 3, like when turning on the herad light in a car.
Close 6.

In this case, switch 36 is typically a manual switch located inside the passenger compartment of an automobile, and load 32 is a headlight. As a result, the output of logic circuit 22 or approximately O
It generates an “O” of volts and typically generates a “1” higher than +VDD when +VDD is in the range of +12 to +16 volts (automotive battery voltage).

These voltages bias transistor 14 off and bias transistor 16 on. Operational amplifier 18 produces an output voltage at terminal 48 that is coupled through biased on transistor 16 to bias transistor 12 on. +VDD) Current begins to flow through transistor 12 and load 32 to VSS. The potential present at node 50 is compared with the voltage at node 52 at operational amplifier 18 . Vref
The voltage level of l is! - selected to correspond to the desired current level to be selectively passed through transistor 12 and load 32; The output voltage developed at node 48 from operational amplifier 18 has a level that biases transistor 12 on, thereby setting the current therethrough to a desired substantially constant level. This level is such that the power consumed by transistor 12 is within the limits that transistor 12 can dissipate without being damaged.

When this approximately constant current flows through the transistor 12 and the load 32, the load 32 is heated and its resistance value becomes "low temperature".
It starts to increase from (low) resistance value towards "high temperature" (high) resistance value. The increase in resistance increases the potential at node 34. When the voltage level at node 34 exceeds Vref2, comparator 20 forces node 54 to a "1". Vref2 corresponds to a preselected impedance level. Therefore, "1" is applied to the terminals 38 and 54 of the logic circuit 22.

As a result, logic circuit 22 has a "1" in node 56, and node 5
"θ" is generated at 8. These conditions bias transistor 14 on and transistor 16 off. This couples the output voltage of voltage multiplier circuit 24 to the gate of transistor 12 and isolates the voltage at output terminal 48 of operational amplifier 18 from the gate of transistor 12. Therefore, the voltage at the gate of transistor 12 increases from less than +VDD to about +2VDD. This biases transistor 12 more strongly on, reducing its drain-source resistance and thus allowing it to conduct much more current. Resistance values of transistor 12 and load 32, +VDD and VS
The magnitude of the difference between S determines the current through the series combination of both.

Initially there is a relatively large current spike, but this is within the limits that transistor 12 can safely dissipate, after which the current increases with the resistance of transistor 12 and the load 3.
2 to a much smaller constant level that is a function of the "hot" resistance value.

Figure 4 shows the current in amperes (solid line) and resistance in ohms (dashed line) in milliseconds (mS) for a typical load such as a car headlight (32). A graph plotted on the y-axis against the x-axis of time (1) is shown. During time 10+ and t=16 ms, the current flowing through lamp 32 is approximately constant, about 2 amperes. During this period, the resistance of the lamp 32 varies from about 0.2 ohms to about 0.
．． Increase to 4 ohms. At t-16+mS, a current spike occurs with a maximum level of about 24 amps.

This is because the resistance value of the lamp 32 has increased sufficiently by t=16 ms, and the voltage at the node 34 has become larger than Vref2. Therefore, at this time, the gate of the transistor 12 is strongly biased on by the voltage multiplier circuit 24. This is because the output terminal 18 of amplifier 18 is now disconnected from the gate of transistor 12. t=
During 16+ms and t=40ms, the current through lamp 32 decreases and reaches a steady state value of approximately 6 Amps. During this same period of time, the resistance of lamp 32 increases from 0.4 ohms to 2.25 ohms. If the gate of transistor 12 is immediately strongly biased when switch 36 is closed,
The current swell in transistor 12 that occurs then is 42 amperes, as shown in the graph of FIG. 1, which causes damage to transistor 12.

In Figure 5, the time (1
) and the junction temperature of the transistor 12 in degrees Celsius is plotted on the y-axis. t=Q+ to t
During -16+mS, the temperature of the junction of transistor 12 is
The temperature rises to approximately 110°C at a roughly constant rate. t=16+
ms, the temperature rises even more rapidly and reaches a maximum value of about +150° C. at about t=25 ms. Then the temperature drops and t
=40ms, the temperature will be approximately +125°C. Therefore, it can be seen that the temperature of transistor 12 is substantially limited to +150° C., so that there is no damage to transistor 12.

FIG. 6 shows a transconductance operational amplifier 18a and a constant current source 60 that can be used in place of the operational amplifier 18, resistor 26, and voltage source (Vrefl) 2g in FIG.
It is shown.

FIG. 7 shows a differential current amplifier 18c and a constant current source 70 that can be used in place of the operational amplifier 18, resistor 26, and voltage source (Vrefl) 28 of FIG.

FIG. 8 shows one embodiment of the logic circuit 22. In FIG. This is a two-man gate 80.82 and an inverter 84
．． Consists of 86. If switch 36 of FIG. 3 is open, the equivalent of 0'' is applied to terminal 38. Regardless of the signal level applied to terminal 54, node 56.5
8 is "0" and node 62 is "1". This condition isolates the gate of transistor 12 (node 46) from any source of turn-on bias, so that transistor 12 is inactive and acts as an open circuit between terminals 11 and 34. Additionally, transistor 60 is enabled (turned on), which pulls node 4B (the gate of transistor 12) to VSS, and transistor 12
deactivate.

When the switch 36 is closed, the input signal to the terminal 38 becomes "1". This disables transistor 60,
The potential at node 46 can be varied to bias transistor 12 on. If the input signal to terminal 54 is "0", then clause 56.58
The output signals appearing at are "0" and "1", respectively. Therefore, the output of the operational amplifier 18 is the gate of the transistor 12).
(node 46) and isolates the output of voltage multiplier circuit 24 from the gate of transistor 12 (node 46). Therefore, a relatively small and substantially constant current flows through transistor 12 and load 32. Terminal 38 is still “
1", and when terminal 54 switches from "0" to "1", terminals 56 and 58 switch to "1" and "0", respectively. This disconnects the gate of transistor 12 from the output of amplifier 12. is connected to the output of voltage multiplier circuit 24. In this state, transistor 12 can conduct much more current from +VDD because its drain-source resistance is small. At this point,
This corresponds when the resistance value of load 32 exceeds a preselected level represented by the level of Vref2.

In FIG. 9, a soft start switch 200 according to one embodiment of the present invention is shown within the width of the dashed box. The switch 200 is an n-channel MOSFET 202
．． 2-power comparator 276. 2-power differential amplifier 230, diode 22'4, 226° 270.274, Zener
Diode 302, power supply bypass capacitor 298, 300
, 344, 346. 356, 358, potentiometer 282° 320, capacitor 348, switching device 306, 322, current sensing coil (current transformer) 214, resistor 216, 219, 220, 228, 234° 238.
240,244,248,258,264.278,2
88,290,294,304゜31.0,314,3
24,326,328,352.2 people Kanoa Gate 2
54, 260 and an inverter 250. A light 204 (typically a car headlight) whose turn-on is to be controlled by switch 1o is coupled to a positive power supply →-Vbat (typically the positive terminal of a car battery) and terminal 212. . A second terminal of lamp 204 connects the drain of MOSFET 202 and node 206.
is combined with The source of transistor 202 is coupled to a negative terminal of a power supply, Vb at 208 (typically the negative terminal of a vehicle battery). The switch 268 is
One terminal of the manual switch, typically located in the passenger compartment of an automobile, is coupled to terminal 212 and +Vbat, and the other terminal is coupled to a first terminal of resistor 264 and terminal 266.

Transistor 202 controls the current through lamp 204 to
When switch 368 is turned on (the condition shown in FIG. 9), transistor 202 turns on the source (essentially operational amplifier 33).
0), which causes the lamp 204 to
and a relatively small, preselected, substantially constant current flows through transistor 202 . Current flows through the lamp 204 H, +7
, monitors its impedance, and when the impedance of lamp 204 reaches a preselected level, gate terminal 35
The weak bias applied to terminal 354 is turned off, and a strong (fully on) bias is applied to terminal 354. The strong bias tends to cause significant current to flow through lamp 204 and transistor 202. As with the switch in Figure 3, the light (
The relatively low level of current flowing between the load (the load) and the current control transistor is used to first heat the load (lamp) and increase its impedance (resistance). When the resistance of the load (lamp) reaches a preselected level, the bias applied to the gate of the current control transistor is increased significantly so that the transistor is fully biased on. When the transistor is biased fully on for the first time, a current spike is generated. The magnitude of the current spike is much smaller than it would be if the transistor were not turned on weakly initially. This reduces cost by allowing the area of the transistor to be much smaller than if the transistor had to be able to safely conduct much larger currents.

Resistors 216, 248, 304, operational amplifier 330, light 2
04, comparator 276.2, a first terminal of each of human powered differential amplifier 230, switch 268 and capacitor 344, 346 is coupled to terminal 212 and +Vbat. first terminals of capacitors 298, 300, 356, 358;
the second terminal of the capacitor 344, 346, the resistor 219,
240°290.324, 326, 340 each first
a second terminal of differential amplifier 230, a source of transistor 202, a first terminal of current sensing coil (current transformer) 206, an anode of Zener diode 302, and second and third terminals of comparator 276. terminals are connected to terminals 208 and -
Coupled to Vbat.

a second terminal of operational amplifier 330 and capacitor 356 .
A second terminal of 358 is coupled to terminal 210 and power supply -Va.

A second terminal of lamp 204 is coupled to the drain of transistor 202, a first terminal of resistor 220, and node 206.

A current sensing coil 214 is wrapped around a wire (not referenced) that couples the second terminal of lamp 204 to the train of transistors 202. A second terminal of current sensing coil 214 is coupled to a second terminal of resistor 340, a first terminal of resistor 336, and node 338. resistance 3
A second terminal of 36 is coupled to a first input terminal (the negative input terminal) of operational amplifier 330 and node 334 . A second terminal of operational amplifier 330 is coupled to a first terminal of capacitor 348 and terminal 335 . A second terminal of capacitor 348 is coupled to the output terminal of operational amplifier 330, a first terminal of resistor 352, and node 350. A second terminal of resistor 352 is coupled to the gate of transistor 202 and node 354 . the second terminal of each of resistors 216 and 219, node 218, the anode of diode 224, diode 226;
is coupled to the positive first input terminal of differential amplifier 230 and node 218 . The second terminal of the resistor 220 is the cathode of the diode 224, the anode of the diode 226, and the resistor 22.
8 , a negative second input terminal of differential amplifier 230 and node 222 . A second terminal of resistor 228 is coupled to an output terminal of differential amplifier 230, a first terminal of resistor 234, and node 232. 1st 3 of resistor 234
6-2 terminal is the first terminal of resistor 238, diode 270
, the anode of diode 274 , the positive first input terminal of comparator 276 , and node 236 .

A second terminal of switch 268 is coupled to a first terminal of resistor 264 and node 266 . The second terminal of the resistor 264 is the Noah Gate) the first input terminal of the resistor 254, 260, the resistor 2
58 and a node 259 . resistance 24
8 is the output terminal of the comparator 276 and the resistor 244
, a first input terminal of inverter 250 , a second input terminal of NOR gate 260 , and terminal 246 . The second terminal of resistor 244 is connected to the second terminal of resistor 238.
is coupled to a first terminal of resistor 240 and node 242 . The output terminal of the inverter 250 is a NOR gate 25
4 and a node 252. Noah·
An output terminal of gate 260 is coupled to a control terminal of switch 322 and node 262 . The output terminal of NOR gate 254 is coupled to the control terminal of switch 306 and node 256.

The first terminal of resistor 278 is the cathode of diode 270, the anode of diode 274, and the second (negative) terminal of comparator 276.
It is coupled to an input terminal and node 272 .

A second terminal of resistor 278 is coupled to the wiper arm of potentiometer 282 and node 281 . A first terminal of potentiometer 286 is coupled to a first terminal of resistor 288 and node 284 .

A second terminal of resistor 288 is coupled to a second terminal of potentiometer 282 , a second terminal of resistor 290 , and node 286 . The second terminal of the resistor 294 is connected to the capacitor 298,
300 , a cathode of Zener diode 302 , a second terminal of resistor 304 , a first terminal of resistor 310 , a first output terminal of switch 306 and node 296 .

The second output terminal of the switches 306 and 322 is connected to the resistor 328.
A first terminal of resistor 326 is coupled to a second terminal of resistor 326 and node 308 . The second terminal of the resistor 328 is connected to the operational amplifier 33
0 and a second (pressure) input terminal at node 332 . A first output terminal of switch 332 is coupled to wiper arm 318 and node 219 of potentiometer 320 . A first terminal of potentiometer 320 is coupled to a second terminal of resistor 310 , a first terminal of resistor 314 , and node 312 . The second terminal of resistor 314 is connected to the second terminal of resistor 324.
, the second terminal of potentiometer 320 and node 3
16.

Switch 268 is shown with its wiper arm (not referenced) open and connected to terminal 212.268.
are separated from each other. This is the position of switch 266 used to turn on light 204. Both switches 306 and 322 are typically motorized rollers (M
C14016), which consists of a pair of complementary MOS transistors and an inverter. An input terminal of switch 306 (node 256) is coupled to the gate of the n-channel transistor of switch 306 and the input terminal of its inverter. The output of the inverter is coupled to the gate of a p-channel transistor. The drain of the n-channel transistor and the source of the p-channel transistor are coupled to node 296. A source of an n-channel transistor and a train of p-channel transistors are coupled to node 308.

The transistors and inverters of switch 322 are connected in substantially the same way as the corresponding elements of switch 306, or coupled to nodes 256, 319, and 30g.

Assume switch 268 is in the turn-on position shown in FIG. When in this position, switch 200 initially connects transistor 200 to
The gate of lamp 204 (node 354) is weakly biased on, setting a relatively small constant current to flow through lamp 204 and transistor 202.
and allows current to pass through transistor 202, and thereafter, after the resistance of lamp 204 reaches a preselected level, the gate of transistor 202 is strongly biased on, causing lamp 204 and transistor 202 to pass. It seems that a much larger current flows through... resistance 2
The combination of 16,219,220°-40=22111.234 and operational amplifier 230 is
The voltage at node 206 is compared to the voltage at node 218 and acts to produce twice that difference at terminal 236 .

Diodes 224 and 226 act to clamp the voltages at nodes 218 and 222, respectively, to within approximately 0.8 volts of each other. The voltage level appearing at node 236 provides one input to the positive input terminal of comparator 276 (node 236).

Resistance 304, 294°288, potentiometer 282
and resistor 290 act to generate a reference voltage corresponding to the preselected resistance of lamp 204, which voltage is applied to the negative input terminal of comparator 276 (node 27).
2) appears. When the voltage at node 236 is less than the voltage at node 272, the output of comparator 276 (node 246) is a logic “O” (typically Since the second input terminal of the NOR gate 260 is "0", the output of the NOR gate 260 (the level of the node 26
2) is "1". Inverter 250 or comparator 276
, thus applying a "1" to the second input terminal of the NOR gate (node 256).

Control terminals of switches 322 and 306, respectively (section 256.2
62), switch 322 couples node 319 to node 308, and switch 306 disconnects node 296 from node 308. Node 319 is at a lower voltage level than node 296. Therefore, the lower voltage level of node 319 is coupled to node 308. resistance 32
After some voltage drop by 8, the voltage at node 328 is applied to the positive input terminal (node 332) of operational amplifier 330.

If the voltage appearing at node 236 is greater than the voltage appearing at node 272 (which corresponds to a condition where the resistance of lamp 204 is greater than the resistance r), the output of comparator 276 will be “
1'', and the outputs of NOR gates 254 and 260 are ``1'' and ``0'', respectively. This causes node 296 to become node 3.
08, and node 319 is separated from node 308.

In this condition, the higher voltage at node 296 controls the voltage at node 308 and thus node 332 (the positive input terminal of operational amplifier 330).

Current sensing coil (current transformer) 216 and resistor 340.33
6 act to sense the magnitude of the current through lamp 204 and transistor 202 and generate a voltage at node 334 (the negative input terminal of operational amplifier 330) corresponding to this current level.

Operational amplifier 330 or its input terminal (im332, 334
) to generate a bias level at its output terminal (node 350). This bias level ensures that when switch 322 is on (coupled to node 319 or node 308), transistor 20
A relatively weak bias is applied to the gate of 2 (node 354), or if switch 306 is on (coupled to either node 296 or node 308), a relatively strong bias is applied to the gate. In either case, a feedback loop including sensing coil 214 and operational amplifier 330 attempts to control a relatively constant current through lamp 204 and transistor 202.

A negative voltage generator 648 is shown in FIG.
- This includes inverters 650, 654, multiple inverters 668.1 and 662, 666, and capacitors 658.
, 678, 688, 690 and diodes 682, 68
4 makes 474. Inverter 668 essentially acts as a driver with the desired driving capability. Inverter 6
50,654, resistor 662,666 and capacitor 65
The combination of 8 essentially acts as an oscillator. All inverters are powered by connecting them between +Vbat and -Vbat in FIG. capacitor 67
8 acts as an AC coupling effect. Diodes 682, 684 act as rectifiers, and capacitors 688, 690 act as filters. Output voltage generated at node 686 -
Va is a negative voltage having a magnitude approximately equal to +Vbat minus about 1.6 volts. Vbat=+
If it is 12 volts, -Va=-10,4 pol]. The negative voltage generator 648 is the operational amplifier 330 of FIG.
It is useful for generating -Va, which is used to supply electricity.

11, a typical embodiment of operational amplifier 330 of FIG. 9 is shown. The resistance shown (resistance 390.392
) is used to control the gain of amplifier 330, which is not shown in FIG.

In FIG. 12, a soft start solid state switch 400 according to one embodiment of the invention is shown within a dashed box. Switch 400 is an n-channel MOSFET
402.2 human power comparator 438, multiple clock type two-person Kanoa gates 464, inverters 450, 458, 5
06, Nando Ge-1-454, 494, 496, p-
n-p type bipolar transistor 470, 472, 4
74°478, diodes 422, 424, resistor 410
゜414.430,431,434,436,446.
448, potentiometer 418 and bypass capacitor 5
02,504. A power source, typically the positive terminal of a car battery +Vbat 402, is connected to the first terminal of a light 204 (typically a car headlight), resistor 41
0,480,482 first terminal, transistor 476
．． 478 and the first terminals of capacitors 502 and 504. Negative terminal of power supply - Vbat40
4, source of transistor 402, resistor 431.43
6,448 first terminals, clocked NOR gate 46
4, and the capacitors 502, 5.
04's second terminal. The clocked NOR gate 1-464 effectively acts as a clocked inverter. The reason why nineteen gates 464 are used is to provide the driving capability necessary to strongly bias transistor 402 on. The switch 468 is typically a manual switch provided in the passenger compartment of an automobile, but the first
terminal or first input terminal of switch 400 and node 484
The second terminal 448 is coupled to ground potential. Typically this potential is the same as -Vbat.

Transistor 402 controls the current through lamp 404, and when switch 486 is turned on (position shown in FIG. 12), transistors 470.472 and 476.478
Transistor 402 is weakly biased on by supplying a substantially constant current to gate terminal 408 from a constant current source of 1η. As will be explained later, when current flows through the lamp 404, its resistance value is monitored. When the impedance level of the lamp 404 reaches a preselected level, the weak, substantially constant current bias applied to the gate terminal 408 is turned off and the clocked (gated) NOR gate 46 is turned off.
4, a strong (fully on) bias is applied to the gate terminal 408. Control of the current flowing through transistor 402 and lamp 404 is provided by transistor 12 and load 32 in FIG.
1, the substantially constant current source of FIG. 1 selectively biases the gate of transistor 12 to control a relatively low level of constant current through transistor 12 and load 32. Instead of generating a current, transistor 402 can be selectively weakly biased to allow the current through transistor 402 and lamp 404 to build up continuously at a substantially constant level. The difference is that it uses a current source. In any embodiment,
The relatively low level of current −4l − flow between the load (lamp) and the current control transistor is used to first heat the negative l1:f (lamp);
Then its impedance (resistance value) is increased. When the resistance of the load (lamp) reaches a preselected level, the bias applied to the current control transistor is increased significantly so that the transistor is fully biased on. When the transistor is fully biased on, a current spike is generated. The magnitude of the current spike is much smaller than it would be if the transistor were not turned on weakly initially. This reduces cost because the area of the transistor can be much smaller than if the transistor had to safely pass much larger currents.

A second terminal of lamp 404 is coupled to a train of transistor 402, a first terminal of resistor 430, and node 406.

A second terminal of resistor 430 is coupled to a first terminal of resistor 434, a second terminal of resistor 431, and i'i 432. a second terminal of resistor 410 or a first terminal of resistor 414;
It is coupled to a first terminal of potentiometer 416 and terminal 412 .

A second terminal of resistor 414 is coupled to a second terminal of resistor 436 , a second terminal of potentiometer 418 , and node 420 . A wiper member 418 of potentiometer 416 is coupled to the cathode of diode 422 , the anode of diode 424 , a first (positive) input terminal of comparator 438 , a first terminal of resistor 446 , and node 426 . The second resistor 434
, the anode of diode 422, the cathode of diode 424, the second (negative) input terminal of comparator 438, and node 4.
28. The output terminal of the comparator 438 is the resistor 42
2, the input terminal of inverter 450 and node 4
40. The second of resistors 442, 446, 448
The output terminal of is coupled to node 444. inverter 450
is coupled to a first input terminal of NAND gate 454 and node 452 . An output terminal of NAND gate 1-454 is coupled to an input terminal of inverter 458, a first terminal of resistor 466, and node 456. Inverter 458
The output terminal of is the control terminal of Noah game 1-464 and node 4
60. The second output terminal of resistor 466 is the base of transistor 470.472, transistor 470
is coupled to the collector and node 468. transistor 4
The collector of 72 is coupled to the output terminal of clocked NOR gate 1-464, the gate of transistor 402, and node 408. The emitter of transistor 472 is coupled to the collector of transistor 476, the base of transistors 476 and 478, and node 474. )・Langister 470
The emitter of the transistor 478 and the node 47
5.

The first input terminal of the switch 400 is the second terminal of the resistor 482, the first input terminal of the gate 494, and the switch 486.
is coupled to a first terminal of and node 484 . switch 40
A second input terminal 492 of zero is coupled to a second terminal of resistor 480 and a first input terminal of NAND gate 496 . A second input terminal of gate 494 is coupled to the output terminal of gate 1-496 and node 500. A second input terminal of gate 496 or an output terminal of gate 494 is coupled to a terminal of the second input of NAND gate 454, an input terminal of inverter 506, and node 498. An output terminal of inverter 506 is coupled to a second input terminal of gate 464 and node 508 .

NAND games h494,496 are cross-coupled to form a flip-flop circuit. This helps limit switch 486 bounce. When switch 486 is in the closed position and the wiper arm contacts node 484,
The output of node 498 is “IM.” This “1” is coupled to the input terminal of inverter 506 and one input terminal of NAND gate 454.

Inverter 506 inverts the "1" input signal, thus applying a "0" to the second input terminal of gated NOR gate 464. At this time, it is assumed that a "1" signal exists at node 460. Therefore, gate 464 is off and the output is high impedance. Therefore, transistor 40
Gate 2 408 is now substantially disconnected from gate 1-464. “1” in node 460 is “0” in node 456
”. This is because inverter 458 couples these two nodes. With node 456 at “0”, the current from Vbat flows through transistor 478.
, 470. A mirror current of this current flows through transistors 476, 472 and into the gate of transistor 402 (node 408), weakly biasing it on. Therefore, current flows from +Vbat back to -Vbat through iJ' 404 and i-transistor 402. Transistor 472.47B continues to provide a substantially constant amount of current to the gate of transistor 402, which increases the voltage at node 408, thus increasing the bias on transistor 402. This increases the current through lamp 404 and transistor 402. When current flows through the lamp 404, its resistance value increases from the low level at "low temperature" to "
[: rises to a high level when the temperature is high. Resistance 410, 414
, 436, 442, 446, 448 and potentiometer 416 sets a reference voltage at node 426 (the positive input terminal of comparator 438) corresponding to the preselected resistance value. The combination of resistors 430, 431, 434 is the light 4
The voltage corresponding to the resistance value of 04 is set at node 428 (comparator 438
negative input terminal).

Assume that light 404 is in the off state and then switch 486 is closed to turn light 404 on. When current flows through lamp 404, its resistance increases and the voltage at the negative input terminal of comparator 438 (node 428) or correspondingly increases with respect to the positive input terminal of comparator 438 (node 426). Rise.

While node 428 is less than or equal to the voltage at node 426, the output terminal of comparator 438 (node 440) is at a logic “
0''. This 0'' is inverted by inverter 450, so that a ``1'' appears at node 452 (the second input terminal of NAND gate 454). As previously mentioned, when switch 486 is closed (as shown), a "1" is applied to the first input terminal (node 498) of NAND game 1-454. Two “1” input signals are NAND gate 45
4 results in a "0" output signal at node 456 the first time switch 486 is closed to turn on lamp 404.

As current continues to flow through lamp 404 and the current level increases, the voltage at node 428 increases -I- until it exceeds the voltage at node 426. Then node 44 of comparator 438
The output signal of 0 changes from "0" to "1". This causes the second input terminal of NAND gate 454 to go to "0", resulting in the output terminal of NAND gate 1-454 to go to "1".

This "1" potential level is human body +Vbat.

Therefore, no current flows through the transistors 470 and 478. Therefore, the gate of transistor 402 (node 408
), the current through transistors 476 and 472 is cut off. 1" at node 456 is inverted by inverter 458, so there is an "O" at node 460, and gate 464 is clocked on. As previously stated, all second input terminals -Vbat , so that the gates 1-466 essentially operate as clocked inverters.The gates 1-464 invert the "0" input signal at its respective first input terminal (node 508); generates a "1" at node 408 (gate of +- transistor 402). This biases transistor 402 strongly on, resulting in an initial current spike that then decreases over time until lamp 404 and a steady state current through transistor 402.

It should be understood that the specific designs described in Section 2 are merely examples, and are merely illustrative of the scope of the invention. Various changes can be made to the specific design in accordance with the ideas of the invention. For example, an n-channel transistor used to control the current through a lamp may be a p-channel transistor or an n-p-n or p-n-p bipolar transistor with the correct polarity of the power supply and appropriate bias. Please understand that you may use . Additionally, other suitable voltage and current sensing circuits and various comparator circuits and amplifiers may be used. Additionally, the novel switch of this invention can be used to control viscous or inverted loads or solenoids.

[Brief explanation of the drawing]

? Figure 81 is a graph showing the current flowing through a series circuit of a transistor and a lamp versus time in a conventional control circuit, Figure 2 is a graph showing the junction temperature of a transistor in a conventional circuit versus time, and Figure 3 is a graph showing this graph. A circuit diagram of a soft start solid state switch according to one embodiment of the invention, FIG. 4 is a graph showing the current through the circuit of FIG. 3 versus time, and FIG. 5 is a graph showing the temperature of the transistor of the switch of FIG. 3 versus time. Graph shown for 6th
The figure is a circuit diagram showing another example of a part of the switch in Figure 3,
7 is a circuit diagram showing still another example of a part of the switch in FIG. 3; FIG. 8 is a circuit diagram of an embodiment of the logic circuit in FIG. 3;
9 is a circuit diagram of a soft star 1 switch according to another embodiment of the present invention, FIG. 10 is a circuit diagram of a negative voltage generator that can be used with the switch of FIG. 9, and FIG.
Schematic diagram of an operational amplifier, which serves as a component of the switch in Fig.
FIG. 12 is a circuit diagram of a soft start switch according to yet another embodiment of the invention. [main? Explanation of C] 12.14.16+h transistor 18: comparator 22: logic circuit 24: voltage multiplier circuit 32: load

Claims (1)

[Claims] 1. In a circuit connected to a load whose impedance increases non-linearly when turned on, the circuit has a control terminal and first and second output terminals, and one output a device selectively coupled to the control terminal of the device such that the current flowing through the device from one output terminal to the other output terminal can be controlled by a bias applied to the control terminal; a first biasing means for selectively biasing the device on such that a current flows therein; and a first biasing means selectively coupled to a control terminal of the device such that a current greater than that permitted by the first biasing means flows. a second biasing means for selectively biasing the device in a manner coupled to a second output terminal of the device, the second biasing means being coupled to a second output terminal of the device for effectively detecting the impedance of the load and for preselecting the impedance of the load; A first biasing means controls the current through the device when the impedance of the load is at or below the preselected level, and a second biasing means controls the current through the device when the impedance of the load is above the preselected level. a detection and coupling/decoupling means for coupling the first biasing means or the second biasing means to bias said device on while simultaneously decoupling the other so as to do so. 2. The circuit of claim 1, wherein said device is a field effect transistor (FET). 3. The device is made of n-channel metal oxide silicon (M
3. The circuit according to claim 2, which is an OS) FET. 4. The circuit of claim 3, wherein said MOSFET has at least first and second sources. 5. The circuit of claim 4, wherein the first biasing means is coupled to the first and second sources and gates of a MOSFET, wherein the first biasing means comprises a resistor, an operational amplifier, and a first reference. means for setting a voltage, the first terminal of the resistor being connected to the first input terminal of the amplifier and the MOSFET.
ET, a second terminal of the resistor is coupled to a second source of the MOSFET, and means for setting a first reference voltage is coupled to a second input terminal of the amplifier; 6. The circuit of claim 5, wherein the output terminal of the amplifier is coupled to the gate of a MOSFET. 7. The circuit of claim 6, wherein said second biasing means includes means for setting a second reference voltage. 8. The circuit according to claim 7, wherein the means for setting the second reference voltage is a voltage multiplier circuit. 9. The detection and coupling/decoupling means is configured such that the first input terminal is coupled to the second source of the MOSFET and the second input terminal is coupled to a third source corresponding to a preselected value of the impedance of the load. It consists of a comparator coupled to a reference voltage, a logic circuit, and first and second coupling/decoupling devices, each of which has a control terminal and a first and second coupling/decoupling device. an output terminal of the comparator is coupled to the logic circuit, a first terminal of the logic circuit is coupled to a control terminal of the first coupling/decoupling device, and a second terminal of the logic circuit is coupled to the control terminal of the first coupling/decoupling device. an output terminal coupled to a control terminal of a second coupling/decoupling device;
the output terminals of the second coupling/decoupling device are coupled to the output terminal of the amplifier and the gate of the MOSFET, respectively;
and a second output is connected to the second biasing means and the MO
5. The circuit of claim 4, wherein the circuit is coupled to the gate of the SFET. 10. The logic circuit includes means for enabling the circuit and biasing the first coupling/decoupling device on and the second coupling/decoupling device when the load impedance is at or below the preselected level. biasing the second coupling/decoupling device off and biasing the second coupling/decoupling device on and the first coupling/decoupling device if the impedance of the load is higher than the preselected level. 10. The circuit of claim 9, further comprising first means for biasing off. 11. A circuit connected to a load whose impedance increases nonlinearly when turned on, which has a control terminal and first and second output terminals, and has a control terminal and first and second output terminals, and has a control terminal and a first output terminal and a second output terminal. a device such that the current flowing through the device can be controlled by a bias applied to a control terminal; and a device selectively coupled to the control terminal of the device, and a preselected substantially constant current flowing through the device. substantially constant current generating means for selectively biasing the device on so that the current flows;
biasing means selectively coupled to a control terminal of the device for selectively biasing the device to conduct a current greater than the constant current; and a biasing means coupled to a second output terminal of the device; Constant current generating means control the current through the device when the impedance of the load is at or below a preselected level, and biasing means control the current through the device when the impedance of the load is above the preselected level. sensing and coupling/decoupling, effectively sensing the impedance of said load to control current and coupling constant current means or biasing means to bias said device on and decoupling the other; A circuit having means. 12. A circuit connected to a load whose impedance increases nonlinearly when turned on, which has a control terminal and first and second output terminals, and has a control terminal and first and second output terminals, and has a control terminal and a first output terminal and a second output terminal. a device selectively coupled to the control terminal of the device such that the current flowing through the device can be controlled by a bias applied to a control terminal of the device; constant current biasing means selectively coupled to the control terminal of the device for selectively biasing the device on such that a substantially constant current flows into the control terminal such that the constant current biasing means strong biasing means for selectively biasing said device on more strongly than said device;
low current means is coupled to the output terminal of the device and controls the current through the device when the impedance of the load is at or below the preselected level and the impedance of the load is above the preselected level. When the strong biasing means controls the current through the device, the impedance of the load is effectively sensed and the constant current biasing means or the strong biasing means are coupled to bias the device on and the other detection and coupling/decoupling means for decoupling. 13. In a current control means for controlling the current passing through a load whose impedance is nonlinear upon turn-on,
having a control terminal and first and second output terminals;
a device such that the current passing through the device from one output terminal to another output terminal can be controlled by a signal applied to a control terminal; current detection means for detecting the current passing through the device; a reference level representative of a desired current flow through the device; and selectively coupled to a control terminal of the device, the current through the device is approximately equal to the reference level. As it turns out,
first comparing and generating means for generating a signal modifying the current through the device, a second output terminal of the device being connected to a load, and further comprising: a voltage at the second output terminal of the device; a reference voltage representative of a preselected level of impedance of a load; and means for comparing a voltage at a second output terminal of the device with the reference voltage to determine a voltage at the second output terminal of the device. a second output signal for generating a first output signal when the voltage is higher than the reference voltage; and a second output signal for generating a different second output signal when the voltage at the second output terminal of the device is equal to or less than the reference voltage; a comparison means, a voltage generation circuit, first and second switching devices each having a control terminal and first and second output terminals, an output terminal of the second comparison means and the first and second switching devices; a logic circuit coupled to a control terminal of a switching device; a second output terminal of the first and second switching device is coupled to a control terminal of the device; a logic circuit coupled to a control terminal of the first switching device; 1
is coupled to an output terminal of the voltage generating circuit, a first output terminal of the second switching device is coupled to an output terminal of the first comparing means, and the logic circuit is coupled to the output terminal of the second switching device. and the voltage at the second output terminal of the device is equal to or less than the reference potential;
said first comparing and generating means are coupled for comparison and said first switching device causes said voltage generating circuit to selectively coupling the voltage generation circuit to the control terminal of the device and the first comparison when the voltage at the second output terminal of the device is higher than the reference voltage; Current control means isolating means. 14. In a circuit connected to a circuit whose resistance value increases non-linearly when turned on, the circuit has a control terminal and first and second output terminals, and the first output terminal is connected to a load. a first biasing means selectively coupled to a control terminal of the transistor to selectively enable the transistor to facilitate current flow through the transistor and a load; second biasing means selectively coupled and selectively enabling said transistor to facilitate a flow of current through said transistor and load of a magnitude greater than that caused by said first biasing means; the first and second biasing means are adapted to be connected to a load and are coupled to the first and second biasing means to effectively detect the resistance of the load and to adjust the resistance of the load to a preselected level or lower; When lower, the first
biasing means are coupled to the control terminal of the transistor, and when the resistance of the load is above the preselected level, a second biasing means is coupled to the control terminal of the transistor. A circuit comprising resistance sensing and coupling/decoupling means for coupling a biasing means or a second biasing means to a control terminal of said transistor and decoupling the other. 15. In a circuit connected to a load whose resistance value increases non-linearly when turned on, the circuit has a control terminal and first and second output terminals, and the first output terminal is connected to the load. a first biasing means selectively coupled to a control terminal of the transistor to selectively enable the transistor to facilitate current flow through the transistor and the load; , a second biasing means selectively coupled to a control terminal of the transistor and selectively enabling the transistor to facilitate a flow of current through the transistor and the load of a magnitude greater than that caused by the first biasing means; biasing means, a resistance sensing means connectable to the load for sensing the resistance of the load, and a first resistance sensing means connectable to a reference level corresponding to a preselected resistance.
and a second input terminal coupled to the resistance value detection means, for comparing the resistance value of the load with a reference value;
a comparator generating a first signal at an output terminal when the resistance value of the load is less than or equal to the reference level and generating a different second signal when the resistance value of the load is greater than the reference level; first and second coupling/decoupling means for selectively coupling or decoupling the first and second biasing means to a control terminal of the transistor; an input terminal coupled to an output terminal of the comparator; a logic circuit whose first and second output terminals are respectively coupled to a control terminal of the first coupling/decoupling means and a control terminal of the second coupling/decoupling means; If the resistance of the load is equal to or less than the reference level, the first coupling/decoupling means couples the first biasing means to the control terminal of the transistor and the second coupling/decoupling means isolating (decoupling) the second biasing means from the control terminal of the transistor by and coupling the second biasing means to the control terminal of the transistor when the resistance of the load is greater than the reference level; A circuit for isolating a first biasing means from a control terminal of said transistor. 16. The circuit of claim 15, wherein the transistor is a field effect transistor. 17. Claim 16, wherein the field effect transistor is an n-channel metal oxide semiconductor (MOS) transistor.
The circuit described. 18. Claim 17, wherein each of said first and second coupling/decoupling means comprises at least one MOS transistor.
The circuit described. 19. The circuit of claim 17, wherein the load is an incandescent lamp. 20. A load characterized by having a non-linear impedance when turned on, a power supply having an output terminal, a control terminal, and first and second output terminals, the power source having a control terminal and first and second output terminals, the power source having a non-linear impedance when turned on; a device capable of controlling a current flowing through the device to an output terminal of the device by a bias applied to a control terminal, the first terminal of the load being connected to the first output terminal of the device; coupled, an output terminal of the power source being coupled to a second output terminal of the device and a second terminal of the load, and further coupled selectively to a control terminal of the device, through the device and the load. a first biasing means selectively coupled to a control terminal of the device to selectively bias the device on such that current flows; and a first biasing means selectively coupled to a control terminal of the device such that the level of current through the device and the load a second biasing means for selectively biasing said device to be greater than a current caused by said device, said second biasing means being coupled to a second output terminal of said device, the impedance of said load being at or above a preselected level; the first biasing means controls the current through the device when the impedance of the load is greater than the preselected level; sensing and coupling/decoupling means for effectively sensing the impedance of the load and coupling the first biasing means or the second biasing means to bias the device on and decoupling the other; circuit with. 21, the device is an n-channel metal oxide semiconductor (M
21. The circuit of claim 20, wherein the load is an incandescent lamp.