JPS63304174A - Zero-phase current detecting method - Google Patents

Abstract

PURPOSE:To detect a zero-phase current without being influenced by a zero- phase residual current, by obtaining the third zero-phase current by subtracting from the first zero-phase current of a zero-phase current transformer, the second zero-phase current which is delayed by a prescribed time from the first zero- phase current. CONSTITUTION:A zero-phase current 3i0 detected by a current transformer flows into a resistance R1 from an input terminal 10, and converted to a voltage Vi0. The input voltage Vi0 inputted to an amplifier 12 is multiplied by R5/R4 and outputted, and it is supplied to a CCD1 13, and brought to sampling successively. As for outputs of the CCD1 13, one of them is provided directly to a positive input terminal of a subtracter 15, and the other is delayed by a prescribed time through a CCD2 14, and thereafter, provided to a negative input terminal of the subtracter 15, in which a difference of the output of the CCD1 13 and the output of the CCD2 14 is calculated. Unless there is a variation in the zero-phase current 3i0, an output of the subtracter 15 is '0'. If a sudden variation is generated in the zero-phase current 3i0, a variation portion of an output current of the CCD1 13 appears in the output of the subtracter 15 within a prescribed time.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to detecting zero-sequence current in an AC line, and more specifically, detects zero-sequence current caused by unbalance in a zero-sequence circuit of an AC line that exists in a steady state. This invention relates to detecting a zero-phase m current that eliminates the effects of residual current and zero-phase residual one-current mutual current caused by differences in characteristics of current transformers.

<Prior art> For example, in a three-phase AC line, the zero-sequence current that occurs in the event of a ground fault in the line has been conventionally measured as shown in Figure 3 (a).
It was detected using method (b). In other words, the same figure (in that case, six current transformers (hereinafter referred to as CT) with the same rating) (
52), the quadratic (or 6
Next) Connect the coils in parallel, and in the figure, each C
The secondary currents of T(52) are ja and ib, respectively.

If it is lc is + ib + ic = 3 i.

The aim is to detect the zero-sequence current.

This principle states that when the three-phase electric circuit (51) is operating normally, 3io=O, but if a ground fault occurs in the a-phase of the electric circuit, for example, the CT secondary current ja of the a-phase becomes (= ia 1 ia ), 3 jo = i'
This is based on the fact that a zero-sequence current can be obtained as a + ib + lc = le. Note that 54 indicates a three-phase current measuring device using, for example, an ammeter.

In addition, in the case of the same figure (b), a three-phase electric line (51) is connected to a so-called zero-phase current transformer (CT (62)) in which a secondary coil (64) is formed in a toroidal shape around one annular core (66). 6
If the currents of each phase of the three-phase circuit are Ia, Ib, and Ic, the magnetic fluxes generated by these are combined in the iron core (63), and as a result, N:2
The aim is to obtain a zero-phase current of 3io as the number of turns of the next coil, but the principle is almost the same as the case (a) above.

<Problems to be solved by the invention> Among the above conventional methods, the method shown in Figure 3 (a) uses six standard CTs and connects these secondary (or sixth) coils in parallel. Zero-sequence current can be obtained by a simple method. However, the CT's ratio error (5) and phase error (for example, as shown in Figure 7, change depending on the magnitude of the CT's primary current. For this reason, if a zero-phase single current is not generated in a three-phase circuit) However, when there is a difference in the current value of each phase, the ratio error and phase error of CT of each phase are not the same,
Therefore, in addition to producing a zero-sequence residual current due to the fact that the sum of each instantaneous value does not become zero, if there are variations in characteristics (ratio error and phase error) among the three-phase CTs, this may occur. A zero-sequence residual current also occurs, and these zero-sequence residual currents flow through each of the three phases. There is a troublesome problem that the current increases or decreases as the value of the Lm current (the primary current of the CT) increases or decreases.

Next, a method using a zero-phase current transformer (62) shown in FIG. 3 (05) will be explained. In this method, each CT
Although the zero-sequence residual current due to variations in the characteristics of is suppressed,
Nonuniformity in characteristics due to stress and shock during manufacturing of the annular core (63) (which generally has a wound core structure using grain-oriented silicon steel plates) and nonuniformity in the geometrical arrangement of the three-phase conductor (61) Depending on the object and other factors, there is still a problem in that a residual current is generated which increases or decreases with the increase or decrease in each phase current value (not including the zero-phase one current) of the three-phase circuit.

In addition, as mentioned above, zero-phase current transformers have six main circuit conductors all passing through the limited window part of one iron core, so the insulation strength of the main circuit conductors must be high, and There is also the problem that mounting locations are limited for practical use. Furthermore, although this is not a problem with the characteristics of the CT, if there is a slight unbalance in the zero-sequence circuit of the three-phase electric circuit in a steady state, a zero-sequence residual current is generated due to this.

Moreover, when trying to detect zero-sequence current due to a ground fault in an electrical circuit, the minimum value that can be detected must naturally be larger than these zero-sequence residual currents, and the zero-sequence current detection sensitivity will decrease by the zero-sequence residual current. There's a problem.

The above explanation was about three-phase electric circuits, but other general electric circuits (
It is clear that similar problems exist in single-phase and polyphase circuits.

<Means for Solving the Problems> The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a device for detecting zero-sequence current in which the influence of zero-sequence residual current is eliminated.

For the above purpose, the present invention has a configuration as shown in FIG. That is, the first zero-sequence current (3
)(3io) through the delay element (1) to generate a second zero-sequence current (4) that delays the first zero-sequence current (3) by a certain period of time (for example, an integral multiple of the frequency of the zero-sequence current). The first and second zero-sequence currents are input to a subtracter (2), and the third zero-sequence current is obtained by subtracting the second zero-sequence current from the first zero-sequence current. The configuration is such that a zero-sequence current (5) of . Note that for the first and second zero-sequence currents, alternating current signals may be used directly, or if only the magnitude needs to be detected, a direct current signal obtained by rectification may be used.

According to the configuration of the present invention, when the electric circuit is in a normal state and the tta current in the electric circuit is constant and unchanged, the zero-sequence residual current is also constant and unchanged. Therefore, the first and second zero-sequence currents (3) and (4) have the same value, and the third zero-sequence current (5), which is the output of the subtracter (2), becomes 0 (zero). Furthermore, the current flowing through the circuit in a steady state is not necessarily constant, but increases and decreases over time, but the changes are very gradual.
Since it gradually increases and decreases, the zero-sequence residual current also gradually increases and decreases accordingly. However, here, the delay time of delay element (2) is sufficiently shorter than the increase/decrease cycle of the current flowing through the circuit, but is sufficiently longer than the change time of the zero-sequence current at the time of a ground fault (for example, about 1 to 2 seconds). If set to , the subtracter (
The third zero-sequence current (5), which is the output of step 2), becomes approximately 0 (zero).

On the other hand, if the first zero-sequence current suddenly changes due to a ground fault occurring in the electrical circuit, the second zero-sequence current will remain in the previous state for the delay time of delay element (2). is maintained, so there is no change, and therefore the third zero-sequence current (5) output from the subtracter (2) becomes a zero-sequence current generated due to a ground fault or the like.

FIG. 2 and FIG. 3 are diagrams showing the operation of the present invention. To explain this, first of all, (a) in FIG.
This is a case where the fault current (a) flowing to the fault point due to a ground fault or the like occurs in the same phase as the normal zero-sequence residual current. (B)
is the first zero-sequence current (b), which is the zero-sequence residual current that always occurs up to the point A where an earth fault occurs, and after point A, it is the composite current with the fault current (a) in (a). (C) and (c)
>(b). (c) is the second zero-sequence current (b') obtained by delaying the first zero-sequence current (b) in (b) by a certain time T using a delay element, and the composite current (C'); (a) shows the output waveform (d) of the subtracter.

In this way, the output waveform (cl) of the subtracter appears only during the delay time T of the delay element, and is equal to the fault current (a).

By the way, since the zero-sequence residual current is generated due to the cause mentioned above (the problem that the invention aims to solve), the phase relationship between the zero-sequence residual current ('b) and the fault current (a) is determined by the combination of each CT. In addition, it is not constant for each side of the zero-phase current transformer, and is completely indeterminate. Therefore, the relationship between the fault current (a) and the zero-sequence residual current (b) will be in opposite phase as shown in Figure 3, and as a result, the composite current (C) may become smaller than the zero-sequence residual current (b). According to the present invention, as shown in FIG. 3), the same signal as the fault current (a) is obtained during the delay time T of the delay element.

<Example> An example of the present invention will be described with reference to FIGS. 3 and 4. FIG. 4 shows a circuit in which a charge transfer device (hereinafter referred to as CCD) is used as a delay element, and the operation of this circuit will be explained below. The zero-sequence current 3io detected by the current transformer flows into the resistor R1 from the input terminal αG, where it is converted into a voltage Vio proportional to 3io.

The input voltage Vio is supplied to the connection point between the bias resistors R2 and R3 via the DC blocking capacitor o1), and is input as a DC signal to the positive input terminal (G) of the amplifier 0 via the input resistor R4. -The negative input terminal ←) is connected to earth E (zero volts). R5 is a feedback resistor, which together with input resistor R4 determines the amplification factor of this amplifier. Note that +VCC and -Vcc are direct currents with earth E as zero volts! This is the power supply for circuit operation. The input voltage Vio input to the amplifier (2) is R54
It is multiplied by ゜(amplification factor of amplifier @) and output, and this is CC
The signal is supplied to D1Q3, where it is sequentially sampled by the clock pulse applied to terminal 2D, and output. C.C.
D+ (13 is a kind of sample and hold circuit as shown in Fig. 5 (a), which detects the input voltage (V
It has a function of sampling and storing io) and outputting the sampled value of the music cycle with the next clock pulse, as well as sampling and storing a new input voltage, and is composed of a memory element) and a Vaffa circuit. One of the outputs of CCD1a3 goes directly to the positive input terminal (G) of subtractor α0, and the other goes to C
CD204), and after a certain time delay, the subtractor α9
is applied to the negative input terminal (→), and the difference between the output of CCD 1Q3 and the output of CCD 2
If there is no change, the output of CCD2α→ is the same in magnitude and phase as the output of CCD1 (to), and the output of subtractor 09 is 0 (zero). If a sudden change occurs in the zero-sequence current 3io, the output of CCD1α3 changes, but the output of CCD2Q4) does not change for a certain period of time. Therefore, within a certain period of time, the output of subtractor 0e (terminal Q
fll) will represent the change in the output current of CCD1 (13).Also, if the zero-sequence current 3io changes slowly over a much longer time period than the delay time of CCD2Q4), the output of CCD1α3 will also change due to the change in the output current of CCD2α. The output also changes substantially in the same way, and the output of the subtracter 0υ becomes 0 (zero). Figure 5 (b) shows an example of the configuration of CCD2α feeding, which includes an m-phase CCD c3υ and a Vaffa circuit (6
) are connected in series, and the total is mxn.
It constitutes a digit shift register. and terminal c2℃
Since the output for each clock pulse added to is obtained from the n-th buffer circuit, the output signal of CCD1Q3 applied to the input terminal has a clock pulse period x
The output will be delayed by m x n CCD
The number m of phases and the number n of series connections of the 2Q(4) CCDs may be appropriately determined depending on the value of the required delay time.

In this embodiment, CCI)2Q4) was explained using the configuration shown in FIG.
A similar result can be obtained with a parallel-serial system (parallel-serial system), and a so-called delay line may be used in addition to a CCD as a delay element, and furthermore, a microcomputer may be applied to perform digital processing. Of course, any other delay element may be used as long as it meets the gist of the present invention. When using a tazo delay line,
A sample and hold circuit such as the CCD1α3 in FIG. 4 is unnecessary and omitted.

<Effects of the Invention> The present invention provides a method for connecting current transformer secondary (or sixth) coils in parallel or from the first zero-sequence current obtained by a zero-phase current transformer.
Since the third zero-sequence current is obtained by subtracting the second zero-sequence current obtained by delaying the first zero-sequence current for a certain period of time, the zero-sequence current is Phase current (fault current) can be detected, especially the 3rd phase current.
As shown in the figure, a zero-sequence current (fault current) occurs in the opposite phase to the zero-sequence residual current that always exists, and the combined current with the zero-sequence residual current becomes smaller than the normal zero-sequence residual current. It is possible to obtain effects that cannot be obtained with conventional methods, such as being able to detect zero-sequence current (fault current) even in cases where

[Brief explanation of the drawing]

FIG. 1 is the basic configuration of the present invention, FIGS. 2 and 3 are waveform diagrams showing the operation and effects of the present invention, FIG. 4 is a specific embodiment of the present invention, and FIG. 5 is a sample and hold circuit and An example of the configuration of a delay element, FIG. 3 is an explanatory diagram of a conventional method, and FIG. 7 shows an example of current characteristics of a general current transformer. 1... Delay element 2... Subtractor 3... First zero-sequence current 4... Second zero-sequence current 5... Third zero-sequence current

Claims (1)

[Claims] 1) A first zero-sequence current detected by a current transformer installed in an AC line, and a delay of a certain time from the first zero-sequence current obtained by passing this first zero-sequence current through a delay element. A third zero-sequence current obtained by subtracting the second zero-sequence current from the first zero-sequence current is inputted into a subtracter provided after the delay element. Zero-sequence current detection method that outputs.