JPS6329834B2 - - Google Patents
Info
- Publication number
- JPS6329834B2 JPS6329834B2 JP54162959A JP16295979A JPS6329834B2 JP S6329834 B2 JPS6329834 B2 JP S6329834B2 JP 54162959 A JP54162959 A JP 54162959A JP 16295979 A JP16295979 A JP 16295979A JP S6329834 B2 JPS6329834 B2 JP S6329834B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- collector
- base
- impurity region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 26
- 238000002955 isolation Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000969 carrier Substances 0.000 claims description 5
- 238000009825 accumulation Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は、高速スイツチングを行なうのに好適
な半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device suitable for high-speed switching.
例えば、TTL（Transistor Transistor Logic）
に於いて、出力側トランジスタがオン、即ち、飽
和状態ではコレクタ・ベース接合及びベース・エ
ミツタ接合が順方向バイアス電圧が印加され、そ
れ等接合にはキヤリヤが蓄積されている。そし
て、該トランジスタがオフになつた場合、そのキ
ヤリヤが消滅する時間に依り装置のスイツチング
速度が定められる。 For example, TTL (Transistor Transistor Logic)
When the output side transistor is on, that is, in a saturated state, a forward bias voltage is applied to the collector-base junction and the base-emitter junction, and carriers are accumulated in these junctions. When the transistor is turned off, the time it takes for its carrier to disappear determines the switching speed of the device.
従来、前記のようなキヤリヤを早く消滅させる
為に種々の開発がなされていて、例えば金などの
所謂ライフ・タイム・キラーを拡散するのもその
一つである。 Conventionally, various developments have been made to quickly eliminate carriers as described above, one of which is the diffusion of so-called life time killers such as gold.
本発明は、前記のような半導体装置に於いて、
トランジスタのオン・オフに対応してオフ・オン
するキヤリヤ流路をベースと接地間に設定し、ト
ランジスタがオンからオフに変つた際は接合に蓄
積されたキヤリヤを積極的に放出するようにし、
装置のスイツチング速度を向上させるものであ
り、以下これを詳細に説明する。 The present invention provides a semiconductor device as described above.
A carrier flow path that turns off and on in response to the on and off of the transistor is set between the base and ground, and when the transistor changes from on to off, the carrier accumulated in the junction is actively released.
This improves the switching speed of the device, and will be explained in detail below.
第１図は本発明一実施例の要部側断面図、第２
図は同じくその要部平面図である。 Fig. 1 is a side sectional view of the main part of one embodiment of the present invention, Fig.
The figure is also a plan view of the main part.
図に於いて、１はｐ型シリコン半導体基板、２
はn+型埋没層、３はｎ型コレクタ領域、４はp+
型分離領域、５はp-型不純物領域、６はｐ型ベ
ース領域、７はn+型エミツタ領域、８はn+型不
純物領域、９はシヨツトキ・バリヤ・ダイオード
（SBD）領域、３Ａはコレクタ・コンタクト領域
をそれぞれ示す。尚、n+型不純物領域８はコレ
クタ領域３と短絡されている。 In the figure, 1 is a p-type silicon semiconductor substrate, 2
is n + type buried layer, 3 is n type collector region, 4 is p +
Type isolation region, 5 is a p - type impurity region, 6 is a p type base region, 7 is an n + type emitter region, 8 is an n + type impurity region, 9 is a shot barrier diode (SBD) region, 3A is a collector・Indicates each contact area. Note that the n + type impurity region 8 is short-circuited to the collector region 3.
本実施例に於いて、コレクタ領域３が高レベル
従つてn+型不純物領域８も高レベル、ベース領
域６が低レベル、即ち、トランジスタがオン状態
になろうとするとき、コレクタ領域３とp-型不
純物領域５とで形成される第１のｐ・ｎ接合と、
p-型不純物領域５とn+型不純物領域８とで形成
される第２のｐ・ｎ接合のそれぞれから空乏層が
拡がつてベース領域６と分離領域４との間をピン
チ・オフしている。そこで、装置は有効にトラン
ジスタ動作をなし得るものである。逆に、コレク
タ領域３が低レベル従つてn+型不純物領域８も
低レベル、ベース領域６が高レベル、即ち、トラ
ンジスタがオフ状態になろうとするとき、前記第
１及び第２の接合からは殆んど空乏層は拡がら
ず、従つてベース領域６と分離領域４との間は接
続された状態に在るので、蓄積キヤリヤは迅速に
放出されてしまう。 In this embodiment, when the collector region 3 is at a high level, the n + type impurity region 8 is also at a high level, and the base region 6 is at a low level, that is, when the transistor is about to turn on, the collector region 3 and the p - a first p/n junction formed with type impurity region 5;
A depletion layer spreads from each of the second p/n junctions formed by the p - type impurity region 5 and the n + type impurity region 8 and pinches off between the base region 6 and the isolation region 4. There is. Therefore, the device can effectively perform transistor operation. Conversely, when the collector region 3 is at a low level, therefore the n + type impurity region 8 is also at a low level, and the base region 6 is at a high level, that is, when the transistor is about to turn off, there is no energy from the first and second junctions. Since the depletion layer hardly expands and therefore remains connected between the base region 6 and the isolation region 4, the stored carriers are quickly released.
ところで、前記実施例のようにn+型不純物領
域８を形成することなく、コレクタ領域３とp-
型不純物領域５とで形成されるｐ・ｎ接合から拡
がる空乏層でピンチ・オフすることは出来なくは
ないが、コレクタ領域３が低レベルのときにベー
ス領域６と分離領域４との間に設定されるキヤリ
ヤ流路が本発明の場合の略1/2にならざるを得な
い（p-型不純物領域５の平面面積は同一とす
る）。尚、n+型不純物領域８はp-型不純物領域５
の全表面を覆うように形成されても良いことは勿
論である。 By the way, without forming the n + type impurity region 8 as in the above embodiment, the collector region 3 and the p - type impurity region 8 are not formed.
Although it is possible to pinch off the depletion layer that spreads from the p/n junction formed with the type impurity region 5, when the collector region 3 is at a low level, the The carrier flow path to be set must be approximately half that in the case of the present invention (the planar area of the p - type impurity region 5 is assumed to be the same). Note that the n + type impurity region 8 is the p - type impurity region 5.
Of course, it may be formed so as to cover the entire surface.
以上の説明で判るように、本発明に依れば、例
えばTTLのような半導体装置の出力側トランジ
スタに於いて、ベース領域と分離領域の間に該ベ
ース領域及び分離領域と同導電型で且つ低濃度で
ある不純物領域を形成し、その不純物領域の表面
の少なくとも一部を覆い且つコレクタ領域と共通
接続されコレクタ領域と同導電型である不純物領
域を形成してあり、トランジスタのオン時にはベ
ース領域と分離領域との間を空乏層を拡げてピン
チオフし、トランジスタのオフ時には空乏層を拡
げることなくベース領域と分離領域の間にキヤリ
ヤ流路を開通させ、トランジスタがオン中に蓄積
されたキヤリヤを速かに放出するようにしている
ので、半導体装置のスイツチング速度を向上させ
ることができる。即ち、前記出力側トランジスタ
がオフ状態からオン状態に切り替わつた直後に
は、前記ベース領域と前記分離領域との接続部分
に於ける抵抗の値を大きくしてコレクタ出力電圧
の立ち下がりを早めることに依り、出力の高レベ
ルから低レベルへの切り替えを急速に行うことを
可能にしている。また、オン状態になつてコレク
タ出力電圧の立ち下がりが進行するにつれて前記
接続部分に於ける抵抗の値が次第に小さくなるよ
うにし、立ち下がつた際のコレクタ出力電圧が低
レベルよりも更に低くなつてノイズとなるアンダ
シユートの発生を防止することができる。更にま
た、特に前記ベース領域と分離領域との間に在る
低濃度不純物領域の一部を覆いコレクタ領域と共
通接続された不純物領域を形成したことに依り、
空乏層は前記低濃度不純物領域の上下二方向から
拡がるので前記ベース領域・分離領域間の抵抗値
変化は大である。従つて、その部分に於ける抵抗
値に対する設計余裕は増大することになり、これ
は装置の微細パターン化に極めて有利である。そ
して、その装置を製造するには、従来慣用されて
いるリソグラフイ技術、不純物導入技術を適用で
き、その間には何等の困難もない。 As can be seen from the above description, according to the present invention, in an output side transistor of a semiconductor device such as a TTL, there is a region between a base region and an isolation region that is of the same conductivity type as the base region and the isolation region. An impurity region with a low concentration is formed, and an impurity region is formed that covers at least a part of the surface of the impurity region, is commonly connected to the collector region, and has the same conductivity type as the collector region, and when the transistor is turned on, the base region pinch-off by expanding a depletion layer between the base region and the isolation region, and when the transistor is off, a carrier flow path is opened between the base region and the isolation region without expanding the depletion layer, and the carriers accumulated while the transistor is on are pinched off. Since the gas is released quickly, the switching speed of the semiconductor device can be improved. That is, immediately after the output side transistor is switched from the off state to the on state, the value of the resistance at the connection portion between the base region and the isolation region is increased to hasten the fall of the collector output voltage. This makes it possible to quickly switch from high to low output levels. In addition, as the collector output voltage falls in the on state, the resistance value at the connection part is made to gradually become smaller, so that the collector output voltage when the voltage falls becomes even lower than the low level. It is possible to prevent the occurrence of undershoot, which becomes noise. Furthermore, by forming an impurity region that covers a part of the low concentration impurity region between the base region and the isolation region and is commonly connected to the collector region,
Since the depletion layer spreads from both the upper and lower directions of the low concentration impurity region, the change in resistance between the base region and the isolation region is large. Therefore, the design margin for the resistance value in that part increases, which is extremely advantageous for fine patterning of the device. In order to manufacture the device, conventionally used lithography technology and impurity introduction technology can be applied without any difficulty.
第１図及び第２図は本発明一実施例の要部側断
面図及び同じく要部平面図である。
図に於いて、１は基板、２は埋没層、３はコレ
クタ領域、４は分離領域、５はp-型不純物領域、
６はベース領域、７はエミツタ領域、８はn+型
不純物領域、９はSBD領域、３Ａはコレクタ・
コンタクト領域をそれぞれ示す。
1 and 2 are a side sectional view and a plan view of the main part of an embodiment of the present invention. In the figure, 1 is a substrate, 2 is a buried layer, 3 is a collector region, 4 is an isolation region, 5 is a p - type impurity region,
6 is a base region, 7 is an emitter region, 8 is an n + type impurity region, 9 is an SBD region, 3A is a collector.
The contact areas are shown respectively.
Claims (1)
ス領域及び分離領域と同導電型であると共にトラ
ンジスタがオンになつた場合には該ベース領域と
該分離領域との間に空乏層を広げてピンチ・オフ
し且つトランジスタがオフになつた場合には空乏
層を広げることなく該ベース領域と該分離領域と
の間にキヤリヤ流路を開通させてトランジスタが
オン中に蓄積されたキヤリヤを放出させるように
した低濃度である不純物領域と、 該不純物領域の表面の少なくとも一部を覆い且
つコレクタ領域と共通接続されそのコレクタ領域
と同導電型である不純物領域と を備えてなることを特徴とする半導体装置。[Claims] 1. A region between a base region and an isolation region, which is of the same conductivity type as the base region and the isolation region, and when the transistor is turned on, between the base region and the isolation region. When the transistor is turned off, a carrier flow path is opened between the base region and the isolation region without expanding the depletion layer to prevent accumulation while the transistor is on. an impurity region having a low concentration and configured to emit carriers; and an impurity region that covers at least a part of the surface of the impurity region, is commonly connected to the collector region, and has the same conductivity type as the collector region. A semiconductor device characterized by:
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16295979A JPS5685836A (en) | 1979-12-15 | 1979-12-15 | Semiconductor device |
| DE8080304070T DE3072002D1 (en) | 1979-11-14 | 1980-11-13 | An output transistor of a ttl device with a means for discharging carriers |
| EP80304070A EP0029350B1 (en) | 1979-11-14 | 1980-11-13 | An output transistor of a ttl device with a means for discharging carriers |
| US06/574,583 US4613887A (en) | 1979-11-14 | 1984-01-27 | Semiconductor device with a means for discharging carriers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16295979A JPS5685836A (en) | 1979-12-15 | 1979-12-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5685836A JPS5685836A (en) | 1981-07-13 |
| JPS6329834B2 true JPS6329834B2 (en) | 1988-06-15 |
Family
ID=15764523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16295979A Granted JPS5685836A (en) | 1979-11-14 | 1979-12-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5685836A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49110282A (en) * | 1973-02-20 | 1974-10-21 | ||
| JPS49110283A (en) * | 1973-02-20 | 1974-10-21 |
-
1979
- 1979-12-15 JP JP16295979A patent/JPS5685836A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49110282A (en) * | 1973-02-20 | 1974-10-21 | ||
| JPS49110283A (en) * | 1973-02-20 | 1974-10-21 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5685836A (en) | 1981-07-13 |
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