JPS6329396A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain high speed read by providing an amplifier circuit comprising a couple of MOSFETs of a 2nd conduction type having a comparatively small conductance where gates and drains are connected in crossing and an output circuit receiving an output signal of the amplifier circuit. CONSTITUTION:A read signal is amplified by using an amplifier circuit comprising a couple of MOSFETs of the 1st conduction type receiving a complementary input signal and having a comparatively large conductance and a couple of MOSFETs of the 2nd conduction type provided respectively to the drain of the former couple of the MOSFETs and having a comparatively small conductance where the gates and drains are in cross connection. That is, a data line D00 is coupled with a common data line CD0 via a MOSFETQ11 forming a Y gate and a common source line is connected to an earth potential point of the circuit via a switch MOSFETQ12. Since the signal level required for the output operation is formed at high speed, the operation is quickened.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in mask-type ROMs (read-only memories) in which writing is performed by ion implantation.

[Conventional technology]

A horizontal mask type ROM in which a storage MOS FET is formed at the intersection of a word line and a data line according to stored information is known (for example, Sanpo Publishing, ``How to Use IC Memory'', September 30, 1977) Co-authored by Tamatsuo and Oomote Ryo, see pages 73-76).

In this mask type ROM, either the gate insulating film of the MOSFET is formed too thick at the intersection of the word line and the data line and the MOSFET does not operate properly, or the gate insulating film is formed too thin. Memory information is written by forming a normally operating MOSFET.

[Problem that the invention seeks to solve]

Prior to the present invention, the inventors of the present application formed an aluminum data line on the surface of the channel region of a MOSFET by ion implantation, and then introduced an impurity of the same conductivity type as the substrate gate, thereby achieving a large threshold. We have developed a mask-type ROM that performs writing by forming a memory MO3FET that has a value voltage. In this case, writing can be performed by the ion implantation method described above in the y' final step of the semiconductor integrated circuit.

This makes it possible to standardize the manufacturing process for semiconductor integrated circuits, thereby improving manufacturing efficiency.

This kind of mask type ROM has a large storage capacity,
A large number of memory elements are arranged in a matrix.

Therefore, one data line has a large parasitic capacitance by being coupled to a large number of storage elements.

Furthermore, since a large number of data lines are selectively connected to a common data line via column switch circuits, it has a relatively large parasitic capacitance. Therefore, in the read operation of the storage element, the charge amplifier or discharge operation of the large parasitic capacitance is involved.
The rate of change of the read signal is slowed down. For this reason, even if a highly sensitive sense amplifier is used, the level change speed of its output signal is slow (this causes a slow reading speed).

An object of the present invention is to provide a semiconductor memory device that achieves high-speed read operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a pair of MOs of the first conductivity type receive complementary input signals and have a relatively large conductance.
The readout is performed by an amplifier circuit consisting of an SFET and a pair of MOSFETs of the second conductivity type, which are respectively provided at the drains of the pair of MOSFETs and whose gates and drains are cross-connected and have a relatively small conductance. It performs signal amplification operation.

[For production]

According to the above means, the positive feedback loop in the amplifier circuit allows the input signal to have a gradual signal change.
It is possible to obtain an output signal that rises quickly.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a main part of a mask type ROM to which the present invention is applied. This example ROM
is formed on a single semiconductor substrate such as single-crystal silicon by a known CMOS circuit manufacturing technique, although not particularly limited thereto. Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. An N-channel MO3FET consists of a source region, a drain region formed on the surface of such a semiconductor substrate, and a polygon film formed on the surface of the semiconductor substrate (channel region) between the source region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode made of silicon. The P-channel MO3FET is formed in an N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MO3FETs formed thereon. The N-type well region is formed on the P-channel region S
Configures the substrate gate of the FET.

Memory array M-ARY includes a plurality of word lines WO to Wn arranged in the horizontal direction and a plurality of data lines (bit lines or deshift &
51) MO3FE for storage at the intersection with DOO=D01 etc.
'TQm is formed.

In this embodiment, although not particularly limited, in order to increase the density of storage elements and reduce power consumption during read operations, a common source is provided between and parallel to a pair of data lines DOO and DIO. A line cso is provided. The common source line csO is connected to the corresponding pair of data lines DOO.
, a memory MO3F whose drain is connected to DIO
The sources of ETQm are connected in common. Furthermore, the drains of the storage MO3FETs whose sources are coupled to the adjacent common source line C3I are commonly connected to the data line DIO. The drain of the other storage MOSFET corresponding to the common source line C81 is connected to the data 1DO.
Connected to 1. The drains of storage MO3FETs whose sources are coupled to a common source &IC32 provided adjacent to the data line DIO are commonly coupled to this data line DIO.

In this way, the data lines and the common source lines are alternately arranged and, except for the data line DOO at the end, are commonly connected to the drains of the storage MO3FETs assigned different Y addresses.

That is, the data line DOO is coupled to the common data line CDO via the MO3FET QI 1 forming a Y gate (column switch). The corresponding common source line C8O is coupled to the ground potential point of the circuit via the switch MO3FETQ12. In addition, the common source line C
Other data kiD10 corresponding to 8O is connected to the common data line CD via MO3FETQ13 that constitutes a Y gate.
is coupled to I. These switches MO3FETQ11
~The gate of Q12 is provided with a Y decoder circuit YDC, which will be described later.
A selection signal YO formed by R is commonly supplied.

The data line DIO is connected to MO3FETQI, which constitutes a Y gate to which another Y address (Y2) is assigned.
4 to the common data line CD 1 . Common source line C3 placed on the right side of the data line 010
I is coupled to the circuit's ground potential via switch MO3FET Q15. The data line Dot arranged on the right side of this common source line C3l is connected to the M
It is coupled to common data ficDO via O5FETQ16. The selection signal Y1 formed by the Y decoder circuit YDCR is supplied to the gates of these MO3FETs QI4 to Q16. Thereafter, data lines, common data lines, and switch MOSFETs are formed by repeating similar patterns.

The gates of the storage MOS FET arranged in the same row are connected to the corresponding word '+1A W O' W
n, respectively. The word line wO-W n is
A selection signal formed by an X decoder circuit XDCR, which will be described later, is supplied to each of them.

In this embodiment, depression type MO3FETCI to Q7 are provided between the data lines DOO to Dol and the common source lines C8O to C32, etc. and, although not particularly limited, to the power supply voltage VCC. The depletion type MO3FETs Q1, Q3, Q5, Q7, etc. corresponding to the data lines DOO to DOI supply a bias voltage and act as load means, and the depletion type MO3FETs Q2, Q4 corresponding to the common sources ucso to C32 supply a bias voltage and act as load means. , Q6, etc. are MOs that supply a bias voltage to set the common source line to a non-select level.
Acts as SFET.

For example, by the Y decoder circuit YDCR, the selection signal Y1
is formed, the switches MO3FETQ14 to Q16 are turned on, so that the data line DI
O, DOI and common source line C3I are selected. In this case, the data line D10. DO1 and common source line C
Only the storage MO3FETs each placed between the SI and the SI must be brought into a selected state. However, if the potentials of the common sources Hcso and C32 are set to a low level like the ground potential of the circuit, the data line D10 and the common source line CSO and the data line DOI and the common source line C3
The storage information of the storage MOS FET arranged between the data line D10 and DOI also appears on the data line D10 and DOI. Therefore, as mentioned above, the depression type MO3FETQ2. Q4. By providing Q6, etc., only the selected common source line C8O is given the circuit ground potential by the Sui-Nochi MO3FET QI5, and the potential of the unselected common source lines C8O and C32 is made equal to the bias potential of the data line. By letting
Data 1D10. Dot and common source lines C3O and C32
This is to turn off the storage MO3FET disposed between the OFF state and the OFF state regardless of the storage information of the storage MO3FET.

Addressing of the memory array M-ARY having the above configuration is performed by each of the following circuit blocks.

An X address signal AX consisting of multiple bits supplied from an external terminal is supplied to an X address buffer XADB,
A complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an internal address signal in opposite phase is formed.

These q complementary address signals are decoded by an X decoder XDCR, and a selection signal for one word line is formed by this X decoder XDCR. In this example, the above
The address buffer XADB and the X decoder XDCR are collectively expressed as χADH-DCR.

A Y address signal AY consisting of multiple bits supplied from an external terminal is supplied to a Y address buffer YADB,
A complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an internal address signal in opposite phase is formed.

These complementary address signals are decoded by a Y decoder YDCR, which forms selection signals for two data lines. In this example, the above Y
The address buffer YADB and Y decoder YDCR are collectively expressed as YADB-DCR.

In addition, in the read operation, since the output signals of the Y decoder YDCR of both common source lines arranged adjacent to the unselected data line are set to low level, each switch MOS FET is both turned off. be done. Therefore, a large number of storage MOS F E
Even though T is coupled, only the current flowing in accordance with the stored information flows only to the storage MOSFET selected by the data line, so that power consumption can be reduced.

In addition, storage MOSFETs whose data lines are assigned different Y addresses can be combined by a selection operation according to the Y address of the common source line.
SFETs can be arranged in high density.

The storage MO5FETQm has different threshold voltages according to storage information. Although not particularly limited, a storage MOSFE to which logic “1” is written
In T, impurities of the same conductivity type as the semi-plane substrate (for example, poron) are added to the semi-plane substrate (channel region) 4 under the gate electrode by a selective ion implantation technique using a suitable masking means. By introducing this, it is possible to have a relatively high threshold voltage. The writing process using such ion implantation technology is the final process of semiconductor integrated circuits formed on a semiconductor wafer, for example,
Data line or common source 1 made of aluminum layer
3 MOS F E which is a memory cell after CS formation
This is carried out by an ion implantation process at a high energy of about 150 KeV through a gate electrode of T Q m. Avoidance of contamination due to ion implantation, etc. or prevention of impurities
Because the iIA edge film remains for interpolation, etc., and the gate electrode has a thick polycide structure, it is considered to be high-energy ion implantation. Therefore, defects are likely to occur in the substrate, and since annealing can only be performed at low temperatures (approximately 450° C. or lower), defects caused by impurity activation and ion implantation cannot be sufficiently removed. Therefore, the leakage current in the memory cell increases and the breakdown voltage at the drain junction deteriorates. Furthermore, the amount of impurities reaching the channel region is small and unbalanced. In other words, the storage MOS F where the above writing was performed
The threshold voltage of E T Q m is relatively low, such as 2 to 3 cm, and has relatively large variations due to variations in the thickness of the gate electrode and the remaining interlayer insulating film formed on its surface. be done. On the other hand, the threshold voltage of the storage MOS FET to which no writing is performed is set to a relatively low voltage of, for example, about 0.5 to 1.

In this embodiment, the following dummy cells are provided in order to accurately identify read signals from the storage MOSFETs having only the small difference in threshold voltage.

Although not particularly limited, for example, two dummy MO3Fs whose gates are coupled to each word vAWO to Wn, respectively.
ETQd, Qd' are provided in parallel type a. These M
The OS FET Q d and Q d ' are placed in parallel by being respectively placed between a pair of common source lines C3 placed on both sides of the dummy data line DD. One of the above dummy MO3FETQd is the memory MOS FET having a relatively low threshold voltage.
Formed in the same way as ET.

The other dummy MO3FET Qd' is formed in the same manner as the storage MO3FET having a relatively high threshold voltage. The dummy MO3FETQd”, which has this high threshold voltage, is connected to the word line selection level (approximately 2v
storage MOS F to be turned off for
It is provided to compensate for a drop in high level due to leakage current occurring in ET.

The dummy data line DD, on which the dummy MO3FETs Qd and Qd' are provided, is connected to the sense amplifier SA, which will be described later, as a reference voltage Vref via a switch MO3FETQ20.
O, supplied to SAI. The common source line CS is coupled to the ground potential point of the circuit via the switch MO3FET QI9°Q21.

Although not particularly limited, a selection signal YD for the dummy MOS FET formed by the Y decoder circuit YDCR is supplied to the gates of the switches MO3FETQI9 to Q21.

A common common data line CDO to which data lines to be selected are commonly connected via a column switch circuit is connected to a non-inverting input terminal (+) of a sense amplifier SAO consisting of a differential amplifier circuit.
supplied to Inverting input terminal of sense amplifier SAO (-
) is a reference signal Vr obtained from the dummy data line DD.
ef is supplied. A sense amplifier SAI similar to the above is also provided for the other common data line CDI.

Since the data line and the common data line have a large parasitic capacitance, the stored information of the storage element read to the common data line has a gradual change in signal. In this embodiment, in order to speed up the read operation, the following output amplifier circuits OAO and OAI are provided on the output sides of the sense amplifiers SAO and SA1, respectively.

The output amplifier circuit OAO is composed of the following circuit elements. The output signal of the sense amplifier SAO is an N-channel MO3FE whose source is coupled to the ground potential of the circuit.
Supplied to the gate of TQ24. Further, the output signal of the sense amplifier SAO is inverted by an inverter circuit N1 and supplied to the gate of an N-channel MO3FET Q25 whose source is coupled to the ground potential of the circuit. The drains of these MO3FETs Q24 and Q25 and 77a
A P-channel MOSFET Q 22 whose gate and drain are cross-connected to the voltage VCC is connected to the voltage VCC.
and Q23 are provided. Above P channel MO3FET
Q22 and Q23 are the above N-channel MO3FETQ2
In order to operate it as a load for MOSFETs Q24 and Q25, its conductance is set to be smaller than that of MOSFETs Q24 and Q25. The P-channel MOS FETs Q22 and Q23 serving as the loads have their gates and drains cross-connected to form a positive feedback loop and operate as variable resistance elements.

The output side Do of the output amplification circuit OAO is obtained from the drain side of MOSFETQ25, although it is not particularly limited.
The signal is transmitted to a data output circuit DOB (not shown). In addition,
The output amplification circuit OAI provided on the output side of the sense amplifier SAI is also constituted by a circuit similar to the output amplification circuit OAO.

The read operation of this embodiment circuit will now be described with reference to the operational waveform diagram shown in FIG.

The signal read to the common data line CDO changes extremely slowly because the common data line CDO and the selected data line have a relatively large parasitic capacitance. The sense amplifier SAO changes its output signal from a low level to a high level when the potential of the common data line CDO becomes high, for example, with respect to the reference voltage V ref.At this time,
Since the change in the input signal is gradual, the change in the output signal of the sense amplifier SA0 is also relatively slow. Such an amplified output signal increases the threshold voltage of MOSFETQ24 (
When the logic threshold (VL) is reached, the MO3FE
TQ24 starts conducting. In addition, inverter circuit N1
When the inverted signal of MOSFETQ25 changes from high level to low level, the conductance of MOSFETQ25 is reduced accordingly. Then, after the two signals SAO and N1 intersect, the conductance of MO3FETQ24 is reversed to become larger than the conductance of MO3FETQ25, so the drain voltage is also reversed and the difference becomes large. In response to this, P channel MO3FET
Since the conductance of Q22 is small and positive feedback is applied to increase the conductance of Q23, the drain voltage difference between the MO3FETs Q24 and Q25 increases rapidly, and the output signal DO quickly changes from low level to high level. Become something. This makes it possible to obtain an output signal that changes rapidly in response to an input signal that changes relatively slowly.

In addition, MOSFETQ22 and Q24 and Q23 and Q25
The logic threshold voltage VT of the amplifier circuit consisting of MOSFET Q24 and Q25 is
Since the conductance of Q22 and Q23 is set small, %'M03FETQ24. This is equal to the threshold voltage of Q25.

Furthermore, in the above embodiment circuit, double-ended differential amplifier circuits that form complementary output signals are used as the sense amplifiers SAO and SAI instead of the single-ended differential amplifier circuits as described above. In this case, the inverter circuit N1 is omitted and its complementary output signal is directly transmitted to the pair of MOSFETs Q24. It is sufficient to supply it to the gate of Q25.

The effects obtained from the above examples are as follows. That is, (1) A load MOSFET that receives a complementary input signal is connected to the output side of a sense amplifier that receives signals read out through a common data line and a data line that have a relatively large parasitic capacitance.
By providing an amplifier circuit having a positive feedback loop using T, the signal level necessary for its output operation can be formed at high speed, so that the effect of realizing high-speed operation can be obtained.

(2) According to (1) above, high-speed reading is possible even if the parasitic capacitance of the common data line is increased, so more data lines can be connected. by this,
This has the effect of realizing a large storage capacity.

(3) Memory M○ configured to run parallel to the data line
By selectively grounding the common source line of the 5FETs by the Y (column) selection signal, the unselected storage MO
Since it is possible to prevent current from flowing through S FET, it is possible to achieve the effect that power consumption during a read operation can be reduced.

(4) According to (3) above, since the common source line can have a selection function, storage MOS FETs whose data lines are assigned different Y addresses can be commonly connected. As a result, the number of data lines can be reduced, so that MO3FETs for storage can be formed with high density, and in combination with the above (2), it is possible to achieve the effect of realizing a large storage capacity.

Although the present invention has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist of the invention9. In order to reduce the current consumption in the output amplifier circuit, the MO3FETQ24. Q25 or M O
The sources of S F E T Q 22 and Q23 may be made common, and the ground potential or power supply voltage cc of the circuit may be supplied through a power switch MO3FET that is turned on only during memory access. In addition, when reading in units of 1 bit, the sense amplifier SA
O or SAI may be selectively operated according to the Y address signal and output from a common data output sofa. Furthermore, when reading in units of 2'' bits such as 4 bits to 8 bits, n/2 sets of the memory array M-ARY, sense amplifier, and data output cover sofa shown in FIG. 1 are provided. Just do something.

Further, in the configuration of the memory array (memory block), the sources of the storage MO3FETs may be directly connected to the ground potential of the circuit.

In this case, the drains of the storage MOS FETs are each coupled to one independent data line.

Furthermore, any method of writing to the storage MOS FET may be used. For example, MO3FET for memory
The writing may be performed electrically using a FAMO3 (floating gate avalanche injection MO3FET) or the like.

The present invention is applicable to semiconductor memory devices such as mask-type ROMs and EPROMs (erasable programmable read-only memories), which are composed of memory elements that have two different threshold voltages according to stored information. It can be widely used in various semiconductor memory devices in which a large parasitic capacitance is added to a common data line or a data line.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the output side of the sense amplifier, which receives signals read out through the common data line and the data line, which have relatively large parasitic capacitance, receives a complementary input signal and connects the load MO.
By providing an amplifier circuit having a positive feedback loop using SFET, the signal level necessary for its output operation can be formed at high speed, so that high-speed operation can be realized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a main part of a mask type ROM to which the present invention is applied, and FIG. 2 is a waveform diagram for explaining the read operation thereof. M-ARY...Memory array, XADB-DCR
・・X address buffer/decoder, YADB/DC
R...Y address buffer decoder, SAO, SAI
・・Sense amplifier, OAO, OAI・・Output amplification circuit

Claims (1)

[Claims] 1. A pair of MOSFEs of a first conductivity type that receive complementary input signals and have a relatively large conductance.
an amplifier circuit consisting of a pair of second conductivity type MOSFETs each provided at the drains of the pair of MOSFETs and whose gates and drains are cross-connected to have a relatively small conductance; and this amplifier circuit. and an output circuit that receives an output signal. 2. The complementary input signals are arranged in a matrix at the intersections of data lines and word lines, with memory elements having relatively high threshold voltages or relatively low threshold voltages according to stored information. 2. The semiconductor memory device according to claim 1, wherein the output signal is an output signal of a sense amplifier that receives a read signal from a memory array formed by a memory array, and an output signal of an inverting amplifier circuit that forms an inverted signal of the sense amplifier. 3. The above memory element is made to have a relatively high threshold voltage by selectively introducing impurities of the same conductivity type as the substrate gate into its channel region by ion implantation. A semiconductor memory device according to claim 2, characterized in that: