JPS63293843A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPS63293843A JPS63293843A JP13010787A JP13010787A JPS63293843A JP S63293843 A JPS63293843 A JP S63293843A JP 13010787 A JP13010787 A JP 13010787A JP 13010787 A JP13010787 A JP 13010787A JP S63293843 A JPS63293843 A JP S63293843A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- base
- emitter
- layer
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 230000001681 protective effect Effects 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 abstract 3
- 238000010168 coupling process Methods 0.000 abstract 3
- 238000005859 coupling reaction Methods 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 2
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 241000270708 Testudinidae Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は１ンビ一ダンス変換用回路をもつトランジスタ
チップからなる半導体素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device consisting of a transistor chip having a circuit for 1-in-1 dance conversion.
第３図は従来の高周波トランジスタの一例の平面図であ
る。図において、７，８はベースおよびエミッタ′電極
露出部、１９．１０はベースおよび工ずツタ連結電極、
１１．１２はベースおよび工ぐツタのボンディングバプ
ド％ １３ｒｉ動作ｊｔ極領域を示している。FIG. 3 is a plan view of an example of a conventional high frequency transistor. In the figure, 7 and 8 are exposed parts of base and emitter' electrodes, 19.10 are base and vine connection electrodes,
11.12 shows the bonding bapt% 13ri operation jt polar region of the base and the vine.
従来の高周波トランジスタｒｊ、高周波特性の低下をき
たす対出力端子容量を低減するために、外部接続用電極
（以下ポンディングパッド又はパッドと略称する）１１
．１２の下に厚い絶縁膜（６）を形成しである場合が多
く、さらにこの効果を上げるために寄生容量を低減した
い側のボンティングパッドを動作電極（４，５）の上に
、絶縁保護膜（６）を介して形成するというようなこと
が行われている。In the conventional high-frequency transistor rj, in order to reduce the capacitance to the output terminal that causes deterioration of the high-frequency characteristics, an external connection electrode (hereinafter referred to as a bonding pad or pad) 11 is used.
．． In many cases, a thick insulating film (6) is formed under the active electrodes (4, 5), and in order to further increase this effect, the bonding pad on the side where the parasitic capacitance is desired to be reduced is placed over the active electrodes (4, 5) for insulation protection. Formation via a film (6) has been carried out.
上述した従来の構造は、前者の場合対出力寄生容量は皆
無にすることはできず、また後者のような場合は対出力
端子との容量は皆無にすることができるが、人力と接地
の端子間の寄生容量を増加させるような結果となってい
る。この入力と接地の端子間の静電容量の増加は１人力
インピータンスの低下を招き、パワートランジスタのよ
うに入力インピーダンスの低いものはさらに人力インピ
ーダンスが低くなる結果となり、外部回路のインピーダ
ンスとの整合がとりにくくなり利得の低下や帯域の狭少
化を招いていた。In the conventional structure described above, in the former case, the parasitic capacitance to the output cannot be completely eliminated, and in the latter case, the capacitance to the output terminal can be completely eliminated; This results in an increase in the parasitic capacitance between the two. This increase in capacitance between the input and ground terminals leads to a decrease in the input impedance, and for devices with low input impedance such as power transistors, the input impedance becomes even lower, making it difficult to match the impedance of the external circuit. This made it difficult to obtain a high gain, resulting in a decrease in gain and a narrowing of the band.
本発明の１的は、このような問題を解決し、外部回路と
のインピーダンス整合をとりやすくして利得特性、帯域
特性を向上させた半導体素子を提供することにある。One object of the present invention is to provide a semiconductor element that solves these problems, facilitates impedance matching with an external circuit, and improves gain characteristics and band characteristics.
本発明の構成は、第１の層に設けられた電極群上にその
領域を覆う絶縁保護膜を有し、この保誇膜上に設けられ
た前記第１ｏ層の電極群の露出部を通してボンディング
用電極群が接続され、これら電極群のうち入力用のボン
ディング用電極部の少くとも一部が前記第１の層の電極
群領域の直上の保護膜表面にある第２の層に形成されて
いる半導体素子において、前記第１の層の入力電極から
前記第２の層の入力用ボンディング用電極部までの連結
用電極部の一部が、前記第１の層の電極群領域の直上か
ら外れて所定の長さあるいｒｉ面積をもって形成されて
いることを特徴とする。The structure of the present invention has an insulating protective film covering the area on the electrode group provided in the first layer, and bonding is performed through the exposed portion of the electrode group of the first o layer provided on the protection film. and at least a part of the input bonding electrode part of these electrode groups is formed on the second layer on the surface of the protective film directly above the electrode group area of the first layer. In the semiconductor device, a part of the connecting electrode part from the input electrode of the first layer to the input bonding electrode part of the second layer is removed from directly above the electrode group area of the first layer. It is characterized in that it is formed with a predetermined length or area.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図ｆａｔ 、 （ｂ） 、 Ｉｃｌｒｉ本発明の第
１の実計１例の断面図、その模式的平面図およびその等
価回路図である０本実施例は、半導体基板１にペース領
域２とエミヴタ領域３を形成し、スパッタ法などにより
各動作電極４．５を形成する。次に、動作電極４．５を
覆うように厚さ０．１μｍＯ酸化膜６をＣＶＤ法で被着
し、フォトエヅチングを用いて動作電極露出部７，８を
形成する。続いて、動作領外に厚い酸化膜層を形成し、
つづいて再びスパッタ法などを用いて連結用電極９，１
０とポンディングパッド１１．１２とを酸化膜６の表面
に形成する。このとき連結用゛電極９は、必賛なインダ
クタンスをもつように動作電極領域１３よリ一部が外れ
て、幅１０μｍ、長さ６５μｍのライン状に形成されて
おり１入力用ボンディングパヅドは。FIG. 1 is a sectional view, a schematic plan view, and an equivalent circuit diagram of the first actual example of the present invention. In this embodiment, a semiconductor substrate 1 is provided with a space region 2 and An emitter region 3 is formed, and each working electrode 4.5 is formed by sputtering or the like. Next, a 0.1 μm thick O oxide film 6 is deposited by CVD so as to cover the working electrode 4.5, and working electrode exposed portions 7 and 8 are formed using photoetching. Next, a thick oxide layer is formed outside the operating area,
Subsequently, the connecting electrodes 9 and 1 are formed again using sputtering or the like.
0 and bonding pads 11 and 12 are formed on the surface of the oxide film 6. At this time, the connecting electrode 9 is formed in a line shape with a width of 10 μm and a length of 65 μm, with a part separated from the working electrode area 13 so as to have a required inductance. teeth.
４００Ｘ１００μ第２の大きさで、全部が動作電極領域
の上に形成されている。第１図（ａ）ｒｉ第１図（ｂ）
のｘ−ｘ’断面図であるため、連結用′亀＆９とバッド
１１とが接続されていないように描かれているが、実際
には接続きれている。A second size of 400×100μ is formed entirely over the working electrode area. Figure 1 (a)ri Figure 1 (b)
Since this is a sectional view taken along the line xx', the connecting tortoise &9 and the pad 11 are depicted as not being connected, but in reality they are completely connected.
第２図（ａ） 、 ｆｂｌに本発明の第２の実施例の模
式的平面図およびその等価回路図である。この実施例の
場合、大略の構成ｒｉ、第１の実施例と岡じであるが％
接地用電極５がベース領域２より広く形成されており、
連結用電＄ｉ９が、幅１０μｍ、長さ６５μｍの形状を
もつ第１の連結ｓ９ａと、幅１０μｍ、長さ２５０μｍ
の形状をもつ第２の連結部９Ｃと、接地用電極５の上に
形成された２４０μｍ×１００μｍの形状をもつ平面部
９ｂとから構成されており、第１の連結部９ａのインダ
クタンス公約０．４ ｎ Ｈ、第２の連結部９Ｃのイン
ダクタンス公約１，７ｎＨ平面部、９ｂの静電容量的８
．９ｐＦ及びポンディングパッド１１の静電容量的５．
４ｐＦとによって、２段のインピーダンス変換回路を構
成している。そのため第１の実施例よりさらに外部回路
とのインピーダンスの整合がとりやすくなっている。FIG. 2(a) and fbl are a schematic plan view and an equivalent circuit diagram of a second embodiment of the present invention. In the case of this embodiment, the approximate configuration ri is the same as that of the first embodiment, but %
The grounding electrode 5 is formed wider than the base region 2,
The connection electric wire $i9 connects the first connection s9a with a width of 10 μm and a length of 65 μm and a width of 10 μm and a length of 250 μm.
It is composed of a second connecting portion 9C having a shape of 4 n H, the inductance of the second connection part 9C is approximately 1.7 nH plane part, and the capacitance of 9b is 8
．． 9pF and the capacitance of the bonding pad 115.
4pF constitutes a two-stage impedance conversion circuit. Therefore, it is easier to match the impedance with the external circuit than in the first embodiment.
以上説明したように本発明ｒｉ、出力端子との寄生容量
を無くすために動作電極上に絶縁保護膜を介して形成さ
れたポンディングパッドと動作４極の間の連結用電極が
、所望のインダクタンスを持つように動作領域の上から
はすれて形成されておシ１人力ボンディングバッドを動
作１！極の上に形成することによって生ずる。入力−接
地間の静電容量とともに適轟なインピーダンス変換回路
を形成することが出来、単に動作電極とポンディングパ
ッドを接続する場合に比べて外部回路のづンビーダンス
との整合が格段にとりやすくなった。As explained above, in the present invention, the connecting electrode between the bonding pad, which is formed on the working electrode via an insulating protective film in order to eliminate parasitic capacitance with the output terminal, and the working 4 poles has a desired inductance. The bonding pad is formed by peeling off from the top of the operating area so that it can be operated manually! Caused by formation on top of poles. It is possible to form a suitable impedance conversion circuit with the capacitance between input and ground, and it is much easier to match the external circuit's Zambia dance compared to simply connecting the working electrode and the bonding pad. .
例えば、第１の実施例の場合、連結用電極のインダクタ
ンスと入力ボンディングバッドの静電容量を含まないイ
ンダクタンスは周波数ＩＧＨｚで５＋ｊ５Ωであるのに
対し、両者を含む場合は１６、ｓ＋ｊｏΩとなり、通常
の高周波回路の特性インピーダンスである５０Ωに対し
て格段に整合がとりやすくなっている。For example, in the case of the first embodiment, the inductance excluding the inductance of the connecting electrode and the capacitance of the input bonding pad is 5+j5Ω at the frequency IGHz, whereas when both are included, it is 16,s+joΩ, which is different from the normal It is much easier to match the characteristic impedance of the high frequency circuit, which is 50Ω.
第１図ｔａｌ 、 ｌｂｌ 、 １ｃｌｒｉ本発明の第
１の実施例の断面図、その平面図およびその等価回路図
、第２図（ａ） 、 （ｂｌｒｔ本発明の第２の実施例
の平面図およびその等価回路図、第３図ｒｉ従来のトラ
ンジスタの一例の配置を示す平面図である。
１・・・・・・半導体基板、２・・・・・・ベース領域
、３・・・・・・エミ、り領域、４・・・・・・ベース
動作電極、５・・・・・・エミヴタ動作篭極、６・・・
・・・酸化膜、７・・・・・・ベース動作電極領域部、
８・・・・・・エミッタ動作電極領域部、９・・・・・
・ベース連結用電極、１０・・・・・・エミッタ連結用
電極、１１・・・・・・ベースボンデインクパッド、１
２・・・・・・エミッタボンディングバッド、１３・・
・・・・動作電極領域、Ｚｏ・・・・・・人力インピー
ダンスｓ Ｌｌ・・・・・・連結電極９によるインダク
タンス、ＣＩ・・・・・・ベースボンデインクパッドに
よる静電容ｆｆｉ、Ｌ鵞・・・・・・連結電極９ａによ
るインダクタンス、Ｃ雪・・・・・・連結電極９ｂによ
る静電容量％ Ｌｌ・・・・・・連結電極９Ｃによる
インダクタンス。
代理人 弁理士 内 原 晋１
７ べ冠く１才ΦＡ出部
刀１図Fig. 1 tal, lbl, 1clri A sectional view, a plan view thereof, and an equivalent circuit diagram of the first embodiment of the present invention, Fig. 2(a), (blrt a plan view and a plan view of the second embodiment of the present invention, and FIG. 3 is a plan view showing the arrangement of an example of a conventional transistor. 1... Semiconductor substrate, 2... Base region, 3... Emitter region, 4...Base operating electrode, 5...Emitter operating cage electrode, 6...
...Oxide film, 7...Base operating electrode region,
8...Emitter operating electrode area, 9...
・Base connection electrode, 10...Emitter connection electrode, 11...Base bond ink pad, 1
2...Emitter bonding pad, 13...
... Working electrode area, Zo... Human power impedance s Ll... Inductance due to connection electrode 9, CI... Capacitance ffi due to base bond ink pad, L ...Inductance due to the connection electrode 9a, C snow...Capacitance % due to the connection electrode 9b Ll...Inductance due to the connection electrode 9C. Agent Patent Attorney Susumu Uchihara 1 7 Bekanku 1 year old ΦA Debe sword 1 illustration
Claims (1)
護膜を有し、この保護膜上に設けられた前記第１の層の
電極群の露出部を通してボンディング用電極群が接続さ
れ、これら電極群のうち入力用のボンディング用電極部
の少くとも一部が前記第１の層の電極群領域の直上の保
護膜表面にある第２の層に形成されている半導体素子に
おいて、前記第１の層の入力電極から前記第２の層の入
力用ボンディング用電極部までの連結用電極部の一部が
、前記第１の層の電極群領域の直上から外れて所定の長
さあるいは面積をもって形成されていることを特徴とす
る半導体素子。An insulating protective film is provided on the electrode group provided on the first layer to cover the area, and the bonding electrode group is connected through the exposed portion of the electrode group of the first layer provided on the protective film. , in the semiconductor element in which at least a part of the input bonding electrode portion of these electrode groups is formed in the second layer on the surface of the protective film directly above the electrode group region of the first layer; A part of the connecting electrode part from the input electrode of the first layer to the input bonding electrode part of the second layer is removed from directly above the electrode group area of the first layer by a predetermined length or A semiconductor element characterized in that it is formed with an area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13010787A JPS63293843A (en) | 1987-05-26 | 1987-05-26 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13010787A JPS63293843A (en) | 1987-05-26 | 1987-05-26 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63293843A true JPS63293843A (en) | 1988-11-30 |
Family
ID=15026119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13010787A Pending JPS63293843A (en) | 1987-05-26 | 1987-05-26 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63293843A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006013346A (en) * | 2004-06-29 | 2006-01-12 | Matsushita Electric Ind Co Ltd | Bipolar transistor |
-
1987
- 1987-05-26 JP JP13010787A patent/JPS63293843A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006013346A (en) * | 2004-06-29 | 2006-01-12 | Matsushita Electric Ind Co Ltd | Bipolar transistor |
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