JPS6329366A - Magnetic tape recording and reproducing device - Google Patents

Abstract

PURPOSE:To decode accurately a sampling signal by supervising the increase/ decrease of the number of data stored in an output buffer memory for a digital audio signal and controlling the frequency of the sampling signal. CONSTITUTION:A control circuit 53 transfers a data in an output buffer memory 57 while supervising the state of rearrangement of a data, outputs a pulse RP synchronously with FS or FS itself and transfers a data from a memory to a data output latch 58 at a prescribed sampling period. The memory is controlled by an output of a selector 56 selecting one of outputs WA, RA of a write address memory 54 and a read address memory 55 controlled by a control circuit 53, a write/read control signal W/R outputted from the control circuit 53 and a write pulse WP and the control circuit in the timing minimizing the number of data in the memory 57 sends a field head signal FH to an FSH/L deciding circuit 59 deciding whether or not the sampling frequency is high or low to the memory. Thus, the sampling frequency is optimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video and digital audio recording and reproducing apparatus, and particularly to a system for generating an audio sampling signal during reproduction.

[Conventional technology]

Figure 10 shows, for example, the 1986 ICASSP Proceedings'A
5TUDY 0NTHE DIGITIZATION
OF AUDIO5IGNALS FORVIDEOT
APE l? It is a block diagram showing the video and digital audio recording/playback 1aZ shown in "EcORDεP" (Hitachi), and in the figure, (1) is a video signal recording processing circuit, (2) is a video system recording amplifier, and (3) is a A rotating drum containing a video head and an audio head, (4) a magnetic tape, (5) a video head amplifier, (6) a video signal reproduction processing circuit, and (7) an analog-to-digital converter (hereinafter simply ADC). ), (81 is a digital signal recording processing circuit, (9) is a four-phase phase signal modulation circuit (hereinafter simply referred to as a four-phase phase modulation circuit), OI is an audio recording amplifier, 0υ is an audio head amplifier, is a four-phase phase modulation signal demodulation circuit (hereinafter simply referred to as a four-phase phase demodulation circuit), α1 is a digital signal reproduction processing circuit, and 0
0 is a digital-to-analog converter (hereinafter simply referred to as DAC).

Next, the operation will be explained. The input video signal is subjected to FM modulation of the luminance signal by the video signal recording processing circuit (1), and the color signal is frequency-modulated (modulated) to a low range. Video head (
(not shown) and recorded on the magnetic tape (4).

In addition, the A word reproduced by the video head is processed by the head F amplifier (5), and the operations above 9 which are restored to the video signal by the video signal reproduction processing circuit (6) are performed by VH3 system, B system, etc. The operation is similar to that of the Ie 5 Saki VTR.

On the other hand, the input audio signal is converted into a digital signal by the ADC (71), converted into a pulse code modulated PCM signal with an error correction code added by the digital signal recording processing circuit (8), and further , is converted into a four-phase phase modulation signal by the four-phase phase modulation circuit (9), and then sent to the recording amplifier α value and sent to the magnetic tape (via the audio head (not shown) built in the rotating drum (3)
4) is recorded. Note that the audio signal is recorded below the video signal (so-called deep layer) similarly to the Hi-Fi audio signal of the VH3 system. In addition, the signal reproduced by the audio head is amplified by the Henodo amplifier αυ, the PCM signal is restored by the four-phase phase demodulation circuit, and further processing such as error correction is performed by the digital signal reproduction processing circuit αJ. It is restored to an audio signal by CQ41.

What is particularly important in the above-mentioned digital audio recording and reproducing apparatus using a rotating head is the sampling of the audio signal (restoration of No. 8). - Since the signal is lost, it is necessary to create a new one in some way during playback.When sampling and restoring an audio signal in one recording/playback device as shown in Fig. 10, one revolution of the rotary head or Half turn (1
Although it is possible to control the number of samples to be recorded for each field (field) to 6 to 11, it is possible to control the number of samples recorded for each field to a value of 6 to 11. For example, it is possible to control the number of samples recorded from a TV tuner for video signals, and for audio signals from a digital audio tape recorder (hereinafter simply referred to as DAT) in digital signal format. In such a case, the relationship between the video signal and the audio signal is not constant. Therefore, it becomes impossible to restore the sampling signal from the period or transmission rate of the reproduced digital signal, so some special means is required.

[Problem that the invention seeks to solve]

In systems that record and reproduce video signals and digital audio signals that are basically not synchronously related (hereinafter referred to as a video-audio asynchronous system), restoring the sampling signal is an important technical issue. If accurate restoration is not possible, problems such as discontinuity of the reproduced audio signal may occur.

The present invention was made in order to prevent the above-mentioned problems from occurring, and an object of the present invention is to provide a magnetic recording and reproducing device that can accurately restore a sampling signal of an audio signal even in a video-audio asynchronous system.

[Means for solving problems]

The magnetic recording/reproducing apparatus according to the present invention controls the frequency of the sampling signal by monitoring the increase/decrease in the number of data stored in the output banoffer memory of the digital audio signal.

[Effect]

The magnetic recording/reproducing apparatus according to the present invention outputs the final ratio of the digital audio signal at the point in time when the number of data in the cover sofa memory becomes the minimum, for example, at the point in time when the first piece of data recorded in the first field position is input. The number of data in the sofa memory is monitored, and if the number of data is larger than a predetermined number, the frequency of the sampling signal is increased, and conversely, if it is smaller, the frequency of the sampling signal is lowered to control the number of data in the sofa memory, so there is no possibility of data loss. Therefore, discontinuity in the reproduced signal does not occur. Furthermore, since the sampling frequency changes in accordance with the number of reproduced data, it is possible to follow uneven rotation of the rotating head, and it is also possible to reproduce tapes recorded with other magnetic tape recording and reproducing apparatuses.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a digital signal reproduction processing circuit and a sampling frequency generation circuit according to an embodiment of the present invention, FIG. 2 shows a configuration diagram of a video-audio asynchronous recording system, and FIG. 6 shows a DA
FIG. 8 shows a configuration diagram of an asynchronous playback system according to an embodiment of the present invention. In the figure, +11 is a video signal recording processing circuit, (2) is a recording amplifier, ( 3) is a rotating drum, (4) is a magnetic tape, (5) is a head amplifier, (6) is a video signal reproduction processing circuit, (7) is an ADCl, (8) is a digital signal recording processing circuit, and (9) is a 4 Phase phase modulation circuit, α0 is recording amplifier, Gυ is head amplifier, Foundation is 4-phase phase demodulation circuit, α1 is digital signal reproduction processing circuit, α ship is D
AC, α9 is the drum motor, αQ is the drum servo circuit,
α7) is a luminance signal color signal separation circuit, Om is a luminance signal recording processing circuit, α Yu is a color signal recording processing circuit, (2@ is a mixing circuit, (21) is a DA vane face circuit, (22) is a clock signal generation circuit circuits, (23) is a carrier signal generation circuit, (24) is a luminance signal/chrominance signal separation circuit, (25) is a luminance signal reproduction processing circuit, (26) is a chrominance signal reproduction processing circuit, (
27) is a mixing circuit, (28) is a frequency dividing circuit, (3o) is a synchronous detection circuit, (31) is a carrier regeneration circuit, (32) is a Cronk regeneration circuit, (33) is a data regeneration circuit, (34)
) is the FS generation circuit, (35) is the DA ink face, (
38) is a decoder, (39) is an FS regeneration circuit, (40) is a phase comparator, (41) is a voltage controlled oscillator, (42) is a frequency divider circuit, (43) is a memory, and (44) is a control circuit. ,(
45) is a selector, (46) is a memory, (47) is a memory, (48) is a PCM data generation circuit, (50) is a memory, (51) is a C, C, decoder, (52) is a memory, (53) is a control circuit, (54) is a write address memory, (55) is a read address memory,
(56) is selector, (57) is memory, (58) is lunch, (59) is F S H/L judgment circuit, (60)
is an integrating circuit, (61) is a voltage controlled oscillator, and (62) is a frequency dividing circuit.

Next, the operation will be explained. In FIG. 2, the video signal V-5IG is input to the luminance signal/chrominance signal separation circuit αη of the video signal recording processing circuit il+, and the luminance signal Y-310
and color signal C-3IG. Each signal is input to the luminance signal recording processing circuit 0 and the chrominance signal recording processing circuit α, and after being subjected to FM modulation and low frequency conversion, it is sent to the mixing circuit (to).
, a recording amplifier (2), and a magnetic tape (4
) is recorded. On the other hand, the rotating drum (3) is driven by the drum motor α image, which is created by the vertical synchronization signal V-3YNC separated from Y-310 by the tumor signal recording processing circuit α and the color signal recording processing circuit Q9). Using the continuous wave so-called color signal subcarrier FSC synchronized with the Hurst signal and the rotational phase and rotational speed detector (not shown) outputs D-PC and D-FC of the rotating drum (3) using human power Since it is controlled by the drum servo circuit that controls the drum motor α9, the rotating drum (3) rotates in synchronization with the input video signal.

Now, when the audio signal is manually input as an analog signal, it is 16 bits by the ADC+71 using, for example, a 48 KHz sampling signal FS (not shown).

The data is converted into 2ch digital data and sent to the digital signal recording processing circuit (8). As long as this sampling signal is generated within the magnetic tape recording and reproducing apparatus, it can be synchronized with the vertical synchronization signal 48 of the video signal, so that the number of audio signal samples within one field can be kept at a constant value. In Figure 3, (
A) is the audio head switching signal A-H3W,
CB) is an audio signal sampled with a sampling signal synchronized with the above switching signal, and M
Suppose we have a sample. In (C), the signal -CB) is divided into fields and then compressed to prevent problems such as data loss at the audio head switching section.

On the other hand, when the audio signal is input as a digital signal in the digital audio interface format, the digital audio ink face circuit (hereinafter simply referred to as the DA ink face circuit) (21) converts the audio signal into a 16-bit signal with a sampling frequency of 48 KHz, for example.
4ch or 32KHz 12bit.

It is converted to 4ch digital data and sent to the digital signal recording processing circuit (81).When an audio signal is input as a digital signal, even if the sample frequency is the same, it is completely different because it was created with different equipment. In other words, even if you try to input a fixed number of samples for each field, there will always be an excess or deficiency in the number of samples.The 6-rotation drum (3) rotates in synchronization with the video signal, and This is a problem that inevitably occurs if a synchronization relationship is not established between the video signal and the audio signal.

Now, the rotating drum (3) must be synchronized with the video signal in order to record the video signal.

Therefore, the above-mentioned excess or deficiency of data must be dealt with on the audio signal side.

If the sampling frequency of the digital audio signal (hereinafter simply referred to as FS) and the field frequency of the video signal (hereinafter simply referred to as FV) are in a synchronous relationship, then F S =4.
8KHz, FV-59,94Hz (7)
A relationship has been established between them. Therefore, the number of samples per field is M. Since the number of DA multiplied signal samples recorded in the field should be an integer, consider providing fields with a large number of samples and fields with a small number of samples so that the overall number of samples is 800.8 per field. Here, two types of samples per field, 798 and 804, were prepared for the purpose of facilitating signal processing and lowering the recording density on the tape. In this way, as shown in FIG. 4, 798 samples become 8 fields and 804 samples become 7 fields every 15 fields.

Next, a case where the video signal and the DA double signal are asynchronous will be described. If the period of the video signal is longer than that of the DA multiplied signal, the number of DA multiplied signal samples entering one field increases. Therefore, the number of fields with 804 samples increases. Since the maximum number of samples in one field is 804, the deviation of the DA double signal video signal is at the upper limit compared to the time of synchronization. Similarly, the upper limit of the deviation is when the period of the video signal becomes short. In other words, if a field of type 2#4 consisting of 798 samples and 804 samples of the I field is provided for the 800.8 samples of the I field, the video signal (
! : Between D A signal (D (F4M force 0.3496%~
This means that it can handle up to 0.3996%. 1 in Figure 5
An example formant of a FieldA98/804 sample is shown.

In the figure, one field consists of 134 blocks of data, 4 blocks of preamble, and 3 blocks of postamble.
Each data block consists of 24 bytes of PCM data, 4 bytes of header, 4 bytes of C1 code, and 6 bytes of C2 code, for a total of 38 bytes. Note that one byte corresponds to six samples of a 16-bit 2-channel DA signal, so in a field of 798 samples, one block worth of dummy data is sufficient. This operation is explained in detail in Figures 6 and 7. do. In FIG. 6, the input DA-3IG is converted into a 16-bit 2hc signal with a sampling frequency (hereinafter simply referred to as FS) of 48KH2 by a decoder (30) inside the DA-IF.
is restored to a digital signal. In addition, the DA flaw signal transmission rate is 128FS, so compare the phases! S (40)
, a voltage controlled oscillator (41) and a frequency dividing circuit (42).
S is played. The audio signal restored by the DA interface circuit (21) is input to the digital signal recording processing circuit (8), and then sent to the input stage buffer memory (43).
The control circuit (44) determines whether the number of samples in one field should be 798 or 804 depending on the degree of the input DA flaw signal. An example of this sample number determination will be explained using FIG. 7. For the purpose of explanation, the addresses of the panzer memory are assumed to be 0 to 1023, and 4 bytes are assigned to each address. That is, one address corresponds to one sample. Furthermore, since the fields are switched by the A-HSW signal, it is assumed that the above judgment is made by the A-H3W signal. When the A-H8W signal changes, the memory address where the latest data is written is E, and the memory address last read in the previous field is F. The data that can be read is at address ( F+1
) to E data. Since the number of data is (E - F), the number of data to be read can be determined based on this value. In Figure 7 (A), E = 805°F - 1023 Also, since the memory address is only up to 1023, (E - F) = 80
It is 6. Therefore, 804 samples can be read. Same figure CB
) is the next field after (A), so 800.8 pieces of data will be newly written, but in this case, 800.8 pieces of data will be newly written.
Assume that 01 pieces of data have been written. Therefore, E −5
82, F-803, so it becomes (EF)-803, and a total of 798 data of numbers 804 to 1023 and numbers 0 to 577 can be read. If the number of samples in one field is 804, input stage buffer memory (43
) to the data selector (45
) to the output stage buffer memory (46). On the other hand, to set the number of samples in one field to 798, after transferring 798 samples of data from the input stage buffer memory (43) to the output stage buffer memory (46) via the selector (45), 6 samples of data are transferred. dummy data from the selector (45) from the dummy data memory (47).
) to the output stage panzer memory (46).

In this way, 804 samples of data will be input to the output stage buffer memory (46) for each field. The data stored in the output stage buffer memory (46) is subjected to processing such as addition of an error correction code and data arrangement in the PCM data generation circuit (48), and one field is 42,864 bits in the format shown in Fig. 5.
2,569.268.16 converted to serial data and output from the data transmission clock signal generation circuit (22)
Hz transmission lock (hereinafter simply referred to as clock signal)
It is sent out by the FCL, and is further transmitted by a four-phase phase modulation circuit (9
), a carrier signal FC of about 2 MHz sent out from a carrier signal generation circuit (23) is subjected to four-phase phase modulation. The four-phase phase modulated signal PSK is recorded on a magnetic tape (4) via an audio recording amplifier (alpha) and an audio head (not shown) built into a rotating drum (3).

Next, the playback operation will be described. In FIG. 8, the rotating drum (3) is a reference vertical synchronizer 13 created by dividing the color signal subcarrier FSC sent out by the color signal reproduction processing circuit (26) and the above FSC by a frequency divider (28). To the video head and audio built into the 0-rotation drum (3) whose rotation is controlled based on VIIfF.

The signals reproduced by a card (not shown) are sent to each.

The signal is amplified and reproduced by the door amplifier (5) and C0. In the video signal system, the output of the head amplifier (5) is separated into an FM modulated luminance signal Y-FM and a low frequency converted color signal by a luminance signal/color signal separation circuit (24), and a luminance signal reproduction processing circuit (25) and a low-frequency conversion color signal, respectively. A color signal reproduction processing circuit (26) performs reproduction processing, and a mixing circuit (27) outputs the signal as a video signal. On the other hand, in the audio signal system, the four-phase phase modulation signal amplified by the head amplifier αυ is composed of a synchronous detection circuit (30), a carrier regeneration circuit (31), a clock regeneration circuit (32), and a data regeneration circuit (33). It is demodulated as a PCM signal by a four-phase phase demodulation circuit (2). In the above four-phase phase demodulation circuit (2), for example, r
PCM audio demodulator J for direct satellite broadcasting (Nationa
l Technical Report Vol.

30 No. I Feb, 1984) PI3
Data detector using synchronous detection method and carrier signal regeneration using inverse modulation method shown in Fig. 5 and F1 of PI3
The digital phase comparison type clock signal regeneration shown in g15 is performed, and the PC
Restored to M signal.

The PCM signal restored in this way is restored to the original audio data in the digital signal reproduction processing circuit αJ, but the transmission rate of the PCM signal, that is, the clock signal, is directly different from the net number of audio data. Since there is no relationship, the sampling signal that determines the net audio data transmission rate cannot be directly restored from the reproduced signal like the above carrier signal or the above clock signal.If this sampling signal cannot be restored correctly, the DACQ
41 or the DA Zeinface circuit (35), this may not only cause discontinuity of the audio data, but also cause a malfunction in the operation of the digital signal reproduction processing circuit α.

Next, generation of a sampling signal according to the present invention ('TJ1.
The original) method will be described in detail. In FIG. 1, the reproduced PCM data and clock signal are input to the digital signal reproduction processing circuit αj, and the memory (50), C+, C
The signal decoded and error-corrected by the Z decoder (51) is input to a temporary memory (52) where the data is rearranged. The control circuit (53) transfers the data to the output sofa memory (57) while monitoring the rearrangement status of the data, and also transfers the data to the output sofa memory (57), and also outputs the FS or the pulse RP synchronized with the FS.
is output and data is transferred from the memory (57) to the data output lunch (58) at a constant sampling period. The memory (57) includes a write address memory (54) and a read address memory (54) controlled by a control circuit (53).
Selector (55) for selecting one of the outputs WA and RA of
6) and the write/read control signal W/R and write pulse WP output by the control circuit (53). The number of data in the memory (57) can basically be considered as the distance between the write address and the read address, so in each field, the data is stored first in the memory (52).
The control circuit (53) transmits the field head signal F at the timing immediately before the data is transferred from the memory (57) to the memory (57), that is, at the timing when the number of data in the memory (57) becomes the minimum.

H is sent to the F S H/L determination circuit (59) which determines whether the sampling frequency is high or low for the memory (57). Since the write address (WA) and read address (RA) are input to the FSH/L determination circuit (59), (WA-RA) is calculated.

In the memory (57), WA and RA have a positional relationship as shown in Figure 9, so (WA-RA) is the number of readable data (data margin) in the memory (57). It is assumed that the level of the sampling frequency is determined by comparing this value with a predetermined value. Now, if the number of samples recorded per field is constant, basically (WA-RA) should be constant,
If there is an increase or decrease, it is immediately clear that the sampling frequency is inappropriate. However, if the video signal and audio signal are asynchronous, the number of samples per field is no longer constant. Let L and S be the number of samples recorded in the l field, and assume that the following relationship holds true.

Now, if the field with the number of samples is (n l) fields and the field with the number of samples S is 1 field, then the distance between the write address and the read address after n fields <WA-RA) is when the initial value is Q. , if the sampling frequency is correct, the number of samples read out per field is (WA-RA)=Q+(n-1)L+5-nX, and (WA-RA)=Q is maintained. Since the number n is not known, it is not possible to compare units of n fields.Also, to compare each field, the number of input data is different, so it is not possible to simply compare (determine) the nth field. If the number of samples in the field is S, then in the (n - 1)th field, (WA - RA) = Q + (n - 1)L - (n -
1)...(3) holds true. Conversely, the field with L samples is 1,
Similarly, when the number of samples is S and the field is (n-1), (WA-RA)=Q--D>Q+D (4). In other words, if the sampling frequency is appropriate, Q-D<(WA-RA)<Q+D (5) in any field.
This means that a relationship has been established. Therefore, FSH/
For example, the L determination circuit (59) determines that (WA-RA)-≧-Q+
If 5■ is output when D, 0■ is output when (WA-RA) is Q-D, and 2.5■ is output when Q-D<(WA-RA)<Q+D, this voltage level signal H/ L is applied to the integrating circuit (60) of the FS generating circuit (34) and causes the voltage controlled oscillator (61) to operate. The sampling frequency obtained by dividing the output of the voltage controlled oscillator (61) by the 128 frequency divider (62) is sent to the control circuit (53), and the series of operations is repeated. It is related to the delay time of signal processing, and it is preferable that it be as small as possible as long as it does not cause any problems.
If you set it so that RA) = Q, from then on the car will have (5)
It is sufficient to monitor whether the formula is satisfied or not, and control the FS generation circuit (34) according to the output of the F S H/L determination circuit (59). According to the formant in Figure 5, L=8
04°S = 798. D=6. If it is around Q-10, it is considered that there is sufficient margin. In addition, in the above explanation, the upper and lower limits of the judgment level of the Teha and FSH/L judgment circuit (59) were explained as Q+ and Q-D, respectively, but the memory (57)
Since the fluctuation range of the number of data within is less than D, it only needs to be smaller than the upper limit.On the other hand, the upper limit may be larger than Q+D, and the lower limit may be smaller than Q-D, but the upper and lower limits If the width is too large, it will take time to make the determination, so it would be better to consider the upper limit as Q+2D and the lower limit as Q-2D.

In the above embodiment, the FSH/L determination circuit (59) has two
The explanation has been made assuming that there are two comparison values and the judgment result is sent as a three-value level signal, but there are two or more comparison values and three
A level signal higher than the above value may be sent, and the judgment result may be a 2-bit or 2-bit or more digital signal, or a pulse signal, and the same effect as in the above embodiment can be obtained. Motsu.

Furthermore, although the output of the F S H/L determination circuit (59) is fed to the integrating circuit (60) and used as the control voltage of the voltage controlled oscillator (61), it may also be used as a control voltage for the voltage controlled oscillator (61).

〔Effect of the invention〕

As described above, according to the present invention, two types of the number of samples that can be input into the field are prepared, so it is possible to support video/audio asynchronous systems. Monitors during writing and controls the sampling frequency so that the difference between the write and read addresses of the memory falls within a threshold that takes into account the difference between the two types of samples.
This makes it easy to optimize the sampling frequency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital signal reproduction processing circuit and sampling frequency generation circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a video-audio asynchronous recording system, and FIG. 3 is a block diagram showing a video-audio asynchronous recording system. FIG. 4 is a diagram for explaining synchronous data sampling, FIG. 4 is a diagram for explaining field allocation of sample data in a video-audio asynchronous system, and FIG. 5 is an example of a recording signal formant according to the present invention. 6 is a block diagram showing the DA Zeintaff 14 circuit and the digital signal recording processing circuit, FIG. 7 is a diagram for explaining the operation of the digital audio signal input stage memory, and FIG. 8 is an embodiment of the present invention. FIG. 9 is a diagram for explaining the operation of a digital audio signal output stage memory, and FIG. 10 is a configuration diagram of a conventional video signal and digital audio signal recording and reproducing apparatus. In the figure, (50) is a memory, (51) is a C, C3 decoder, (52) is a memory, (53) is a control circuit, and (54) is a C3 decoder.
) is the write address memory, (55) is the read address memory, (56) is the selector, (57) is the memory, (58) is the latch, (59) is the FS H/L judgment circuit, (60) is the integration circuit, (61) is a voltage controlled oscillator, and (62) is a frequency dividing circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Masu Oiwa Figure 7 (, 4) (8) Figure 9 procedural amendment (voluntary) 24 Title of invention Magnetic tape recording/reproducing device 3, relationship to the person making the amendment Case Patent applicant address Tokyo 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo (
Contact number 03 (213) 3421 1t'F section) 5. Detailed description of the invention and drawings according to claim 2 of the specification subject to amendment. 6. Contents of amendment (1) The scope of claims in the specification will be corrected as shown in the attached sheet. (2) The specification shall be amended as follows. (3) Figures 2 to 8 and 9 of the drawings are corrected as shown in the separate sheet. 7. List of attached tongues (1) One document stating the amended scope of claims: 2) One or more drawings (Figures 2, 8, and 9) Claims (1) A rotary head helical scan type magnetic tape recording and reproducing device that records video signals and digital audio signals. an input signal storage means for temporarily storing an audio signal; and a data distribution means for dividing the audio signal into two types of samples (M or N) for each field according to the number of samples of the audio signal stored in the input signal storage means. and a digital signal recording processing means that divides one or N pieces of data distributed by the data distribution means into one or more blocks and performs data arrangement, addition of an error correction code, etc., and the digital signal recording processing means. means for recording the output of the means on a magnetic tape at a constant transmission ratio; a means for reproducing the signal recorded on the magnetic tape by the recording means; and error correction and data rearrangement for the signal reproduced by the reproducing means. digital signal reproduction processing means for restoring the original digital signal by performing the above operations, and output signal storage means for temporarily storing the reproduced digital audio signal restored by the digital signal reproduction processing means and outputting it at a constant cycle;
means for controlling writing and reading of the reproduced digital audio signal into the output signal storage means, the first reproduced digital audio signal of each field from the digital signal reproduction processing means is written into the output signal storage means; means for detecting the time at which the output signal is read out and transmitting it to the control means; means for detecting the number of readable data in the output signal storage means based on the time signal; Sampling that determines whether it is high, appropriate, or low with respect to a predetermined threshold value and outputs a sampling frequency control signal consisting of a binary or more than two-value level signal or a digital signal of two or more bits, including some degree. 1. A magnetic tape recording and reproducing apparatus comprising: frequency monitoring means; and sampling frequency generating means for controlling the sampling frequency to an optimum value using the sampling frequency control signal.

Claims (1)

[Claims] A rotating head helical scan magnetic tape recording and reproducing device for recording and reproducing video signals and digital audio signals, in which the field frequency of the video signal and the sampling frequency of the digital audio signal are not synchronized. an input signal storage means for temporarily storing an input digital audio signal; a digital signal recording processing means for dividing the M or N data distributed by the data distributing means into one or more blocks and adding data arrangement and error correction codes; means for recording the output of the signal recording processing means on a magnetic tape at a constant transmission ratio; means for reproducing the signal recorded on the magnetic tape by the recording means; and error correction or correction for the signal reproduced by the reproducing means. A digital signal reproduction processing means for restoring the original digital signal by rearranging the data, and an output signal storage for temporarily storing the reproduced digital audio signal restored by the digital signal reproduction processing means and outputting it at a constant cycle. and means for controlling writing and reading of the reproduced digital audio signal to the output signal storage means, the first reproduced digital audio signal of each field from the digital signal reproduction processing means to the output signal storage means. means for detecting the writing time and sending it to the control means; means for detecting the number of readable data in the output signal storage means based on the time signal; Determine whether it is large, appropriate, or small with respect to a predetermined threshold value, and determine whether it is a binary value or a level value number of two or more values, including a certain degree.
A magnetic tape recording and reproducing device comprising: sampling frequency monitoring means for outputting a sampling frequency control signal consisting of a digital signal of bits or more; and sampling frequency generating means for controlling the sampling frequency to an optimum value using the sampling frequency control signal. Device.