JPS63292838A - Propagation delay adjusting system - Google Patents

Abstract

PURPOSE:To reduce the number of adjusting processes, and to shorten an adjusting time within a field because of automatic control by making adjustment within a bit unnecessary, by placing several bits of guard between time slots, and performing transmission so that the burst transmission timing of a subscriber can be adjusted in a unit of bit. CONSTITUTION:Both an up signal and a down signal are provided with 308 bits, and 256 bits in the center are allocated to a voice signal and data, and in the down signal, remaining 10, 1, 1, and 4 bits are allocated to a signal S for speech channel control, a don't-care DC, a parity P, and the don't-care DC, and in the up signal, they are allocated similarly to the S, the DC, the P, and a guard bit G. And the adjustment of the delivery timing of the up signal of a subscriber station is performed by inserting a delay circuit with several stages in a transmission data circuit and adjusting the number of stages of the said delay circuit by the number of bits representing a deviation quantity transmitted from a base station. For example, when one bit delay is instructed from the base station, a system is constituted so that transmission data is outputted after passing one stage of flip-flop additionally further.

Description

[Detailed description of the invention] [M Required] Adjustment of inter-station propagation delay is required in wireless TDM, but by providing guard bits in the burst transmission signal, intra-byte adjustment can be made unnecessary. In addition, dedicated time slots enable automatic adjustment during continuous operation.

[Industrial application field]

The present invention utilizes time division multiple access (TDMA) for wireless communications.
Tia+e Division Multipl
This invention relates to a method for adjusting the inter-station propagation delay time required in the e-Access method.

The wireless TDMA system is used for digital subscriber wireless, etc., and targets one base station and multiple subscribers #1 to #n, as shown in Figure 5, and each subscriber communicates with and through the base station. Communicate with other subscribers.

[Conventional technology]

As shown in FIG.
, a subscriber wireless line terminating device 12, and a subscriber wireless transmitting/receiving device 14, and the base station includes a base station wireless transmitting/receiving device 16, a base station wireless line terminating device 18, a supervisory control device 20, and a supervisory control device. It is equipped with a desk 22, and performs time division multiple access TDMA in, for example, the 26GH2 band between these transmitting and receiving devices 14 and 16. Since it is TDMA, each subscriber transmits and receives data using the time slot given to him/her.

The downlink signal from the base station to the subscriber station is a continuous signal in a frame synchronization format, and each subscriber extracts and processes data within a time slot addressed to the subscriber station after frame synchronization. The source of the downlink signal is one base station, but there are as many uplink signals from subscribers to the base station as the maximum number of subscribers, and each subscriber transmits at the same time (in each time slot). This is called a burst signal. Burst signals must arrive at the base station exactly in the time slots assigned to each base station, and if there is a delay or lead in the arrival time, the burst signal will overlap with the time slot of an adjacent subscriber (to prevent inter-burst interference). occur). Therefore, it is necessary to adjust the transmission timing of each subscriber, and the distance between each subscriber and the base station varies, and the characteristics of the equipment used by each subscriber are usually non-uniform. The above adjustment will be made for each subscriber.

[Problem that the invention seeks to solve]

Traditionally, delay adjustment was done manually using a measuring device during line setup (initial startup). This requires l bits (clock speed) in order to prevent transmission signals from multiple stations (buffed signals from each subscriber) from interfering on the time axis.
This is due to the fact that adjustment of the minute time within, for example, adjustment in units of 32 divisions of the clock speed is required, and human labor is required to judge the adjustment. Automatic adjustment is also possible, but this requires complex circuitry for delay time detection and control. In addition, this automatic adjustment is intended for adjustment during system on-site adjustment, and changes in inter-station propagation delay time due to temperature differences between summer and winter (this delay time is the sum of the spatial propagation time and the propagation delay time of parts used within the equipment). , the latter changes with temperature) cannot be followed.

The present invention achieves the above points by: (1) eliminating the need to slightly increase the propagation delay, (2) automatically adjusting the delay at the time of system startup, and (2) automatically detecting and correcting delay time fluctuations during operation. This is an attempt to improve.

[Means for solving problems]

In the present invention, multiple bits of guard are placed before and after the upstream signal. Figure 2 shows an example of the format of uplink and downlink signals (1
slots), but each has the same length and number of bits), and the downstream signal is a don't care (anything goes) signal D'C that continues for a while, followed by a PCM-converted audio signal or data ■S, and then Call channel control signal S
, Don't Care DC, Parity P1 and Don't Care DC follow (.

In addition, the uplink (burst) signal is subjected to multiple bits of guard G, followed by a preamble PRE and a synchronization pattern 5YNC for uplink burst signals, followed by a PCM-converted voice signal or data vs, and then a call. Channel control signal S, don't care DC, parity bit P, and finally multiple guard bits G (.

Further, in the present invention, the base station's upper reversal signal receiving circuit is configured as shown in FIG. In Fig. 1, 30 is a demodulator;
32 is a clock extraction circuit, 34 is a pattern matching detection circuit, and 36 is a FIFO (First In First 0
ut) register, 38 is an inhibit gate.

Furthermore, in the present invention, the base station detects the phase difference using the acquisition channel of the uplink signal, notifies the subscriber of this using the control channel of the downlink signal, and adjusts the delay.
FIG. 3 shows the radio frame format, and FIG. 4 shows the format of the acquisition channel ACQ of the uplink signal.

As shown in Figure 3, one frame consists of one TSO (
It consists of a time slot zero) and a plurality of VCHs (voice/data channels), the latter used for transmitting and receiving voice or data between the base station and subscriber stations, and the former used for control. TSO consists of the downlink frame synchronization pattern F1 control channel CNTL, don't care DC, and order wire (meeting line designation) OW in the downlink signal a, and the guard bit G, control channel CNTL, and
Acquisition channel ACQ and order wire O
Consists of W. In addition, as shown in FIG. 4, acquisition channel ACQ has a large number of guard bits G before and after, and these are used to control preamble PRE, synchronization pattern 5YNC for uplink burst signals, and acquisition pattern ACQ PTN. , station identification code 5T10
, put a don't care DC1 error detection code CRC.

[Effect]

As shown in Fig. 2, if several bits of guard G are placed between time slots and the uplink signal transmission period is only period Tb, even if the subscriber's uplink signal transmission timing moves back or forth by one bit, the adjacent channel (However, inter-burst interference also depends on other factors such as filter characteristics).

The transmitter is designed so that the subscriber's burst transmission timing can be adjusted in units of one bit.

Timing errors of 1 bit or less can be absorbed by the receiving circuit shown in FIG. That is, when a subscriber sends out a burst signal,
This is received by the receiving circuit shown in Fig. 1, demodulated by the demodulator 30, and the clock extraction circuit 32 which receives the demodulated output has a built-in PLL to extract the clock from the preamble PRE (Fig. 2). , whose output clock is synchronized to the preamble), and sends it to gate 38 and detection circuit 34. Similarly, the pattern matching detection circuit 34 which receives the demodulated output compares the synchronization pattern 5YNC (FIG. 2) with the built-in scheduled pattern and, if they match, generates a synchronization detection output and releases the inhibition of the gate 3B. As a result, the clock output from the clock extraction circuit 32 passes through the gate 38 and is written to the FIFO raster 36 as the write clock -CLK.
The audio signal VS portion of the demodulated output is input into the register 36 one after another. At the same time as this writing, the read clock RCLK enters the FIFO register, and the written audio signals are sequentially read out. Since the FIFO register functions as a buffer, the read clock RCLK does not need to be synchronized with the write clock WCLK.In this receiving circuit, the pattern match detection circuit detects synchronization pattern 5YNC by detecting a match with the scheduled pattern, and thereafter Since a method is adopted in which a predetermined number of bits of the audio signal VS are taken into the FIFO register 36 as the audio signal VS, a phase shift within one bit is absorbed and does not pose a problem.

By providing the guard bit G shown in Figures 1 and 2, extracting the clock from the received signal, detecting the synchronization pattern, and capturing subsequent data, fine adjustment of the propagation delay is no longer necessary. Become.

To acquire received data at a base station, a method is usually adopted in which the demodulated output is punched using a clock generated at the base station, but with this method, the phase of the demodulated output and the clock must match correctly (data (The clock needs to be punched through the center of the line), which requires slight adjustment of the subscriber transmission timing, but this is not necessary in the circuit shown in FIG.

Automatic delay adjustment uses ACQ for upstream signals and CNT for downstream signals.
This can be done using L. When starting up the system, the subscriber receives the upstream signal b in Figure 3 at an appropriate timing (however, since the downstream signal is being received, the subscriber enters the TSO).
(However, this only sends ACQ). The base station receives this and transmits 5YNC and ACQ P as shown by Δ in Figure 4.
Detect the boundary of the TN, calculate the deviation from the position (reference) of the boundary in the number of bits when the subscriber correctly transmits to its own slot, and calculate the deviation (number of bits) as the downlink signal in Figure 10. A notification is sent to the subscriber station using the control channel CNTL of a. In response to this, the subscriber station automatically adjusts the transmission timing of the uplink signal so that the specified deviation becomes O.

If this delay adjustment is performed periodically during operation, it is possible to prevent delays caused by changes over time.

The delay adjustment in this case can be performed by instructing the subscriber from the base station during operation using the control channel CNTL of the downlink signal, and having the subscriber send out <ACQ as described above.

When starting up the system, it is conceivable that multiple subscriber stations simultaneously send out acquisition (ACQ) patterns.

In this case, the base station will interfere with each other, and the base station will know this by checking the CRC and do nothing. Since the subscriber does not receive a response from the base station, the subscriber raises the ACQ again after a predetermined period of time, but it is possible to set this retry time to be different for each subscriber station so that simultaneous transmission will not occur this time. taken.

〔Example〕

To give a specific example, the upstream/downstream signals (meeting and call channels) in Figure 2 are both 308 bits (V in Figure 3).
(corresponding to one of the CHs), the first 4, 16, 16 bits are don't care DC in the down signal, guard bit G, preamble PRE, and synchronization pattern 5YN in the up signal.
It becomes C. The middle 256 bits are assigned to voice signals or data, and the remaining 10.1.1.4 bits are used for the communication channel control signal S and don't care DC in the downstream signal.

Parity P1 is assigned to don't care DC, and the same <S, DC, P and guard bit G are assigned to the upstream signal.

The pattern of preamble PRE is 1010...
, and the don't care DCs are all 1.

In Figure 3, one frame is 8192 bits, and the time is 4m.
S s so the bit rate is 2048K b/S.

This 800 bits of one frame are stored in time slot zero T.
The remaining 7392 bits of SO are voice channels VCH #1 to #24 of 308 bits each.

The TSO is divided into 16,272,204.308 bits, and these are the synchronization pattern F1 control channel CNTL, don't care DC, and order wire OW for the downlink signal, and the guard focus 01 control channel CNTL and the acquisition channel for the uplink signal. ACQ and order wire OW occupy.

As shown in Figure 4, the acquisition channel consists of a 70-bit guard 0, a 16-bit preamble, a 16-bit synchronization pattern, an 8-bit acquisition pattern, a 6-bit station identification code, a 2-pin don't care DC, It consists of a 6-bit error detection code CRC and a 70-bit lower G.

Adjustment of the transmission timing of uplink signals from subscriber stations is performed by inserting multiple stages of delay circuits into the transmission data circuit, and adjusting the number of stages of the fence circuit according to the number of bits indicating the amount of deviation sent from the base station. be able to. This delay circuit is a flip-flop (register), and if the transmit data is shifted sequentially using a clock, for example, when the base station instructs a 1-bit delay, the transmit data passes through one more stage of flip-flops. You can follow the above instructions by setting the output after

〔Effect of the invention〕

As explained above, in the present invention, there is no need for fine adjustment within the bit, and automatic control is performed, so the adjustment man-hours and adjustment time in the field are reduced, and the system start-up and adjustment time are reduced.
Operation can be done quickly. Furthermore, since phase (shift) fluctuations due to changes over time, temperature changes, etc. can be automatically adjusted, interference between bursts caused by phase fluctuations can be prevented, and system reliability and line quality can be improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a burst signal receiving circuit according to the present invention. Fig. 2 is an explanatory diagram showing an example of a burst signal format. Fig. 3 is an explanatory diagram showing an example of a radio frame format. Fig. 4 is an explanatory diagram showing an example of a wireless frame format. FIG. 5 is an explanatory diagram of the digital subscriber radio system, and FIG. 6 is a detailed explanatory diagram of a part of FIG. In FIG. 1, 30 is a demodulator, 32 is a clock extraction circuit, and 34
is a pattern match detection circuit, 36 is a PIFO register, 3
8 is an inhibitor sotogate.

Claims (2)

[Claims] (1) TD by connecting a base station and multiple subscriber stations via wireless lines
In a signal propagation delay adjustment method from a subscriber station to a base station in a system that communicates using the MA method, the base station:
A receiving circuit including a demodulator (30), a circuit for extracting a clock from the demodulated output (32), a circuit for detecting a synchronization pattern (34), and a FIFO register (36) is provided, and the uplink from the subscriber station to the base station is provided. Guard bits (G) are placed before and after the signal, and a synchronization pattern (SYNC) is included, followed by transmission data (VS). At the base station, the detection circuit (34) detects the synchronization pattern, A propagation delay adjustment method characterized by loading subsequent transmission data into a FIFO register. (2) When the subscriber station starts up the system and/or receives instructions during operation, it sends out uplink signals in a predetermined pattern at appropriate timings so as to enter a predetermined time slot (TSO), and the base station transmits the uplink signals. receive the signal, calculate the deviation from the reference point in the number of bits, insert it into the downlink signal of the predetermined time slot (TSO) and notify the subscriber station, and the subscriber station sends out the uplink signal according to the notified number of bits. 2. The propagation delay adjustment method according to claim 1, wherein the propagation delay adjustment method adjusts timing.