JPS63292336A - Information processor - Google Patents

Abstract

PURPOSE:To quickly restore a system by sending a signal indicating segments of processes and a fault detection signal from the copy source side to the copy destination side and providing a buffer storage on the copy destination side and completing the copying operation after completion of copy of the process, which is copied at present, at the time of reporting fault detection. CONSTITUTION:When a CPU 10 writes data in a main storage device (MM) 20 through an operating bus 30, a duplex controller (MXC) 40 transfers its write address and write data to an MXC 41 through an address data communication bus (X bus) 50. When the fault of the CPU 10, the MM 20, or the bus 30 is detected, it is reported to the MXC 41 by a signal line ERR 60. The MXC 41 stores received write address and data in an internal buffer storage (BUF) 42. The MXC 41 successively reads out stored write address and data and writes them in an MM 21 of the copy destination to complete the copying operation. Thus, the system is quickly restored.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device, and more particularly to an information processing device having a duplex control device between a duplex central control device and a main storage device.

[Conventional technology]

Conventionally, this type of technology involves copying to the main memory of the copy destination at the same time as the copy source or with a small time difference using buffer storage;
The first method interrupts the software to stop copying when a failure occurs on the copy source, and the second method has buffer storage and there is a time difference between the time when writing is performed on the copy source and the time when writing is performed on the copy destination. There is a second method in which copying is stopped even if write information remains in buffer storage if a failure occurs in the copy source.

[Problem that the invention seeks to solve]

Among the conventional methods mentioned above, the first method has the following thinning points. In other words, when there is a failure when writing at the copy source, writing is also being performed at the copy destination, and it may not be possible to stop the copy in time. be.

In addition, in the second method, if the copy source detects a failure and stops immediately, the copy information stored in the buffer memory will not be copied, so stopping is suitable for the cause before the failure is detected, but one process If writing to the main memory is performed multiple times during this process, there may be a logical contradiction within the process, and there is a problem in that this logical contradiction prevents quick recovery from failure.

[Means for solving problems]

The information processing apparatus of the present invention has a buffer memory having a capacity sufficient to store a write address and data generated within one process, receives a signal indicating a process break from a copy source, and stores a process break in the buffer memory. When it receives a failure signal from the copy source, it verifies this bit, writes to the copy destination until the next break, and stops writing for copying at the process break. There is.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram of the duplex control device in FIG. 1.

A redundant central control unit (hereinafter referred to as CPU) 10.11 and a redundant main memory unit (hereinafter referred to as MM) 20.21 each have an address data bus (hereinafter simply referred to as bus>30.31).
connected with. From the bus 30 to the bus 31, there is a redundant control device (hereinafter referred to as MXC) 40.41, and this MXC40,
41 signal line and address data communication bus (hereinafter referred to as
They are logically connected via a bus) 50.

Now, CPU10 is operating and MM2 is connected via bus 3o.
When writing to 0, the MXC 40 transfers the write address and write data to the MXC 41 via the X bus 50. Mana CPU10. MM20. When a failure on the bus 30 is detected, the failure is reported to the MXC 41 via a signal line ERR60. The MXC 41 stores the received write address and data in an internal buffer storage (hereinafter referred to as BUF) 42.

Further, the MXC 41 sequentially reads out the stored write address and data and writes them to the copy destination MM 21, thereby completing the copy operation. Process delimiter signal (hereinafter P
R3C) 70 is “1” only at the first write of each process.
, so that you can see the process boundaries.

In MXC41, the write address and write data information from MXC40 are sent to BUF42 along with the information of PR3C70.
is stored in An example of the content of BUF42 is shown in Figure 3.
R3CF421 is a field indicating a process delimiter, and when it is "1", it indicates that this is the first write information in the next process. ADD 422 is a field indicating a write address, and DATA 423 is a field indicating write data. - Figure 3 shows the process from CPU30 to MM20 at a certain point in time.
Data 201 is written to address 21, then data 20101 address 41'' is written within the same process, and similarly data 20202 address 42'' and 20303 address 43 are written.
", 20404 address 44" is written, and in the next process 205 is written to address 22, then 205
05 address 31" is written, 20606 address 32" is written,
In the next process, 0MXC41, which indicates that "400" has been written to address 12, needs to write (copy) the same data to the same address of MM21. The copy write control circuit (hereinafter referred to as CPCIR) 43 is a block having a circuit that performs this write operation, and is
When the storage of the write address and data information from 40 to BUF 42 for one process is completed, CPCIR 43
is activated, the CPCIR 43 reads the write address and data from the BUF 42, and performs the operation of writing to the MM 21. In reality, a large amount of memory is written within the same process, and a large buffer storage capacity is required.

Now, the contents of Figure 3 are written in BUF42, and BUF
Information with address “3”, that is, “4” to address 202.
MXC4 via ERR60 while writing 2” data.
Assuming that there is a failure report from 0, the CPCIR43 retains that failure report, and after writing up to the BUF address "5", the bit of the process delimiter field PR3CF421 with the BUF address "6" becomes 1. Therefore, when restoring the system to the 0th order where data copying is stopped, the recovery operation is started from the side that was the copy destination, which is the side opposite to the side where the failure was detected, so there is no conflict in the instructions, and the recovery Since the operation can be performed, quick system recovery is possible.

〔Effect of the invention〕

As explained above, the present invention sends a signal indicating a process break and a fault detection signal from the copy source side to the copy destination side, and the copy destination side has buffer storage so that when a fault detection is reported, By completing the copying operation after the process that is currently copying has completed to the end, it is possible to quickly recover the system from the copying destination side by eliminating logical contradictions caused by interruptions in copying within the same process. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram of the duplication control device in FIG. 1, and FIG. 3 is a diagram showing an example of the contents of buffer storage in FIG. 2. 10.11... Central control unit (CPU), 20°21
... Main memory (MM), 30.31 ... Address data bus, 40.41 ... Duplex control device (MX
C), 42...Buffer storage (BUF), 43...
Copy write control circuit (CPCIR), 50...address data communication bus (X bus), 6o...failure report signal ERR170...process delimiter signal (PR3C),
421...Process delimiter field bit (PR3
CF), 422...Write address field (AD
D), 423...Write data field (DATA
). Agent Patent Attorney Otohara Uchihara 1 Figure 2 Figure 3

Claims (1)

[Claims] In a system consisting of a central control unit and a main memory device which are each duplicated, a main memory copying device writes to the main memory device of the other system between the central control units so that the contents of the main memory devices of both systems always match. The main memory copying device has a buffer memory having a capacity sufficient to store write addresses and data to be written to the main memory within one process, and the buffer memory has a main memory address and data to be written to. An information processing apparatus characterized in that, by holding a bit indicating a process execution unit in addition to write information, copying is stopped at a process break when a failure occurs in a copying source apparatus.