JPS63291460A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce a chip size by obtaining a wiring space for passing inner wirings for communicating a signal between control circuits disposed at both sides through a memory cell array, and passing the inner wirings through the space. CONSTITUTION:Spaces are formed among blocks MB1-MB4, which independently designate memory cells MC in the blocks MB1-MB4 to read/write data. A constitution for operating only subarrays 1A, 1B and controlling the other subarrays 1C-1H may be formed. Accordingly, spaces can be obtained among them, and inner wirings 9, 10 are disposed in the spaces. Thus, since the lengths of the wirings 9, 10 are shortened, signal propagation delays between address system controllers 5, 6 and input/output controllers 7, 8 are reduced to shorten an access time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a large-capacity semiconductor memory device, particularly a semiconductor memory device that can minimize signal delays caused by parasitic capacitance and parasitic resistance of internal wiring. ! ! It is related to the device.

[Conventional technology]

Figure 2 shows, for example, an international conference I held in February 1985.
S S CC85 (International 5
olid-3tate C1rcuits Confe
1985) is an array configuration diagram of a 1-megapix 1-dynamic RAM shown in lecture number FAM17.8. In the figure, the memory cell array is divided into a plurality of subarrays 1A to 1H, and each subarray 1
Memory cells MC constituting A to 1H are transistors (not shown).

It is composed of a capacitor cell (not shown), a bit line BL, and a word line WL.

To specify a specific memory cell MC from multiple memory cells MC, use bit! ! jlBL and word line WL must be specified. From that, subarray 1
A row decoder 2A for specifying word line W[ in A is provided corresponding to subarray 1A. Similarly, a row decoder 2B is provided corresponding to the sub-array 1B. The bit line BL of subarray 1A and subarray 1B is shared, and subarray 1A and subarray 1
A column decoder 3 for specifying a bit line BL between
AB is provided. Further, a sense amplifier 4A is provided corresponding to the sub-array 1A for sensing and amplifying the contents of the memory cell MC in the sub-array 1A designated by the row decoder 2A and column decoder 3AB during a read operation. Similarly, a sense amplifier 4B is provided corresponding to the sub-array 1B. As described above,
Sub-array 1A and sub-array 1B share bit IBL and column decoder 3AB, and are related to each other, including sub-arrays IA, 1B, and row decoder 2A.

2B, column decoder 3AB and sense amplifier 4A.

4B constitutes a block MBI.

Similarly, subarrays 1G, 1b, row decoders 2C, 2D
, a row decoder 3CD and sense amplifiers 4G, 4D form a block MB2, a subarray IE, 1F, a row decoder 26.2F, a column decoder 3EF and a sense amplifier 4E, 4F form a block M83, and a subarray 1G, 1['' , row decoders 2G, 2H, column decoders 3GH and sense amplifiers 4G, 4H block M.
It constitutes B4.

Since the blocks MB1 to MB4 are configured as described above, they are mutually independent. And each block M
In order to control the operations of BI to MB4, an address system control circuit 5.6 and an input/output system control circuit 7.8 are provided on both sides of the memory cell array. In addition, since there is a close relationship between these control circuits, the internal wiring 9 for exchanging signals etc. between the address system control circuit 5 and the input/output system control circuit 7 is connected to both υJt [between one circuit Connected. Similarly, an internal wiring 10 is connected between the address system control circuit 6 and the input/output system control circuit 8.

The semiconductor memory device configured as described above operates as follows. Row decoders 2A-2H select word lines WL of sub-arrays 1A-1H, respectively, in response to address signals applied from outside the chip. On the other hand, column decoders 3AB to 3 correspond to address signals applied from outside the chip.
GH selects bit line BL, and subarrays 1A to 1 selected by these word lines WL and pits 1i1BL
Information is read/written to each memory cell MC of H. Here, when reading information from the memory cell MC, a minute voltage on the bit line B[ is detected and amplified by the sense amplifiers 4A to 4H.

The address system control circuit 5.6 and the input/output system control circuit 7.8 that control the circuit operation of the semiconductor memory device are often arranged on the outer periphery of the long side of the semiconductor memory device, as shown in FIG. became. The reason for this is that as storage capacity continues to increase, chip dimensions become larger, and due to constraints such as the lens aperture of the mask exposure device and the cavity dimensions of the package, there is no longer any margin for the long side of the chip. . Among both control circuits, especially the address system control circuit 5
．． 6 needs to be placed on the row decoders 2A to 2H side.

The reason for this is that the function of the address system 11JI11 circuit 5.6 is to convert an external address signal into an address signal of a format used in the row decoders 2A-2 and column decoders 3A8-3GH. On the other hand, the input/output system control circuit 7.8 is placed on the opposite side of the address system control circuit 5.6 across the memory cell array due to design constraints such as wiring.

It is necessary to closely transmit and receive signals between these two control circuits via internal wirings 9 and 10. The reason for this is that input/output control is changed in response to changes in address signals, and operation modes that utilize feedback/feedforward of various address and input/output signals to improve performance have been adopted. This is because it has become.

At the same time, as storage capacity increases, the number of divisions of memory cell arrays also increases. The reason is the bit line BL
This is to improve the operating margin of information read/write operations for the memory cell by shortening the length of the memory cell.

[Problem that the invention seeks to solve]

As described above, in the conventional semiconductor memory device, the internal wires 9 and 10 for transmitting and receiving signals between the address system control circuit and the input/output system control circuit are arranged to pass through the outer periphery of the memory cell array. As a result, the length of the internal wiring 19 and 10 becomes long, and their strange resistance and parasitic capacitance become large, causing a delay in the propagation speed of signals passing through the internal wiring 9 and 10, and the delay of the wiring passing through the corners of the chip. There were problems such as an increase in the number of chips and an increase in chip size.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor memory device that can shorten the length of internal wiring between control circuits and also prevent an increase in chip size. do.

[Means for solving problems]

The present invention provides a semiconductor memory device in which a wiring space is secured for passing internal wiring for transmitting and receiving signals between control circuits located on both sides of a memory cell array between independent blocks, and Internal wiring is passed through the wiring space.

[Effect]

In the semiconductor memory device of the present invention, by passing the internal wiring between independent blocks, the width of the internal wiring can be shortened, and the signal propagation delay can be reduced. moreover,
Since the number of wires passing through the corners of the chip can be reduced, the increase in chip size can also be suppressed.

〔Example〕

FIG. 1 shows an embodiment of the present invention, 1 to 10 MB
1-MB4. MC, BL and WL are exactly the same as the conventional device. In this figure, each block MB1~
A space is provided between MB4. This is because, as described above, each block M81 to M84 can independently designate the memory cell MC in each block MB1 to MB4 and perform data read/write operations. As an extreme example, a configuration in which only subarrays IA and 1B are operated and the other subarrays 1C to 1H are controlled is also possible. Therefore, it is possible to secure a space between them, and the internal wirings 9 and 10 are arranged in these spaces.

By configuring as shown in E, internal wiring 9.10
Since the length of is shortened, it is possible to reduce the signal propagation delay between address system control circuits 5 and 6 and input/output system control circuits 7 and 8. Thereby, the operation of detecting a change in the address signal applied from outside the chip, transmitting the detection signal to the input/output circuit, and switching the data output can be executed quickly, and the access time can be shortened. Further, it is possible to quickly perform a feedback operation such as detecting that the data output signal has been determined and sending the detection signal to the address system control circuits 5 and 6 to prepare for address application in the next cycle.

Furthermore, since the number of wires passing through the corners of the chip can be reduced, an increase in chip size can be suppressed.

In the above embodiment, dynamic RAM was explained, but static RAM, EPROM, EEPRO
M or mask ROM may be used, and the same effects as in the above embodiments can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, a wiring space is secured for passing the internal wiring for transmitting and receiving signals between the control circuits located on both sides of the memory cell array, and the internal wiring is routed through the wiring space. This has the effect of providing a semiconductor memory device with high speed and small chip size.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional semiconductor memory device. In the figure, 1A to 1st are sub-arrays, 2A to 2nd are row decoders, 3A8 to 3GH are column decoders, 4A to 4H are sense amplifiers, 5 and 6 are address system control circuits, and 7 and 8 are input/output system control circuits. , 9.10 is internal wiring, MBI~MB
4 is a block. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 9, 10-11 Meat Wholesaler 6 Otsuen MBI-MB4
---Plot 7 Figure 2

Claims (2)

[Claims] (1) A memory cell array is divided into a plurality of subarrays, a row decoder, a column decoder, and a sense amplifier, each having a plurality of blocks that can be addressed independently, and a block for controlling the operation of the blocks. In a semiconductor memory device in which control circuits are provided spaced apart on both sides of the memory cell array, and the control circuits are electrically connected by internal wiring, a wiring space is secured between the blocks, and the internal wiring is connected to the wiring. A semiconductor storage device characterized by having a space passed through it. (2) The control circuit includes an address system control circuit and an input/output system control circuit, and both control circuits are provided spaced apart on both sides of the memory cell array. semiconductor storage device.