JPS63290163A - Switching power source circuit - Google Patents

Switching power source circuit

Info

Publication number
JPS63290163A
JPS63290163A JP12479087A JP12479087A JPS63290163A JP S63290163 A JPS63290163 A JP S63290163A JP 12479087 A JP12479087 A JP 12479087A JP 12479087 A JP12479087 A JP 12479087A JP S63290163 A JPS63290163 A JP S63290163A
Authority
JP
Japan
Prior art keywords
circuit
switching element
winding
output
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12479087A
Other languages
Japanese (ja)
Inventor
Kiyonobu Hayazaki
早崎 喜代信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12479087A priority Critical patent/JPS63290163A/en
Publication of JPS63290163A publication Critical patent/JPS63290163A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve efficiency and to reduce noise, by carrying out pulse width control of a switching power source only in respective secondary circuits. CONSTITUTION:A power source 1 is connected in series with the primary winding 4a, of a transformer 4 and a switching element 3, then the switching element 3 is ON/OFF controlled through alternating pulses fed from an oscillation circuit 2. A load 8 is connected through a rectifier circuit comprising a switching element 5 and a bypass diode Db and a smoothing circuit comprising a coil L and a capacitor C to the secondary winding 4b of the transformer 4. Here, a control winding 4c is connected in series with the winding 4b of the transformer 4 with one end thereof being connected through a bias resistor R with the gate of the switching element 5. Furthermore, pulses are fed from a pulse width control circuit 10 for controlling ON pulse width corresponding to the output voltage from the smoothing circuit are fed to the gate of the switching element. Consequently, output current can be controlled.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はスイッチング電源回路に関し、特に多出力用に
好適なスイッチング電源回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switching power supply circuit, and particularly to a switching power supply circuit suitable for multiple outputs.

〔従来の技術〕[Conventional technology]

従来の多出力用のスイッチング電源回路は、第4図の回
路図に示すように、電圧変換用のトランス6の2次側を
複数巻線とし、各2次巻線に巻線電圧整流用およびバイ
パス用のダイオードD1およびD2から成る整流回路並
びにコイルL1およびコンデンサC1から成る平滑回路
を接続した上で、そのうちの1出力(負荷8−2の出力
)電圧が所定値になるようパルス幅制御回路13で1次
側のスイッチング素子3をオンオフ制御し、他方の出力
は平滑後更にパルス幅制御回路12でスイッチング素子
15をオンオフ制御して、このあとのダイオードD3、
コイルL3及びコンデンサC3から成る平滑回路の制御
を行なっている。
In the conventional multi-output switching power supply circuit, as shown in the circuit diagram of FIG. After connecting a rectifier circuit consisting of bypass diodes D1 and D2 and a smoothing circuit consisting of a coil L1 and a capacitor C1, a pulse width control circuit is installed so that the voltage of one output (output of load 8-2) becomes a predetermined value. 13 controls the switching element 3 on the primary side on and off, and after smoothing the other output, the pulse width control circuit 12 controls the switching element 15 on and off, and the subsequent diode D3,
It controls a smoothing circuit consisting of a coil L3 and a capacitor C3.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の多出力用のスイッチング回路° は、1
出力電圧のみでパルス幅制御したオンオフ信号を1次側
に帰還する方式を適用しているので、この1出力側の負
荷変動等に伴ってこれに接続している2次巻線電圧が上
昇すると、1次側のスイッチング素子のオン期間を短縮
するよう帰還制御する。この結果、帰還側の負荷電圧は
所定値を保持できるが、他の2次巻線電圧が下り過ぎる
と、これに接続している負荷電圧を所定値に保持できな
くなる。このように制御不可能状態を回避するため、従
来のスイッチング電源回路では、制御用出力電圧に対す
る他の出力電圧の比が1以下(トランスの設計によって
は数分の1以下)に制限されるという欠点がある。
The conventional multi-output switching circuit described above is 1
Since a method is adopted in which the on/off signal whose pulse width is controlled only by the output voltage is fed back to the primary side, if the voltage of the secondary winding connected to this increases due to load fluctuations on this 1st output side, , performs feedback control to shorten the on period of the primary side switching element. As a result, the load voltage on the feedback side can be maintained at a predetermined value, but if the voltage of the other secondary windings drops too much, the load voltage connected thereto cannot be maintained at a predetermined value. In order to avoid such an uncontrollable state, in conventional switching power supply circuits, the ratio of other output voltages to the control output voltage is limited to less than 1 (or less than a fraction depending on the design of the transformer). There are drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の回路は、1つの1次巻線と出力用および制御用
の各巻線から成る少くとも1組の2次巻線とを有するト
ランスと、前記1次巻線に直列接続したスイッチング素
子と、該スイッチング素子のオンオフ制御信号を発生す
る発振器と、各前記出力用巻線の両端間にFET (電
界効果トランジスタ)のソース及びドレイン間と転流用
のダイオードとを直列接続し該FETのゲート電圧を前
記制御用巻線から与える構成を有し該ダイオードの両端
を出力端にした整流回路と、各該整流回路の出力端に継
続接続した平滑回路と、各該平滑回路の出力電圧に応答
して前記FETへ前記ゲート電圧を与えるタイミングを
制御する制御回路とを、備えている。
The circuit of the present invention includes a transformer having one primary winding and at least one set of secondary windings each consisting of an output winding and a control winding, and a switching element connected in series to the primary winding. , an oscillator that generates an on/off control signal for the switching element, and a commutating diode connected in series between the source and drain of an FET (field effect transistor) between both ends of each of the output windings to determine the gate voltage of the FET. a rectifier circuit having a configuration in which the control winding provides output voltage from the control winding, with both ends of the diode being output terminals, a smoothing circuit continuously connected to the output terminal of each of the rectifier circuits, and a smoothing circuit that responds to the output voltage of each of the smoothing circuits. and a control circuit that controls the timing of applying the gate voltage to the FET.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例を示す回路図である。電
源1は、入力直流電源であり、トランス4の1次側の巻
線4aおよびスイッチング素子3(Nチャンネルの電界
効果トランジスタ(FET)のソース及びドレイン間)
に直列接続しである。スイッチング素子3は、発振回路
2から(FETのゲートに)与えられる交番パルスでオ
ンオフ制御される。トランス4の2次側出力用の巻線4
bには、スイッチング素子5 (FETのソース及びド
レイン間)およびバイパス用のダイオードDbから成る
整流回路と、コイルし及びコンデンサCから成る平滑回
路とを経て、負荷8が接続されている0巻線4bに直列
に設けた制御用の巻線4Cの一端は、バイアス用の抵抗
Rを介してスイッチング素子5の制御端子(FETのゲ
ート)に接続しである。更に平滑回路の出力電圧に応じ
てオンパルス幅を制御するパルス幅制御回路10の送出
パルスを、スイッチング素子の制御端子に与えておく。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. A power supply 1 is an input DC power supply, and includes a winding 4a on the primary side of a transformer 4 and a switching element 3 (between the source and drain of an N-channel field effect transistor (FET)).
Connected in series. The switching element 3 is turned on and off by an alternating pulse given from the oscillation circuit 2 (to the gate of the FET). Winding 4 for secondary output of transformer 4
0 winding to which a load 8 is connected to b through a rectifier circuit consisting of a switching element 5 (between the source and drain of the FET) and a bypass diode Db, and a smoothing circuit consisting of a coil and a capacitor C. One end of the control winding 4C provided in series with the control winding 4b is connected to the control terminal (gate of the FET) of the switching element 5 via a bias resistor R. Furthermore, the output pulse of the pulse width control circuit 10, which controls the on-pulse width according to the output voltage of the smoothing circuit, is applied to the control terminal of the switching element.

今、1次側のスイッチング素子3がオンすると、巻線4
bに電圧が現るると共に巻線4cの電圧によりスイッチ
ング素子5がオンして、整流回路から出力電圧を得る0
次いでスイッチング素子3がオフした時点で、巻線4C
の駆動電圧は消滅し、スイッチング素子5がオフすると
共にダイオードDbがオンし整流電流を持続させる。出
力電圧が上昇していき、パルス幅制御回路10の制御範
囲に入った時点では、スイッチング素子3がオンの状態
でもパルス幅制御回路10の出力オンによりスイッチン
グ素子5のゲート電圧がしゃ断され、スイッチング素子
5がオフしてダイオードDbに転流するので、これによ
り定常状態での出力電圧制御を行える。又、2次回路の
電流検出信号をパルス幅制御回路10に与えることによ
り、出力電流制御を行うことも出来る。
Now, when the switching element 3 on the primary side turns on, the winding 4
When a voltage appears on b, the switching element 5 is turned on by the voltage on the winding 4c, and the output voltage is obtained from the rectifier circuit.
Next, when the switching element 3 is turned off, the winding 4C
The driving voltage disappears, the switching element 5 turns off, and the diode Db turns on to maintain the rectified current. When the output voltage increases and enters the control range of the pulse width control circuit 10, even if the switching element 3 is on, the gate voltage of the switching element 5 is cut off by the output on of the pulse width control circuit 10, and the switching Since element 5 is turned off and current is commutated to diode Db, the output voltage can be controlled in a steady state. Further, output current control can be performed by applying a current detection signal of the secondary circuit to the pulse width control circuit 10.

第2図は本発明の第2の実施例を示す回路図であり、−
スイッチング素子5の制御をPチャンネルのFE中12
で駆動する点が第1図と異なる。本回路の基本動作は第
1図と同じであるが、パルス幅制御回路11の動作が常
時オンであり、制御回路が働いた時のみオフになる反転
動作となっている点が異なる。この回路では、第1図に
比ベパルス幅制御回路11の駆動電力が小さくて済むと
共に、第1図のバイアス用の抵抗Rを無くしてスイッチ
ング素子5のオンスピードを速くできる利点がある。
FIG. 2 is a circuit diagram showing a second embodiment of the present invention, -
The switching element 5 is controlled during the P channel FE 12.
It differs from Fig. 1 in that it is driven by . The basic operation of this circuit is the same as that in FIG. 1, except that the operation of the pulse width control circuit 11 is always on and is an inverted operation that is turned off only when the control circuit is activated. This circuit has the advantage that the driving power of the pulse width control circuit 11 compared to that shown in FIG. 1 can be small, and that the on-speed of the switching element 5 can be increased by eliminating the bias resistor R shown in FIG.

第3図は第1の実施例の多出力電源への応用例を示す回
路図であり、トランス6の2次側にn個の巻線及び回路
を設け、各出力で独立に電圧制御を行うことにより、安
定した出力電圧を各負荷相互間のバランスに無関係に得
ることができる。
FIG. 3 is a circuit diagram showing an example of application of the first embodiment to a multi-output power supply, in which n windings and circuits are provided on the secondary side of the transformer 6, and voltage control is performed independently at each output. As a result, a stable output voltage can be obtained regardless of the balance between the loads.

第3図の回路では、直流コンバータの発振周期が発振回
路2で設定した単−且つ固定の周波数である為従来回路
(第4図)での(パルス幅制御回路12および13の)
多重発振形の場合のような各出力のビートにより低周波
雑音の発生が無く、音声帯域の雑音が制限される交換器
用多出力電源に時している。又、第4図の第2出力がス
イッチング素子3及び15の2段スイッチングになって
いるのに比べ、全回路が1段スイッチングなので、電力
交換ロスが小さく、更にスイッチング素子5がFETで
ある為、オン抵抗を小さくできるので、第4図での通常
のダイオードD!に比べ順方向電圧効果を小さくするこ
とができ、低損失の直流コンバータが実現できる。
In the circuit shown in Fig. 3, the oscillation period of the DC converter is a single and fixed frequency set by the oscillation circuit 2.
Unlike the case of a multiple oscillation type, low frequency noise is not generated due to the beat of each output, and noise in the voice band is limited, making it suitable for a multi-output power supply for an exchanger. Also, compared to the second output shown in Fig. 4, which has two-stage switching of switching elements 3 and 15, the entire circuit is one-stage switching, so the power exchange loss is small, and furthermore, since switching element 5 is an FET, , the on-resistance can be reduced, so the normal diode D! The forward voltage effect can be reduced compared to the conventional method, and a low-loss DC converter can be realized.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、トランスの1次側のオン
オフをフリーランの発振器で制御し、2次側の出力巻線
にFETスイッチを接続し且つ2次側の制御巻線をFE
Tスイットのドレイン・ゲート間に接続すると共に、出
力電圧制御用の回路でFETスイッチのオフタイミング
をゲート制御するよう構成することにより、スイッチン
グ電源のパルス幅制御を各2次側回路のみで実施できる
為、トランスの2次側に本回路を複数個並列に並べるだ
けで任意出力数の多出力電源回路を構成できる。この結
果、従来の多出力電源に比べ高効率で且つ低ノイズの電
源を実現できる上、制御信号形が2次側で完結している
ので、1次−2次間の結合が小さく高耐圧の電源が容易
に実現できる効果がある。
As explained above, the present invention controls the on/off of the primary side of the transformer using a free-running oscillator, connects the FET switch to the output winding of the secondary side, and connects the control winding of the secondary side to the FE
By connecting between the drain and gate of the T-switch and configuring the output voltage control circuit to gate control the off timing of the FET switch, pulse width control of the switching power supply can be performed only with each secondary circuit. Therefore, a multi-output power supply circuit with an arbitrary number of outputs can be constructed simply by arranging a plurality of this circuits in parallel on the secondary side of the transformer. As a result, it is possible to realize a power supply with higher efficiency and lower noise than conventional multi-output power supplies, and because the control signal form is completed on the secondary side, coupling between the primary and secondary is small and high withstand voltage is achieved. This has an effect that can be easily realized by a power source.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は本発明の実施例を示す回路図、第4図
は従来のスイッチング電源回路の構成を水回路図である
。 1・・・入力電源、2・・・発振回路、3,5.5−1
〜5−n、15・・・スイッチング素子、4.6・・・
トランス、8 、8−1〜8− n−・負荷、10〜1
3.10−1〜10−n・・・パルス幅制御回路、RH
RI〜Rn、r・・−抵抗、L、L1〜Ln−・コイル
、C,C1〜Cn−1ンデンサ、D1〜D3゜Db、D
b 1−Dbn−−−ダイオード。 $ I 閉 茅 2 凹 茅 3 図 茅 4 図
1 to 3 are circuit diagrams showing embodiments of the present invention, and FIG. 4 is a water circuit diagram showing the configuration of a conventional switching power supply circuit. 1... Input power supply, 2... Oscillation circuit, 3, 5.5-1
~5-n, 15... switching element, 4.6...
Transformer, 8, 8-1 to 8- n- load, 10 to 1
3.10-1 to 10-n...Pulse width control circuit, RH
RI~Rn, r...-resistance, L, L1-Ln--coil, C, C1-Cn-1 capacitor, D1-D3゜Db, D
b 1-Dbn---diode. $ I Closed grass 2 Concave grass 3 Figure grass 4 Figure

Claims (1)

【特許請求の範囲】[Claims] 1つの1次巻線と出力用および制御用の各巻線から成る
少くとも1組の2次巻線とを有するトランスと、前記1
次巻線に直列接続したスイッチング素子と、該スイッチ
ング素子のオンオフ制御信号を発生する発振器と、各前
記出力用巻線の両端間にFET(電界効果トランジスタ
)のソース及びドレイン間と転流用のダイオードとを直
列接続し該FETのゲート電圧を前記制御用巻線から与
える構成を有し該ダイオードの両端を出力端にした整流
回路と、各該整流回路の出力端に継続接続した平滑回路
と、各該平滑回路の出力電圧に応答して前記FETへ前
記ゲート電圧を与えるタイミングを制御する制御回路と
を、備えているスイッチング電源回路。
a transformer having one primary winding and at least one set of secondary windings each consisting of an output winding and a control winding;
A switching element connected in series to the next winding, an oscillator that generates an on/off control signal for the switching element, and a commutation diode between the source and drain of an FET (field effect transistor) between both ends of each of the output windings. a rectifier circuit having a configuration in which the FETs are connected in series and the gate voltage of the FET is applied from the control winding, and both ends of the diode are used as output ends; and a smoothing circuit continuously connected to the output ends of each of the rectifier circuits. A switching power supply circuit comprising: a control circuit that controls the timing of applying the gate voltage to the FET in response to the output voltage of each of the smoothing circuits.
JP12479087A 1987-05-20 1987-05-20 Switching power source circuit Pending JPS63290163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12479087A JPS63290163A (en) 1987-05-20 1987-05-20 Switching power source circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12479087A JPS63290163A (en) 1987-05-20 1987-05-20 Switching power source circuit

Publications (1)

Publication Number Publication Date
JPS63290163A true JPS63290163A (en) 1988-11-28

Family

ID=14894186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12479087A Pending JPS63290163A (en) 1987-05-20 1987-05-20 Switching power source circuit

Country Status (1)

Country Link
JP (1) JPS63290163A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5490522A (en) * 1977-12-28 1979-07-18 Fujitsu Ltd Power circuit
JPS5788875A (en) * 1980-11-21 1982-06-02 Fujitsu Ltd Dc/dc converter
JPS57156670A (en) * 1981-03-20 1982-09-28 Shindengen Electric Mfg Co Ltd Dc-dc converter
JPS60156269A (en) * 1984-01-25 1985-08-16 Fujitsu Ltd Dc/dc converter
JPS6318962A (en) * 1986-07-09 1988-01-26 Nichicon Corp Switching power source

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5490522A (en) * 1977-12-28 1979-07-18 Fujitsu Ltd Power circuit
JPS5788875A (en) * 1980-11-21 1982-06-02 Fujitsu Ltd Dc/dc converter
JPS57156670A (en) * 1981-03-20 1982-09-28 Shindengen Electric Mfg Co Ltd Dc-dc converter
JPS60156269A (en) * 1984-01-25 1985-08-16 Fujitsu Ltd Dc/dc converter
JPS6318962A (en) * 1986-07-09 1988-01-26 Nichicon Corp Switching power source

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