JPS63285035A - Clock control system - Google Patents

Abstract

PURPOSE:T maintain the stuff rate and the frequency accuracy as it is by using a reception asynchronous clock obtained from a reception data from an opposite station through smoothing at a PLO after destuffing as a low-order group input clock when a low-order group input clock is interrupted. CONSTITUTION:When a low-order group input clock CSL is interrupted, it is detected by a clock interruption detection circuit 1 and a selector 2 outputs selectively a clock CRL from a reception PLO 16 to input the clock CRL to a phase comparator 4, on the other hand, in an AIS (Alarm Indication Signal) insertion circuit 5, the AIS signal is outputted as a transmission data. Since the clock CRL from the reception PLO 16 satisfies the specified frequency accuracy, the phase comparator 14 is operated normally,a stuff bit is inserted by a stuff insertion circuit 6 at a specified stuff rate and the AIS signal with normal stuff inserted thereto is multiplexed by a multiplex circuit 8 and sent to the opposite station.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clock control method in a stuff multiplexing converter that performs asynchronous multiplexing at a constant stuffing rate, particularly when a low-order group input clock is disconnected. The receiving PL
This invention relates to a clock control method in which a smoothed clock from O is used as a low-order group input clock.

[Prior art] In conventional asynchronous multiplex conversion devices, rPCM-
100M multiplex conversion device (part 3)” (S-25-5
, page +05-112), stuffing pulses are inserted at a constant stuffing rate, and the sending clock frequency accuracy is ±1 for 32M and 100M.
It is now defined as Opp+*.

On the other hand, as a monitoring method, rPCM-24G relay transmission method terminal station relay equipment" (Research Practical Application Report Vol. 30, No. 12)
As shown in , if the input clock of the local low-order group is disconnected, the corresponding channel in the high-order group receives A.
IS (A alarm indication)
ignal) signal (full mark signal) is inserted, and the lower-order group in the game is notified as a warning to its subordinate devices.

[The problem to be solved by the invention] By the way, in the stuff multiplex conversion device, such an AIS sending method is not taken into account, and when the AIS signal is sent out when the low-order group input clock is cut off, The staffing rate and frequency accuracy have not been considered.

If the low-order group input clock is cut off at the own station, the transmission phase comparator will not operate normally due to the clock cutoff, and therefore the stuff pulse insertion operation performed based on the phase comparison result will also not be carried out normally. As a result, the transmission stuffing rate becomes abnormal, and in the game that receives this, the frequency accuracy of the PLO output smoothing clock after destuffing the received data deteriorates, and the frequency accuracy from that game to lower-level equipment also exceeds the standard. This results in the lower device being unable to synchronize the received bits, making it impossible for the lower device to detect the AIS signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock control method that makes it possible to maintain the stuffing rate and frequency accuracy even when the input of the low-order group clock is cut off.

[Means for solving the problem] The above purpose is to reduce the received asynchronous clock obtained by smoothing with PLO after destuffing the received data from the game when the low-order group input clock is disconnected. This is achieved by using it as the next group input clock.

[Effect] The received PLO output clock is obtained by smoothing the received data after destuffing, but since the destuffing is based on the transmission stuff insertion in the game, the receive PLO output clock frequency is the same as that in the game. It is the same as the asynchronous low-order group clock frequency before stuffing. Therefore, as long as the frequency accuracy of the low-order group clock in the game is maintained, the PLO output clock obtained at the own station also maintains its frequency accuracy, and this is used as the transmit clock of the own station. In this case, the insertion stuffing rate remains the same. Stuff pulses are inserted at the same stuffing rate in both transmit and receive directions, and the PLO output clock frequency is the same for both games, so there will be no malfunction even if the received PLO output clock is used as the low-order group input clock. be.

[Example] The present invention will be explained below with reference to FIGS. 1 and 2.

First, before entering into a detailed explanation of the present invention, a PCM multiplex transmission system using a plurality of multiplex converters will be explained.
FIG. 2 shows an example of the system configuration. As shown in the figure, in the multiplex converter (PCM-32M multiplex converter) 18, five low-order group signals are multiplexed into five, but these five multiplexed signals are sent to the other two multiplex converters (PCM-32M multiplex converter) 18.
M-32M multiplex converter) (not shown) are multiplexed into three multiplexed signals from each multiplex converter (PCM-100M multiplex converter) 19, and then transferred to the multiplex converter (PCM-100M multiplex converter) ) 20. In the multiplex converter 20, the three multiplexed signals are demultiplexed (separated) into three systems of signals, and each of the signals separated into three systems is further demultiplexed by the corresponding three multiplex converters (PCM-32M multiplex converter). [
) 21, it is demultiplexed into five systems of low-order group signals. Multiplexing and demultiplexing of signals in the opposite direction is also similar. In the present invention, for example, when the multiplex converter 19 detects an interruption in the input of the low-order group clock from the multiplex converter 18, the clock to the multiplex converter 18 is used to transmit the input to the multiplex converter 20, which is the opponent game. An AIS signal is inserted into the corresponding channel.

Now, to explain the present invention in detail, FIG. 1 shows the configuration of an example of a multiplex conversion apparatus according to the present invention.

Analog parts such as the U (unipolar)/B (bipolar) converter and B/U converter are not shown, but the overall configuration is roughly divided into a transmitting system and a receiving system. .

First, to explain the operation under normal conditions, that is, when the low-order group input clock is normal, in the transmission system, the low-order group input clock C8L extracted from the low-order group transmission data DSL is normal. Therefore, the clock loss detection circuit 1 does not detect a clock loss, and the low-order group input clock C
5L is input to the buffer memory 3 and the phase comparison circuit 4 via the selector 2. The low-order group transmission data DSL is written into the buffer memory 3 by the low-order group input clock C8L, but reading from the buffer memory 3 is performed by the synchronized clock from the high-order group transmission clock generation circuit 9 via the AND gate 7. There is. Low-order group transmission data DSL read out from buffer memory 3
In this case, the AIS signal is not inserted in the AIS insertion circuit 5, and the stuff bit and its control flag are inserted in the stuff insertion circuit 6 via the AIS insertion circuit 5. The phase comparison circuit 4 detects the phase difference between the low-order group input clock C8L and the synchronized clock from the transmission clock generation circuit 9 via the AND gate 7. This detection result causes the stuff insertion circuit 6 to The insertion of bits and their control flags is controlled. AND gate 7 when inserting the stuff pit
By masking the synchronization clock by one pulse, reading of the low-order group transmission data DSL from the buffer memory 3 is prohibited. The low-order group transmission data DSL from the stuffing insertion circuit 6 is multiplexed with data from other line correspondence sections as transmission data of the line corresponding section by a multiplexing circuit 8, and is transmitted to the opposing station as high-order group data DSH. However, the high-order group data DSH is the high-order group clock C8.
It is now transmitted to the opposing team in a form that includes H.

On the other hand, in the receiving system, the high-order group input clock CRH is extracted from the received high-order group data DRH from the game, but the high-order group data DRH is separated in accordance with the line by the separation circuit 10, and the low-order group input clock CRH is extracted from the received high-order group data DRH from the receiving clock circuit 11. It is sent to the corresponding line corresponding section together with the group clock. In each line corresponding section, when the stuff detection circuit 13 detects a stuff bit from the control flag,
In order to remove the stuff bit, the low-order group clock is divided by one pulse by the AND gate 14, thereby inhibiting the writing of low-order group data into the buffer memory 15. When the stuff bit is detected, the AND gate 14 obtains a low-order group clock with a so-called toothless state. In this case, the state clock is also an asynchronous clock CRL smoothed by the receiving PLO (phase locked oscillator) 16, but data is read from the buffer memory 15 by this clock CRL, and the clock CRL The AIS insertion circuit 17 includes the lower-order group data DRL, which is output to the lower-order device as it is. If the high-order group data DRH is an AIS signal, the AIS detection circuit 12 detects this fact, and based on this detection result, the AIS insertion circuit 17 outputs the AIS signal as the low-order group data DRL. It is something that

Now, to explain the case where the low-order group input clock is disconnected, when the low-order group input clock C8L is disconnected, this is detected by the clock disconnection detection circuit 1. Then, in selector 2, receive PLO1
By selectively outputting the clock CRL from A 6, the clock CRL is inputted to the phase comparator circuit 4.
The IS insertion circuit 5 outputs the AIS signal as transmission data. Since the clock CRL from the reception PLO 16 satisfies the specified frequency accuracy, the phase comparator circuit 4 operates normally, and stuffing bits are inserted from the stuff insertion circuit 6 at the specified stuffing rate. There is. Therefore, the AI in which the staff was successfully inserted
Since the S signal is multiplexed by the multiplexing circuit 8 and sent to the game player, after the received data is separated by the separation circuit in the game game, stuff bits are normally detected and removed, so that the reception PLO is Since the low-order group clock is smoothed, the accuracy of the low-order group output clock frequency of the game is maintained. To further explain this situation with reference to FIG. 2, if the low-order group input clock is disconnected at the local station 19, an AIS signal is inserted into the corresponding low-order group channel, and then the stuff is inserted normally as described above. After being multiplexed, it is sent to the game player 20. At the game station 20, after separating the received data for each line, it is normally destuffed to maintain frequency accuracy and send the separated data (contents are Al5) to the low-order group lower device 21.

In the lower bag v121 that received this, bit synchronization is normally achieved and it is possible to detect that the data is an AIS signal.

[Effects of the Invention] As explained above, according to the present invention, even if the low-order group clock is disconnected in the stuffing multiplex conversion device, the transmission stuffing rate and the frequency accuracy of the receiving PLO output clock in the game can be maintained. This has the effect that the AIS signal can be reliably transmitted to the lower players of the game.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an example of a stuff multiplex conversion apparatus according to the present invention, and FIG. 2 is a diagram showing the system configuration of an example of a PCM multiplex transmission system. DESCRIPTION OF SYMBOLS 1... Clock disconnection detection circuit, 2... Selector, 3゜15... Buffer memory, 4... Phase comparison circuit, 5
...AIS insertion circuit, 6...Stuff insertion circuit, 7
, 14...AND gate, 8...Multiple circuit, 10...
...Separation circuit, 12...AIS detection circuit, 13...
Stuff detection circuit, 16...reception PLO.

Claims (1)

[Claims] 1. Transmission buffer memory, transmission clock phase comparison circuit,
A clock control method in a stuffing multiplex conversion device including a low-order group input clock disconnection detection circuit, an AIS insertion circuit, a stuff insertion circuit, a reception stuff detection/removal circuit, a reception buffer memory, and a reception PLO, If clock interruption is detected, receive PLO
A clock control method characterized by using a smoothed output clock as a low-order group input clock.