JPS63282777A - Modulo computation processor chip - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a modulo arithmetic processor chip for performing addition, multiplication, and exponent calculation regarding a Galois field consisting of remainders of integers modulo a prime number.

[Prior Art and Problems to be Solved by the Invention] A cryptographic system for transmitting a computable security code generated from a transformed text of a known message transmitted by a transmitter is disclosed in U.S. Pat. .200.77
No. 0, U.S. Patent No. 4.405.82 to Levest et al.
No. 9, U.S. Pat. No. 4,218.582 to Hellman et al.
No. 4,424.414 to Hellman et al.
It has been described in several patents, including No.

These patents generally disclose the broad concept of using a secure cipher encryption key, which is generated from a transformed text of transformed signals exchanged by a set of converters. Each converter in a set processes a secret signal and exchanges a first public translation of the secret signal with the other converters. The received public transformation of the other converter's private signal is again transformed into the receiving other converter's private signal to generate a security cipher encryption key. The above conversion uses known operations that are easy to perform but extremely difficult to reverse. After obtaining either the secret signal of the converter or a copy of the latter transformed text, it is not practicable to reverse transform the first public transformed text by an eavesdropping device in order to obtain the confidentiality cipher encryption key. be.

These patents do not disclose the special means or devices necessary to implement their broad patentable concepts.

In particular, these patents do not disclose how to configure the processor chip to perform the necessary transformations to pass the security key.

Furthermore, these patents do not disclose or suggest how to implement these transformations in a fast manner on a processor chip.

An object of the present invention is to provide a processor chip for performing addition, multiplication, and exponent calculation regarding a Galois field consisting of remainders of integers modulo a prime number.

Another object of the invention is to provide a processor chip for performing exponent calculations in a fast manner.

[Means and operations for solving the problem] According to the present invention, as will be described in detail later, a processor chip is provided for adding an n-bit first integer to an n-bit second integer. . Here, the remainder modulo the n-bit fourth integer regarding the data of the addition result of the first integer and the second integer is equal to the n-bit third integer, and the processor chip the first to store an integer of 1
, second register means for storing the second integer, and feedback means for generating and storing a feedback number. The number of feedbacks is 2 of the fourth integer.
is the complement of The present invention includes arithmetic means connected to the first register means and the second register means. The calculation means adds the first integer to the second integer, thereby generating the third integer. At this time, the third integer is stored in accumulator means connected to the arithmetic means. The invention further includes overflow means connected to said accumulator means for storing an overflow integer overflowing from said third integer. Furthermore, the above feedback number is
Means are provided for fetching the returned number into a register and using the arithmetic means to add the returned number to the third integer stored in the accumulator means. Also provided are means connected to the accumulator means for responsive to the third integer being greater than the fourth integer and converting the third integer into a remainder modulo the fourth integer. .

A second concept of the invention includes a modulo arithmetic processor chip for multiplying an n-bit first integer by an n-bit second integer. Here, the remainder modulo the n-bit fourth integer regarding the data of the addition result of the first integer and the second integer is equal to the n-bit third integer. The modulo arithmetic processor chip for multiplication includes a first register means for storing the first integer and a second register means for storing the first integer.
and feedback means for generating a feedback number. Here, the feedback number is a two's complement of the fourth integer, and the feedback number is connected to the first register means and the second register means.
calculation means for adding the second integer to the third integer in response to the lowest digit of the first integer being shifted to the right from the register means. Accumulator means are provided connected to the arithmetic means for storing the third integer. The present invention also provides overflow means connected to the accumulator means for counting and storing overflow bits as an overflow integer, the overflow means, the feedback means, the first register means, and the second register means. and transmitting the overflow integer to the first register means and transmitting the feedback number to the second register means in response to completion of the multiplication of the first integer and the second integer to generate a product. and second partial conversion means for multiplying said feedback number by said overflow integer and adding said product to said third integer stored in said accumulator register means. Means are provided connected to said accumulator means for responsive to said third integer being greater than said fourth integer for converting said third integer to a remainder modulo said fourth integer. The present invention also provides a method for changing the feedback number to the second integer in response to the most significant part of the second integer being connected to the second register means and moved by a left digit from the second register means. and first partial conversion means for adding and thereby converting a portion of said second integer.

Other objects and advantages of the invention will be set forth below, or will be apparent in part from the description that follows.

Alternatively, other objects and advantages of the invention may be obtained in part from actual use of the invention.

[Effects of the Invention] As explained above, according to the present invention, there are two register means for storing the first and second integers, a feedback means for generating and storing the feedback number, and the first and second register means for storing the first and second integers. an arithmetic means for adding or multiplying integers to generate a third integer; accumulator means for storing the third integer; overflow means for storing an overflow integer;
means for fetching the feedback number into the register of and adding the feedback number to the third integer of the accumulator means, and means for converting it into a remainder of the third integer modulo a fourth integer p, It is possible to realize a processor chip that can perform addition, multiplication, and exponent calculation regarding a Galois field consisting of remainders of integers to prime numbers at high speed.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

A preferred embodiment of the invention provides an X register with L bits of memory for storing an N-bit integer It includes first and second A registers for storing bits. The present invention converts an N-bit integer X stored in an X register into first and second separate integers each having L bits, and converts the first and second separate integers into and means for storing in the second register A. The invention also includes control means connected to the first and second registers for generating control signals.

first and second B registers for storing L bits, respectively; and first and second B registers for storing L bits, respectively.
The C register of is connected to the full adder. The control logic circuit is also connected to a full adder, and the full adder inputs the data stored in the first and 20B registers in response to a "1" bit control signal output from the control logic circuit. After moving the digit to the left, it is added to the data stored in the first and second C registers. The full adder shifts the data in the first and second B registers to the left in response to a "0" bit control logic signal.

A feedback register having L bits of memory for storing an N-bit feedback number is included along with means for generating a feedback number from an N-bit prime number p and storing said feedback number in said feedback register. modulus means are connected to the feedback register and the first and second C registers and convert into a remainder of the data bits stored in the first and second C registers modulo a prime number p; This is means for converting the data bits stored in the 1 and second C registers into L-bit integers and then storing the L-bit integers in the X register.

The processor chip of the present invention performs addition, multiplication, and exponent calculation regarding the Galois field GF (p) consisting of the remainder of an integer modulo a prime number p. For large prime numbers, (several chips can be cascaded together to function as one larger chip with operational equivalents. They can also be connected modulo the composite number.) It can be used to perform index calculations on a ring consisting of remainders of integers. Here, the factorization of this composite number is kept secret, for example in R3A public key cryptography. In the following discussion, focuses on the Galois field GF(p), where p is a prime number.

The prime number p is an n-bit number expressed using a base 2 representation (usually a binary representation) as shown in the following equation.

p=P[n-1+B2[n-3+P[n-2]2m-!
+...10P[1]2. +PC 0] Here, +P[il) is a binary symbol.

Furthermore, it is convenient to use two's complement representation for p as shown in the following equation.

p=2°-F[n-1]2°-'-F[n-2]2°
-1-...F[ll2-F[Ol Here, (F[ill is a binary symbol.

Since p is equivalent to O in the Galois field GF (p), the following equation is obtained.

2n mod p=F[n-1]2m-3+F[n-
2+B2[n-”+...10F[1]2+F[Ol
...(1) Therefore, 2m is bit (F[il)
is equivalent to an n-bit binary number expressed in base-2 representation with . This fact is widely used to convert all integers into their representation in nbyy, where (F[il
) are called "feedback bits".

Next, the exponent calculation of the Galois field GF (p) will be explained. When X is an element of the Galois field GF (p), the m-bit integer Z is expressed by the following equation.

Z = Z [m -1]2n-3+ Z [m -2
]2--"+...+ZEIko2+Z[Ol Furthermore, an element of any Galois field GF (p) such as X is also expressed by the following equation.

X=X[n-1+B2[n-3+X[n-2+B2[n
−”, +...+X[1]2+X[0]Here, tZc
i]) and 毫X[iKO) are binary symbols. Next, calculation of the following equation will be explained.

Y=X'' modp Here, Y is of course an element of the Galois field GF (p). The basic operation of exponent calculation for this processor chip is obtained by the following equation.

xz:xZ[0]+22[1]+2nZ[21”2n-
'Zcm-1]=XZ[0](x2)Z[1](x2n
) Z[2]1,, (x2--') Z[m-,1]=
xZ[0] (xZ[1] (X2)Z[2]1,,(
X2np Z[m-1]) t= x'Z[o] (x
Z[1] (XZ[2]1,, (x2n-3)Z[+
a-1])! + 1 Here, it is defined as in the following formula.

E , , :XZ[m-niko(x2)Z[ll1-k
"ll1,, (X2n-3)Z[m-1]k=1.2
．． ...2m Next, the formula for the index calculation algorithm is set as shown in the following formula.

E, = Xz [m-t] E 4 = xZ [m-k] E, -1 = 2.2, F
3, ...2m Here, XZ=E.

and Y=Emmodp The index calculation comprises a series of multiplications of the remainder modulo the prime p. For any two integers A and B, AB sod
p = (A mod p) (B nod p) mod
p Therefore, it is not necessary to convert the multiproduct of integer remainders modulo the prime number p until all product operations forming the exponent calculation are completed. Furthermore, some transformations at each stage can be performed using the relationship in equation (1). This partial conversion allows all integers to be represented by n binary symbols.

Multiplication Algorithm The heart of the processor chip is the Galois field GF (p) multiplication operation. Two n belonging to Galois field GF (p)
Consider bit integers A and B.

These are any two integers smaller than the prime number p. Consider the required multiplication operation of the following equation.

C=AB mod p A, B, and C are called the 7 power, the multiplicand, and the product, respectively.

A. Another Representation As mentioned above, the element A in the Galois field GF (p) can be uniquely represented by n binary symbols IA[i]) as shown in the following equation.

A=A[n-1]2n-3+A[n-2]2n-"+・
...+A[1]2+A[0] To avoid carry propagation, for example when two n-bit integers are added, consider another non-unique representation of the following equation.

A = A, + A t 2 = A1[n-1]2n-3+A1[n2]2n-"
10...+A1[1]2+A1[1] 2+P[0]+A2[n-3]2n-3+...+B2
[1]2+B2[n132°+A2[n-3]2n-3
+...+B2[1]2+B2[n 2. ]2n-3
+...+A1[1]2n+A1[1]2+P[0]2
Here, IA1[i] l and {A, [+]) are binary symbols. In this representation, there are many sets of n bits representing the same integer.A.

and the i-th component A1[i and A2[n-3] of At.
2n-3+...+B2[1]2+B2[j] defines the i-th integer component of the following equation.

A [i] −A1[i] +A1[i] 2This i-th integer component is 0. 1. 2. or a 2-bit integer with a value of 3. B and C are represented by the same expression. Here, B is expressed by the following formula.

13 = B I+ B t 2 = B1[n 1] 2n-3+B1[n 2] 2n-
”+...10 B 1[112+ B 1[1]2+P[
0]+B2[n-3]2n-3+...+B2[1]2
+B2[n 1]2°+B2[n-3]2n-3+・
・・+B2[1]2+B2[n 2]2n-3+・・
・10B1[1]2n+B1[0] 2B1[i] and B
The i-th component of B and Bt given by 1[i is
Form the i-th integer component of B as shown in the following equation.

B[i = B+ [i] +Bt [i] 2 The i-th integer component of B is also a 2-bit integer having a value less than or equal to 3.

In this unambiguous representation, the integers A, B, and C are represented by n 2-bit integer components.

Since the above alternative representations for A, B, and C are not unambiguous, there is some freedom to choose the representation that is easy to implement. The specific format is described below assuming there are two n-bit registers for the multiplier A1, the multiplicand B1, and the product C.

89 Multiplier The "digit shifted and added" multiplier is stored in two n-bit registers "Multiplier" A = A I
+ A t 2, ``After the multiplier A is shifted a digit to the right (the higher order bits are on the left)''
The bits of the “sum” are output to the control logic circuit that calculates the “sum” and “carry”.
= B r + B * 2 integer as C=C, +C,
It is used to control the addition to the accumulator of the "product" given by 2. The control logic for the multiplication is at the right end of the n-bit registers of A and A. The binary variables r2, rt, and At+ are initially set to zero. This logic circuit calculates the following integer:

△ r = r z + At++ As [0] and A
tlS A1 [0] △ Here, r is r=r in base 2 representation as shown in the following formula.
l+r*2 Data of multiplier registers A1 and A are respectively set to the right Δ.

The multiplication logic located at the right end of the A, register and the A, register simply converts to an ununique n-bit radix-2 representation. Here, the bit (r,) of the operation result is the shifted multiplicand register B
, and B to the product accumulator registers C0 and C3.

C1 multiplicand n-bit registers B and B with two multiplicands;

is stored and shifted a digit to the left (multiplied by 2). Before moving the data in the registers B and B, respectively, one digit to the left, the bits in these registers are output from the multiplication logic circuit.

△ Product accumulator registers C1 and C depending on trl
8 or not.

The multiplicand B is expressed by the following formula.

i=0 Moreover, the multiplicand B is expressed by the following equation having the converted term.

i=0 Furthermore, by multiplying both sides of the above equation by 2, the following equation is obtained.

i;1 + (2B 2[n-3]2n-3+...+B2[1
]2+B2[n-1]+B 1[nt]+B2
[n-3]2n-3+...+B2[1]2+B2[n
-2]) 2'' Using the fact that each 2m term can be replaced by a feedback term using equation (1), the number of 2n terms above is given by the following equation, 5=2B2[n -3]2n-3+...+B2[1]2
+B2[n 1]+81[n 1]+B2[n-3
]2n-3+...+B2[1]2+B2[n 2]
The feedback n-bit sequence is given by:

F n= 32 ″mod p The four possible non-O feedback terms are defined as F1, F1, F, and F4. Now, the shift operation of the integer B is given by the following equation.

Initial state: Load B and set the following formula.

5=2B2[n-3]2n-3+...+B2[1]2
+B2[n-1]+B1[n-1]+B1[n-2] Perform digit shift calculation according to the following equation.

i=1 △ △ △ △S −
2B 2[n-3]2n-3+...+B2[1]2+
B2[n-1]+B1[:n-1]+B2[n
-3]2n-3+...+B2[1]2+B2[n-1
]△Here, B is the integer of the first register, and B=2
B is the integer of the shifted register.

FIG. 1 shows this digit shift operation using a full adder.

At any given time, B is given by the following equation.

i:0 If r+=1, B is added to an integer C consisting of two n-bit registers.

Problems dealing with overflow terms are handled using equation (1). Since no shifting of the data in the C register is involved, all overflow terms accumulate until all shifting and addition operations are completed. At the end of the shift and add operation, all accumulated overflow terms are added to the C register to obtain the final answer.

Assuming Δr+=1, each addition operation for adding B to C is shown in FIG. 2 for each of the two sets of full adders. After all digit moves and additions have been completed, the counter contains the integer I and the final product ABmodp is obtained by adding 12r' to the integer C contained in the two n-bit registers. This restarts the digit movement and addition operation using A and F replaced by ■, B replaced by F, and starts using the current value of the C register.
This can be done by replacing m with Ft=2mm mod p and adding IF to the accumulator register. Again, the operations shown in FIG. 2 are used. This operation is repeated until the cycle of digit movement and addition is completed and I=O.

If the initial integers A and B each consist of n bits, then any digit shift in B causes a term smaller than two 2m terms to enter C fewer than n times. will be added. Therefore, the counter is 2
Count the integer I that is not thicker than n. If n = 5ooo, a 14-bit counter is required. Therefore,
The count value I of the counter has a maximum integer of 14 bits,
The shift and add cycle associated with the operation of adding IF to the accumulator is short compared to the initial shift and add cycle.

Product Conversion When the multiplication operation is finished, two n-bit registers CI and C are used to continue the exponent calculation algorithm.
Transfer the data stored in 1 to two n-bit registers AX, A1, and/or B I{B. When the exponent calculation algorithm is completed, the integer C stored in the two n-bit registers is converted into one 2 of the following formula.
It is desirable to convert to a base number representation.

Here, C2[i] = 0 for all i=O, 1, . . . , n-1.

In two n-bit representations, the integer C satisfies the following equation.

C=C1[n-1+B2[n-1+c2[n-3]2n
-3+...+B2[1]2+B2[n-2+B2[n
1+1,, +C1[0]+ 1]2n-2] 2n-'
+ C1[n-3] 2 ”-' 10...+ Ct
[-1]<2-1 where C2[-tconi, 0 and 1]2n-1]=O. 2″+2=
2 "', so C in the normal n-bit representation
, the term 2r'' of 1gA is the maximum.
The conversion to n-bit representation is given by:

Step 1: Set N4-n Step + 1 4-0 Step 2: Set C4-C+O N 4-N-1 Step 3: Check N=0 If N=O, proceed to step 4.

If N≠0, proceed to step 2.

Step Knob 4: Check z 7 Counter I If I=0, stop.

If ■≠0, set C4-C+F.

After that, proceed to step 1.

The above calculation operations are performed by examining FIG. 2 with B=0. Starting from the lowest order bit, the first (C+Q) operation yields C2[0] =
Find C2[11
Find =O. The same applies hereafter.

Modulo p conversion The representation of one n bit of C is expressed by the following equation.

Assuming that the most significant bit of the prime number p is 1, we obtain the following equation.

i=0 Here, P[n-1]=1. This is not a limiting condition. This is because n exists by defining the number of bits required to represent the prime number p. Therefore, p≧2m1 or 2p≧2m and c<2p.

If the representation of C is greater than the prime number p, i.e. ap , then by performing the following steps, C
It is desirable to convert C-p to C-p.

Step 1: Set Y4-C Step 2: Set C4-C+F.

Step 3: Set N+O 1←　0 Step '4 = Set C4-C+O N 4-N-1 Step 5: Check N=0 If N=O, proceed to step 6.

If N≠0, proceed to step 4.

Step 6: Check counter I If I=O, stop.

If ■≠0, stop after set Y4-C.

To show that the above procedure is correct, the final answer must be an n-bit representation satisfying , one n-bit representation is C-p that satisfies the following equation.

0≦C−p<p Here, since p=2n F+, C+ F1=2 n+(Cp). If ■≠0 after converting C+F into one n-bit representation, then C−
If p≧0 or C≧p, the last data of the C register is accepted as the answer. If not, ie, if I=Q, then the data value of the first C register (after the addition of F,) is the desired answer.

Processor chip The following equation shows the general characteristics of a Galois field GF (p) processor chip that performs calculations.

Y=X2 mod p Y=XZ nod I) and Y=X+Z mod p A, basic structure This processor chip has 12 pinto registers and L full adders, as shown in FIG. It has a basic structure with control and feedback logic. Prime feedback term F
3 and F4 are calculated from the input F1, while F is obtained simply by shifting Fl. The inputs to this chip are the integers X and Z. It is assumed that all these integers are represented in n bits and the prime number p is an n-bit integer. The final exponent calculation will be performed in the n-bit register Y. At any time after loading the F1, Z, and X registers, a start command can initialize addition, multiplication, or exponentiation. Loading these registers is not allowed during calculations.

Since the index calculation consists of a series of multiplication operations C=AB, the basic structure in Figure 3 is mainly based on the Galois field GF.
(p) multiplier. When the last answer is obtained in the n-bit register CI, the last answer is loaded into the Y register.

Only the last answer above can be read from the Y register after all calculations have been performed.

Most of the above basic structure consists of a set of 12 n-bit registers and L full adders.

A longitudinal section of this foundation structure is shown as a foundation cell in FIG. Most of the infrastructure of FIG. 3 includes identical copies of the foundation cells shown in FIG. 4 cascaded L times, such as a set of register cells.

The basic cell is composed of 12 registers and one full adder that operates in a time-division manner to perform the operations shown in FIGS. 1 and 2. In FIG. 4, load lines and communication lines are shown, where the base cell receives input from the two adjacent cells on the right and the outgoing cell receives input from the two adjacent cells on the left. 3 feedback pings)S.

+SL+ss exists.

B. Mismatch So far, a processor chip includes L basic cells. Therefore, all integers of interest are n-bit integers. The prime number p was also assumed to be an n-bit prime integer.

Now, when a prime number is represented by n bits, it is considered that the processor chip has L basic cells. Here, n≦, and Z is expressed by m bits.

A chip structure of L basic cells can be used to perform the desired index calculations.

When an n-bit prime number, the integer X is an n-bit integer, and the results of addition, multiplication, and exponent calculation are n-bit integers. To allow for a mismatch between L and n, the n-bit integers X and F are loaded into the most significant n-bit register locations of the X and F registers. The data in the most significant m bit positions of the Z register is loaded into the integer Z of m pintos. This is illustrated in FIG. Essentially, only the top n cells of the L cell chips are used. The only modification required here is as follows. That is, at the beginning of each multiplication, the data in the A1 and A registers are shifted to the right by q=L=n steps so that the rightmost logic circuits are accurately synchronized.

C. Modular Chips For large prime numbers, it is impractical to put all the basic cells on one chip. Therefore, a so-called modular design is used, in which L basic cells are mounted on one chip. Therefore, one chip can perform exponent calculation for any n-bit prime number p when n≦.

In a modular chip design, two cascaded chips behave like one chip with 2L basic cells and can handle prime numbers when n≦2L. In this modular design, n≦K
When L and p is an n-bit prime number, the cascaded modular chips form a Galois field GF.
It operates like a single chip consisting of KL basic cells capable of performing index calculations on (p).

To implement this modular design, consider the structure of FIG. 3, which shows a modular chip. In this modular chip, the logic circuit at the left end is disabled by a signal on an input control pin, and the logic circuit at the right end is disabled by a signal at another input control pin.

Input and output pins are located on each chip to connect the two chips together so that the series of basic cells continues from one chip to the next. Therefore, every chip has L base cells and all edge logic circuits, as shown in FIG. As a first variant, the logic circuit at the end can be rendered inactive and the chips can be connected in a continuous cascade of basic cells.

The cascaded modular chips then have the left-most chip with the left-hand logic circuitry activated and the right-hand logic circuitry deactivated. The (K-2) middle chips have all the edge logic circuitry inactive, while the leftmost chip has the left logic circuitry inactive and active. It has a logic circuit on the right side that is assumed to be . Since the edge logic occupies only a small area on each modular chip, the overall wasted chip area is very small for unused edge logic. 1st
In addition to the above edge logic shown in the figure, the chip-wide controller is also replicated on each chip, although it is only used on the left-most chip in the cascaded modular chips. There is a whole-chip controller. This chip controller occupies almost no chip area, as will be described later.

It is assumed that there are 2 modular chips connected in cascade to form the chip controller KL basic cells. Bi in the representation of n as a prime number p.

If the number of bits is 1=0, the relevant control parameters are n, m, and q, where n=number of bits representing p, m=number of bits representing z, and q=KL−n. .

When these parameters are entered into the control register,
Before each calculation, n-bit inputs X and Fl and m-bit input Z are input.

A. Basic subroutine In the flowchart below, multiplication is expressed as follows.

P.Y. The overflow compensation is expressed as follows.

OVF Compensation Also, the conversion from two n bits to one n bit is expressed as follows.

2→1 Conversion These three subroutines are shown in FIGS. 6, 7, and 8, respectively. The counters in FIG. 2 have an integer count indicated by a square symbol, which is the overflow index used in these subroutines. Multiplication is the most common subroutine used in index calculations. Overflow compensation is used to check the 2m terms in the counter, as shown in Figure 2, and if an overflow has occurred, then (
1) Add a feedback term using equation. 1 from 2 n bits
The conversion to n bits is performed by adding O to C n times.

B. Calculation of feedback term As mentioned above, the feedback term is given by:

F3=S2mmodl) or i=0 i=1 F3=F,+F, mod p and F4=F3+F+ll1od pSince the prime number has the most significant order bit P[n-1] =1,
Obtain F[n-1]=O. Therefore, F can be obtained by a simple cursor movement with respect to Fl. Because it does not result in a number with 2m terms. However, F and F4 may not require conversion to a remainder modulo the prime p. Simply Fl
+F3+ and F4 are respectively stored in registers. F
3 and F4 are calculated using the flow shown in FIG.

C. Overflow Control Program An overall control flowchart using the above-mentioned subroutines is shown in FIG. This overall control flowchart consists of three independent functions: exponential calculation, multiplication, and addition.
It suffers from the common parts that follow. This common part first stores the answers in the CI and C1 registers as C
After converting to one n-bit representation in 1, a final mod p conversion is performed.

It will be apparent to those skilled in the art that various transformations can be made to the Galois field processor chip of the present invention without departing from the scope and concept of the invention. It is also intended that the invention cover other embodiments and variations of Galois field processor chips as provided by the following claims and their equivalents. Furthermore, the present invention provides an IC for encryption and message authentication.
It is intended to encompass current and new applications of Galois field processors, including card public key management schemes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the digit movement operation of the processor chip according to the invention. FIG. 2 is a block diagram showing the accumulator operation of the processor according to the invention. FIG. 3 is a block diagram showing the basic structure of the processor chip according to the invention. , FIG. 4 is a circuit diagram showing the basic cell of the processor chip of the present invention, FIG. 5 is a block diagram showing the configuration of the register of the present invention, FIG. 6 is a flowchart of the multiplication subroutine of the present invention, and FIG. 7 is a diagram showing the structure of the register of the present invention. FIG. 8 is a flowchart of an overflow compensation subroutine of the present invention; FIG. 8 is a flowchart of a subroutine for converting two N bits into one N bit; FIG.
and a flowchart showing the settings of F4. FIG. 10 is an overall flowchart showing the processor chip of the present invention. A1, A1, B1, B! + C,,C,,X,Y,Z
. F1, F2, F3, F, ... register, p ... prime number, GF (p) ... Galois field. 1st

Claims (1)

[Claims] (1) An X register having L bits for storing an n-bit integer X, and a Y register having L bits for storing an n-bit integer Y.
a register, first and second A registers each having L bits, converting an n-bit integer means for storing another integer in said first and second A registers; and control means connected to said first and second A registers for generating a control signal, each storing L bits. first and second B registers for storing L bits, respectively; first and second B registers and first and second C registers for storing L bits, respectively; The data stored in the first and second B registers are shifted to the left in response to a control signal of a "1" bit connected to the control means.
Adds to the data stored in the register and adds “0” to the data stored in the register.
a full adder for shifting the data stored in the first and second B registers to the left in response to a control signal of the `` bit; and an L bit for storing an n-bit feedback number; means for generating a feedback number from an n-bit integer p and storing the feedback number in the feedback register; and a modulo means for converting the data bits stored in the first and second C registers to a remainder modulo an integer p, and the data bits stored in the first and second C registers to an L-bit integer. Convert the above L-bit integer to the above Y
and means for storing in a register. (2) An X register with L bits to store an n-bit integer X, and a Y register with L bits to store an n-bit integer Y.
a register, first and second A registers each having L bits, converting an n-bit integer means for storing another integer in said first and second registers A; and control means connected to said first and second A registers for generating a control signal, each storing L bits. first and second B registers for storing L bits, respectively; first and second B registers and first and second C registers for storing L bits, respectively; In response to a "1" bit control signal connected to the control means, the data stored in the first and second B registers are added to the data stored in the first and second C registers, respectively. a full adder for converting the data bits stored in the first and second C registers into an L-bit integer, and converting the L-bit integer into the Y-bit integer.
and means for storing in a register. (3) The device further comprises an L-bit feedback register for storing an n-bit feedback number, and means for generating a feedback number from an n-bit integer p and storing the feedback number in the feedback register. , connected to the feedback register and the first and second C registers;
3. Apparatus as claimed in claim 2, further comprising modulo means for converting the data bits stored in the C register of the register into a remainder modulo an integer p. (4) The device further comprises means for performing index calculation on a ring consisting of remainders of integers modulo an integer p from a series of multiplications of remainders modulo an integer p according to the following formula: An apparatus for performing multiplication on a ring consisting of remainders of integers modulo an integer p according to claim 1. X^Z=X^Z^[^0^](X^Z^[^1^]{X
^^Z^[^2^]...(X^2^^m^^-^^3)
^Z^ [^m^-^1^]}^2}^2 (5) The above device further includes an overflow counter connected to the full adder and for counting the overflow value I output from the counter. and wherein the full adder adds I2^n to the first and second C registers by replacing 2^n with the feedback number F_1 and then adding IF_1 to an accumulator register. The device according to item 1. (6) The device further includes an overflow counter connected to the full adder for counting an overflow value I output from the full adder, and the full adder calculates 2^n by the feedback number F_1. 3. Apparatus according to claim 2, characterized in that I2^n is added to said first and second C registers by adding IF_1 to an accumulator register after replacement. (7) The device further includes an overflow counter connected to the full adder for counting an overflow value I output from the full adder, and the full adder calculates 2^n by the feedback number F_1. 4. The apparatus of claim 3, wherein I2^n is added to said first and second C registers by adding IF_1 to an accumulator register after replacement. (8) A modulo arithmetic processor chip for adding an n-bit first integer A to an n-bit second integer B, wherein the second integer B is added to the first integer A. The remainder modulo the n-bit fourth integer p regarding the added data is the third
is equal to the integer C, and the above first integer A is A=A[n-1]2^n^-^1+A[n-2]2^n
^-^2+A[n-3]2^n^-^3+...+A[
1]2+A[0] It is represented by the binary number {A[i]} in the representation,
The above second integer B is B=B[n-1]2^n^-^1+B[n-2]2^n
^-^2+B[n-3]2^n^-^3+...+B[
1]2+B[0] Represented by the binary number {B[i]} in the representation,
The third integer C above is C=C[n-1]2^n^-^1+C[n-2]2^n
^-^2+C[n-3]2^n^-^3+...+C[
1]2+C[0] Represented by the binary number {C[i]} in the representation,
The above fourth integer p is p=P[n-1]2^n^-^1+P[n-2]2^n
^-^2+P[n-3]2^n^-^3+...+P[
1]2+P[0] It is represented by the binary number {P[i]} in the representation,
Thereby, C=(A+B) mod p, and the modulo arithmetic processor chip has a first register means for storing the first integer A and a second register means for storing the second integer B. 2 register means, and feedback means for generating and storing a feedback number F, said feedback number F being the two's complement of said fourth integer p, whereby F=2^n-p. and an arithmetic means connected to the first register means and the second register means for generating a third integer C by adding the first integer A to the second integer B; , an accumulator means connected to the arithmetic means and for storing the third integer C, an overflow means connected to the accumulator means and for storing an overflow integer, and the overflow means and the second register means. is connected to, in response to the overflow integer, fetches the feedback number F into the second register B, and uses the arithmetic means to add the feedback number F to the third integer C stored in the accumulator means. means connected to the accumulator means for converting the third integer C modulo the fourth integer p into a remainder of the third integer C modulo the fourth integer p in response to the third integer C being greater than the fourth integer p; A modulo arithmetic processor chip comprising means for and. (9) The calculation means includes the first register and the second register.
9. The modulo arithmetic processor chip according to claim 8, further comprising a plurality of full adders connected to the register for adding the first integer A to the second integer B. (10) The calculation means includes a plurality of half adders connected to the first register means and the second register means for adding the first integer A to the second integer B. The modulo arithmetic processor chip according to claim 8, characterized in that: (11) A modulo arithmetic processor chip for adding an n-bit first integer A to an n-bit second integer B, the data obtained by adding the second integer B to the first integer A. The remainder of the n-bit fourth integer p modulo is equal to the n-bit third integer C, and the base bit of the first integer A is A_1=A_1[n-1]2^n^- ^1+A_1[n
-2]2^n^-^2+A_1[n-3]2^n^-^
It is represented by a binary number {A_1[i]} in the representation of 3+...+A_1[1]2+A_1[0], and the carry bit of the first integer A is A_2=A_2[
n-1]2^n^-^1+A_2[n-2]2^n^-
^2+A_2[n-3]2^n^-^3+...+A_
It is represented by a binary number {A_2[i]} in the representation of 2[1]2+A_2[0], and the radix bit of the second integer B is B_1=B_1[n-1]2^n^-^
1+B_1[n-2]2^n^-^2+B_1[n-3
]2^n^-^3+...+B_1[1]2+B_1[
0], and the carry bit of the second integer B is B_
2=B_2[n-1]2^n^-^1+B_2[n-2
]2^n^-^2+B_2[n-3]2^n^-^3+
...+B_2[1]2+B_2[0], represented by the binary number {B_2[i]}, and the radix bit of the third integer C is C_1=C_1[n-1]
2^n^-^1+C_1[n-2]2^n^-^2+C
_1[n-3]2^n^-^3+...+C_1[1]
Binary number in the representation consisting of 2+C_1[0] {C_1
[i]}, and the carry bit of the third integer C is C_2=C_2[n-1]2^n^-^1+
C_2[n-2]2^n^-^2+C_2[n-3]2
^n^-^3+...+C_2[1]2+C_2[0]
It is represented by a binary number {C_2[i]} in the representation, and the fourth integer p is expressed as p=P[n-1]2^n^-^1+P[n-2]2^n
^-^2+P[n-3]2^n^-^3+...+P[
1] Binary number in the representation consisting of 2+P[0] {P[i
]}, thereby C=(A+B)mo
d p, and the modulo arithmetic processor chip is
first radix register means for storing a radix bit of said first integer A; first carry register means for storing a carry bit of said first integer A; and said second integer B. second radix register means for storing the radix bit of the second integer B; second carry register means for storing the carry bit of the second integer B; a first feedback number F_1, a second feedback number F_2, feedback means for generating a third feedback number F_3 and a fourth feedback number F_4, wherein the first feedback number F_1 is a two's complement of the fourth integer p, whereby F_1 =2^n-
p, and the second feedback number F_2 is equal to twice the first feedback number F_1, so that F_2=2F_1
mod p, and the third feedback number F_3 is equal to three times the first feedback number F_1, so that F_3
=3F_1 mod p, and the fourth feedback number F_
4 is four times said first feedback number F_1, thereby F_4=4F_1 mod p, said first radix register means, said first carry register means, said second radix register means and said a plurality of full adders connected to a second carry register means; using the plurality of full adders to generate a first sum having a radix bit and a carry bit; after simultaneously adding the radix bit and carry bit of the second integer B to each radix bit of the second integer B, using the plurality of full adders to generate the radix bit and carry bit of the third integer C, respectively. arithmetic means for adding the radix bit and carry bit of the first sum to each carry bit of the second integer B, and a means connected to the arithmetic means for storing the radix bit of the third integer C; an accumulator radix means for counting overflow bits, an accumulator carry means connected to the arithmetic means for storing a carry bit of the third integer C; overflow means connected to said overflow means, said second radix register means and said feedback means for storing said overflow integer I=I;
After fetching the feedback number F_1, F_2, F_3, or F_4 outputted from the feedback means in response to 1, 2, 3, or 4 into the second radix register means, the feedback number F_1, F_2, F_3, or F_4 output from the feedback means in response to number F_1, F_2, F_3, or F
_4 to the third integer C stored in the accumulator base means and the accumulator carry means, respectively.
means for adding to said third integer C modulo said fourth integer p connected to said accumulator base means and responsive to a third integer C greater than said fourth integer p; A modulo arithmetic processor chip, comprising: means for converting into a remainder. (12) A modulo arithmetic processor chip for adding an n-bit first integer to an n-bit second integer B, which relates to data obtained by adding the second integer B to the first integer A. The remainder modulo the n-bit fourth integer p is equal to the n-bit third integer C, and the base bit of the first integer A is A_1=A,_1[n-1]2^n^ -^1+A_1[
n-2] 2^n^-^2+A_1[n-3]2^n^-
It is represented by a binary number {A_1[i]} in the representation of ^3+...+A_1[1]2+A_1[0],
The carry bit of the first integer A is A_2=A_2
[n-1]2^n^-^1+A_2[n-2]2^n^
-^2+A_2[n-3]2^n^-^3+...+A
It is represented by the binary number {A_2[i]} in the representation consisting of _2[1]2+A_2[0], and the second integer B is
The radix bit of B_1=B_1[n-1]2^n^-
^1+B_1[n-2]2^n^-^2+B_1[n-
3] 2^n^-^3+...+B_1[1]2+B_1
It is represented by the binary number {B_1[i]} in the representation of [0], and the carry bit of the second integer B is
B_2=B_2[n-1]2^n^-^1+B_2[n
-2]2^n^-^2+B_2[n-3]2^n^-^
It is represented by a binary number {B_2[i]} in the representation consisting of 3+...+B_2[1]2+B_2[0], and the radix bit of the third integer C is C_1=C_1[n-
1] 2^n^-^1+C_1[n-2]2^n^-^2
+C_1[n-3]2^n^-^3+...+C_1[
1] Binary number in the representation consisting of 2+C_1[0] {C
_1[i]}, and the carry bit of the third integer C is C_2=C_2[n-1]2^n^-^
1+C_2[n-2]2^n^-^2+C_2[n-3
]2^n^-^3+...+C_2[1]2+C_2[
0], and the fourth integer p is expressed as p=P[n-1]2^n^-^1+P[n-2]2^n
^-^2+P[n-3]2^n^-^3+...+P[
1] Binary number in the representation consisting of 2+P[0] {P[i
]}, thereby C=(A+B)mo
d p, and the modulo arithmetic processor chip is
first radix register means for storing a radix bit of said first integer A; first carry register means for storing a carry bit of said first integer A; and said second integer B. second radix register means for storing a radix bit of said second integer B; second carry register means for storing a carry bit of said second integer B; and feedback means for generating a feedback number F. , where the feedback number F is the two's complement of the fourth integer p,
As a result, F=2^n-p, which is connected to the first radix register means, the first carry register means, the second radix register means, and the second carry register means, and is connected to the radix bit and the carry register means. the first with bits
After simultaneously adding the radix bit and carry bit of the first integer A to each radix bit of the second integer B to generate the sum of , the radix bit and carry bit of the third integer C are generated. arithmetic means for adding the radix bit and carry bit of the first sum to each carry bit of the second integer B, respectively, and a radix bit of the third integer C connected to the arithmetic means; accumulator radix means for storing a carry bit of the third integer C; accumulator carry means connected to the arithmetic means for storing a carry bit of the third integer C; overflow means for counting and storing as an overflow integer I; and an overflow means connected to the overflow means, the second radix means and the feedback means for fetching a feedback number F output from the feedback means in response to the overflow integer. After that,
means for adding the feedback number F to the third integer C; A modulo arithmetic processor chip characterized by comprising means for converting into a remainder of a third integer C modulo C. (13) The calculation means is connected to the first radix register means, the first carry register means, the second radix register means, and the second carry register means and has a radix bit and a carry bit. After simultaneously adding the radix bit and carry bit of said first integer A to each radix bit of said second integer B to generate a sum of 1, the radix bit and carry bit of said first sum are 13. The modulo arithmetic processor chip of claim 12, further comprising a plurality of full adders for storing in the radix accumulator means and said carry accumulator means, respectively. (14) The modulo arithmetic processor chip further includes the plurality of full adders, the first radix register means, the first carry register means, the second radix register means, and the second carry register means. said radix accumulator means and said carry accumulator means, said radix and carry bits of a first sum stored in said radix accumulator means and said carry accumulator means for generating said third integer C simultaneously. after adding to the carry bit of the second integer B, switching the plurality of full adders to store the radix bit and the carry bit of the third integer C in the radix accumulator means and the carry accumulator means, respectively; 14. The modulo arithmetic processor chip of claim 13, further comprising multiplexer means. (15) A modulo arithmetic processor chip for multiplying an n-bit first integer by an n-bit second integer B, the data of the multiplication result of the first integer A and the second integer B. The remainder modulo the n-bit fourth integer p is n
equal to the third integer C of bits, and the first integer A above is A=A[n-1]2^n^-^1+A[n-2]2^n
^-^2+A[n-3]2^n^-^3+...+A[
1] Binary number in the representation consisting of 2+A[0] {A[i
]}, and the second integer B is expressed as B=B[n-1]2^n^-^1+B[n-2]2^n
^-^2+B[n-3]2^n^-^3+...+B[
1] Binary number in the representation consisting of 2+B[0] {B[i
]}, and the third integer C is expressed as C=C[n-1]2^n^-^1+C[n-2]2^n
^-^2+C[n-3]2^n^-^3+...+C[
1] Binary number in the representation consisting of 2+C[0] {C[i
]}, and the fourth integer p is expressed as p=P[n-1]2^n^-^1+P[n-2]2^n
^-^2+P[n-3]2^n^-^3+...+P[
1] Binary number in the representation consisting of 2+P[0] {P[i
]}, thereby C=A・B mod
p, and the modulo arithmetic processor chip has a first register means for storing the first integer A, a second register for storing the second integer B, and a feedback number F. feedback means for generating a feedback number F, wherein said feedback number F is the two's complement of a fourth integer p, such that F=2^n-p, and is connected to said second register means. said feedback number F in response to the most significant of said second integer B being shifted to the left from said second register means;
a first partial conversion means for adding to said second integer B and thereby converting a portion of said second integer B; and connected to said first register means and said second register means; arithmetic means for adding the second integer B to the third integer C in response to the lowest digit of the first integer A that has been shifted to the right from the first register means; accumulator means connected to the means for storing said third integer C; overflow means connected to said accumulator means for counting and storing overflow bits as an overflow integer I; said first register means and said a second register means, the overflow means and the arithmetic means; the overflow integer I is connected to the first register means in response to the completion of the multiplication of the first integer A and the second integer B; transfer said feedback number F to said second register means, multiply said feedback number F by an overflow integer I to generate a product, and said product is transferred to said third register means stored in said accumulator means. second partial conversion means for adding to an integer C; and second partial conversion means connected to said accumulator means and responsive to said third integer C being greater than said fourth integer p to modulo said fourth integer p. and means for converting the third integer C into a remainder. (16) A modulo arithmetic processor chip for multiplying an n-bit first integer A by an n-bit second integer B, the chip comprising: a multiplication result of the first integer A and the second integer B; The remainder modulo the n-bit fourth integer p regarding the data is n
equal to the third integer C of bits, and the first integer A above is A=A[n-1]2^n^-^1+A[n-2]2^n
^-^2+A[n-3]2^n^-^3+...+A[
1] Binary number in the representation consisting of 2+A[0] {A[i
]}, and the second integer B is expressed as B=B[n-1]2^n^-^1+B[n-2]2^n
^-^2+B[n-3]2^n^-^3+...+B[
1] Binary number in the representation consisting of 2+B[0] {B[i
]}, and the third integer C is expressed as C=C[n-1]2^n^-^1+C[n-2]2^n
^-^2+C[n-3]2^n^-^3+...+C[
1] Binary number in the representation consisting of 2+C[0] {C[i
]}, and the fourth integer p is expressed as p=P[n-1]2^n^-^1+P[n-2]2^n
^-^2+P[n-3]2^n^-^3+...+P[
1] Binary number in the representation consisting of 2+P[0] {P[i
]}, thereby C=A・B mod
p, and the modulo arithmetic processor chip has a first register means for storing the first integer A, a second register for storing the second integer B, and a feedback number F. feedback means for generating, wherein said feedback number F is the two's complement of a fourth integer p, such that F=2^n-p; 2 register means for adding said second integer B to said third integer C in response to the lowest order of said first integer A being shifted to the right from said first register means; arithmetic means connected to the arithmetic means and for storing the third integer C; overflow means connected to the accumulator means for counting and storing overflow bits as an overflow integer; means connected to said feedback means, said first register means, and said second register means for transmitting said overflow integer I to said first integer I in response to the completion of the multiplication of said first integer A and said second integer B; transferring said feedback number F to said second register means, multiplying said feedback number F by said overflow integer I to generate a product, and said product being stored in said accumulator means. a second partial conversion means for adding to a third integer C; and a second partial conversion means connected to the accumulator means to modulate the fourth integer p in response to a third integer C greater than the fourth integer p. a modulo arithmetic processor chip, comprising means for converting the third integer C into a remainder. (17) Claim characterized in that the arithmetic means includes a plurality of full adders connected to the second register means for simultaneously adding the second integer B to the third integer C. 17. The modulo arithmetic processor chip according to item 16. (18) Claim characterized in that the arithmetic means includes a plurality of half adders connected to the second register means for simultaneously adding the second integer B to the third integer C. 17. The modulo arithmetic processor chip according to item 16. (19) A modulo arithmetic processor chip for multiplying an n-bit first integer A by an n-bit second integer B, wherein the multiplication result of the first integer A and the second integer B is The remainder modulo the n-bit fourth integer p regarding the data is n
equal to the third integer C of bits, and the first integer A above is A=A[n-1]2^n^-^1+A[n-2]2^n
^-^2+A[n-3]2^n^-^3+...+A[
1] Binary number in the representation consisting of 2+A[0] {A[i
]}, and the second integer B is expressed as B=B[n-1]2^n^-^1+B[n-2]2^n
^-^2+B[n-3]2^n^-^3+...+B[
1] Binary number in the representation consisting of 2+B[0] {B[i
]}, and the third integer C is expressed as C=C[n-1]2^n^-^1+C[n-2]2^n
^-^2+C[n-3]2^n^-^3+...+C[
1] Binary number in the representation consisting of 2+C[0] {C[i
]}, and the fourth integer p is expressed as p=P[n-1]2^n^-^1+P[n-2]2^n
^-^2+P[n-3]2^n^-^3+...+P[
1] Binary number in the representation consisting of 2+P[0] {P[i
]}, thereby C=A・B mod
p, and the modulo arithmetic processor chip has a first register means for storing the first integer A, a second register for storing the second integer B, and a feedback number F. feedback means for generating a feedback number F, wherein said feedback number F is the two's complement of a fourth integer p, such that F=2^n-p, and is connected to said second register means. , adds the feedback number F to the second integer B in response to the most significant second integer B being shifted to the left from the second register means, thereby increasing the number of the second integer B. a first partial conversion means for converting a portion; and a first integer A shifted to the right from said first register means and connected to said first register means and said second register means. arithmetic means for adding the second integer B to the third integer C in response to the lowest integer; and accumulator means connected to the arithmetic means for storing the third integer C; means connected to the accumulator means and responsive to a third integer C greater than the fourth integer p for converting it into a remainder of the third integer C modulo the fourth integer p. A modulo arithmetic processor chip. (20) Claim characterized in that the arithmetic means includes a plurality of full adders connected to the second register means for simultaneously adding the second integer B to the third integer C. 20. The modulo arithmetic processor chip according to item 19. (21) Claim characterized in that the arithmetic means includes a plurality of half adders connected to the second register means for simultaneously adding the second integer B to the third integer C. 20. The modulo arithmetic processor chip according to item 19. (22) A modulo arithmetic processor chip for multiplying an n-bit first integer A by an n-bit second integer B, the chip comprising: a multiplication result of the first integer A and the second integer B; The remainder modulo the n-bit fourth integer p regarding the data is n
is equal to the third integer C of bits, and the base bit of the first integer A is: A_1=A_1[n-1]2^n^-^1+A_1[n
-2]2^n^-^2+A_1[n-3]2^n^-^
It is represented by a binary number {A, [i]} in the representation consisting of 3+...+A_1[1]2+A_1[0], and the carry bit of the first integer A is A_2=A_2[n
-1]2^n^-^1+A_2[n-2]2^n^-^
2+A_2[n-3]2^n^-^3+...+A_2
[1] Binary number expressed as 2+A_2[0] {
A_2[i]}, and the radix bit of the second integer B is B_1=B_1[n-1]2^n^-^1
+B_1[n-2]2^n^-^2+B_1[n-3]
2^n^-^3+...+B_1[1]2+B_1[0
], and the carry bit of the second integer B is B_
2=B_2[n-1]2^n^-^1+B_2[n-2
]2^n^-^2+B_2[n-3]2^n^-^3+
...+B_2[1]2+B_2[0], represented by the binary number {B_2[i]}, and the radix bit of the third integer C is C_1=C_1[n-1]
2^n^-^1+C_1[n-2]2^n^-^2+C
_1[n-3]2^n^-^3+...+C_1[1]
Binary number in the representation consisting of 2+C_1[0] {C_1
[i]}, and the carry bit of the third integer C is C_2=C_2[n-1]2^n^-^1+
C_2[n-2]2^n^-^2+C_2[n-3]2
^n^-^3+...+C_2[1]2+C_2[0]
It is represented by a binary number {C_2[i]} in the representation, and the fourth integer p is expressed as p=P[n-1]2^n^-^1+P[n-2]2^n
^-^2+P[n-3]2^n^-^3+...+P[
1] Binary number in the representation consisting of 2+P[0] {P[i
]}, thereby C=A・B mod
p, and the modulo arithmetic processor chip comprises a first radix register means for storing a radix bit of the first integer A, and a first radix register means for storing a carry bit of the first integer A. carry register means; second radix register means for storing a radix bit of said second integer B; second carry register means for storing a carry bit of said second integer B; 1 feedback number F_1, a second feedback number F_2, a third feedback number F_4, and a fourth feedback number F_4, wherein the first feedback number F_1 is the fourth integer. It is the two's complement of p, which makes F_1=2^n-
p, and the second feedback number F_2 is equal to twice the first feedback number F_1, so that F_2=2F_1
mod p, and the third feedback number F_3 is equal to three times the first feedback number F_1, so that F_3
=3F_1 mod p, and the fourth feedback number F_
4 is four times the first feedback number F_1, so that F_4=4F_1 mod p, and is connected to the second radix register means, the second carry register means and the feedback means, moving the second integer B to the left in response to the most significant radix bit and carry bit of the second integer B being moved leftward from the radix register means of 2 and the second carry register means; adding said first, second, third, or fourth feedback number to said second integer B according to a preselected selection of said radix bit and carry bit, thereby said second integer number B;
a first partial conversion means for converting a part of the integer B; the first radix register means, the first carry register means, the second radix register means and the second carry register; a plurality of full adders connected to said first register means, responsive to the least significant of said first integer A being shifted to the right from said first register means; After simultaneously adding the radix bit and carry bit of the second integer B to each radix bit of the third integer C using the plurality of full adders to generate a sum, the plurality of full adders arithmetic means for adding the radix bit and carry bit of the first sum to each carry bit of the third integer C using accumulator radix means for storing; accumulator carry means connected to said arithmetic means for storing a carry bit of said third integer C; and overflow means connected to said accumulator means for storing an overflow integer I. and said feedback means connected to said overflow means, said feedback means, said first radix register means and said second radix register means, respectively in response to said overflow integer I=1, 2, 3, or 4. fetches the first, second, third, or fourth feedback number outputted from the first, second, third, or fourth feedback number into the second radix register means, and respectively fetches the first, second, third, or fourth feedback number from a second partial conversion means for adding the third integer C stored in the accumulator radix means and the accumulator carry means using the arithmetic means; A modulo arithmetic processor chip characterized by comprising means for converting a third integer C larger than p into a remainder of the third integer C modulo the fourth integer p. . (23) A modulo arithmetic processor chip for multiplying an n-bit first integer A by an n-bit second integer B, the chip comprising: a multiplication result of the first integer A and the second integer B; The remainder modulo the n-bit fourth integer p regarding the data is n
equal to the third integer number C of bits, thereby making C=A・
B mod p, and the modulo arithmetic processor chip includes a first radix register means for storing a radix bit of the first integer A, and a first radix register means for storing a carry bit of the first integer A. 1 carry register means; second radix register means for storing the radix bits of the second integer B; and second carry register means for storing the carry bits of the second integer B. , feedback means for generating a first feedback number F_1, a second feedback number F_2, a third feedback number F_3, and a fourth feedback number F_4, wherein the first feedback number F_1 is the fourth feedback number F_4. is the two's complement of the integer p, which makes F_1=2^n-
p, and the second feedback number F_2 is equal to twice the first feedback number F_1, so that F_2=2F_1
mod p, and the third feedback number F_3 is equal to three times the first feedback number F_1, so that F_3
=3F_1 mod p, and the fourth feedback number F_
4 is four times said first feedback number F_1, thereby F_4=4F_1 mod p, said first radix register means, said first carry register means, said second radix register means and said a second carry register means for generating a first sum having a radix bit and a carry bit in response to the least significant of said first integer A shifted to the right from said first register means; After adding the radix bit and carry bit of the second integer B to each radix bit of the third integer C, add each radix bit and carry bit of the third integer C to the radix bit and carry bit of the first sum. an arithmetic means for adding to a carry bit; an accumulator radix means connected to the arithmetic means and for storing the radix bit of the third integer C; and an accumulator radix means connected to the arithmetic means and a carry of the third integer C. an accumulator carry means for storing bits; an overflow means connected to the arithmetic means and for storing an overflow integer I; the overflow means, the feedback means, the first radix register means and the second radix. said first, second, third, or fourth feedback number connected to said register means and output from said feedback means in response to said overflow integer I=1, 2, 3, or 4, respectively; a third integer stored in the accumulator radix means and the accumulator carry means by respectively fetching the first, second, third, or fourth feedback number into the radix register means using the arithmetic means. second partial conversion means for adding to C modulo said fourth integer p in response to a third integer C connected to said accumulator base means and greater than said fourth integer p; and means for converting the third integer C into a remainder. (24) The arithmetic means is connected to the second radix register means and the second carry register means to calculate the radix of the second integer B for generating a first sum having a radix bit and a carry bit. 24. The modulo arithmetic processor chip of claim 23, further comprising a plurality of full adders for simultaneously adding bits and carry bits to the radix bits of the third integer C. (25) The modulo arithmetic processor chip further converts the radix bit and carry bit of the first sum into the third
25. The modulo arithmetic processor chip of claim 24, further comprising multiplexer means for controlling said plurality of full adders to add to the carry bit of an integer C. (26) A modulo arithmetic processor chip for multiplying an n-bit first integer A by an n-bit second integer B, the chip comprising: a multiplication result of the first integer A and the second integer B; The remainder modulo the n-bit fourth integer p regarding the data is n
equal to the third integer number C of bits, thereby making C=A・
B mod p, and the modulo arithmetic processor chip includes a first radix register means for storing a radix bit of the first integer A, and a first radix register means for storing a carry bit of the first integer A. 1 carry register means; second radix register means for storing the radix bits of the second integer B; and second carry register means for storing the carry bits of the second integer B. , feedback means for generating a first feedback number F_1, a second feedback number F_2, a third feedback number F_3, and a fourth feedback number F_4, wherein the first feedback number F_1 is the fourth feedback number F_4. is the two's complement of the integer p, which makes F_1=2^n-
p, and said second feedback number F_2 is equal to twice said first feedback number F_1, thereby making F=2F_1
mod p, and the third feedback number F_3 is the first feedback number F_3.
is equal to three times the feedback number F_1, which makes F_3=
3F_1 mod p, and the fourth feedback number F_4 is
is four times said first feedback number F_1, thereby F_4=4F_1 mod p, and is connected to said second radix register means, said second carry register means and said feedback means, said second and said second integer B is shifted to the left in response to the most significant radix bit and carry bit of said second integer B that is shifted to the left from said radix register means and said second carry register means. adding said first, second, third, or fourth feedback number to said second integer B according to a preselected selection of a base bit and a carry bit, thereby adding said second integer B to said second integer B; a first partial conversion means for converting a portion of the digits; and connected to the first radix register means, the first carry register means, the second radix register means and the second carry register means. said second integer B to generate a first sum having a radix bit and a carry bit in response to the least significant of said first integer A being shifted to the right from said first register means. an operation for adding the radix bit and carry bit of the first sum to each radix bit of the third integer C, and then adding the radix bit and carry bit of the first sum to each carry bit of the third integer C; means, an accumulator radix means connected to said accumulator means for storing a radix bit of said third integer C; and an accumulator carry connected to said accumulator means for storing a carry bit of said third integer C. overflow means connected to said accumulator means for storing an overflow integer I; and overflow means connected to said accumulator radix means for storing said fourth integer C greater than said fourth integer p. and means for converting the third integer C into a remainder modulo the integer p. (27) said arithmetic means is connected to said second radix register means and said second carry register means and said second integer B for generating a first sum having a radix bit and a carry bit; 27. The modulo arithmetic processor chip of claim 26, further comprising a plurality of full adders for simultaneously adding a radix bit and a carry bit to the radix bit of the third integer C. (28) The modulo arithmetic processor chip further converts the radix bit and carry bit of the first sum into the third
28. The modulo arithmetic processor chip of claim 27, further comprising multiplexer means for controlling said plurality of full adders to add to a carry bit of an integer C. (29) A modulo arithmetic processor chip for multiplying an n-bit first integer A by an n-bit second integer B, the chip comprising: a multiplication result of the first integer A and the second integer B; The remainder modulo the n-bit fourth integer p regarding the data is n
equal to the third integer number C of bits, thereby making C=A・
B mod p, and the modulo arithmetic processor chip includes a first radix register means for storing a radix bit of the first integer A, and a first radix register means for storing a carry bit of the first integer A. 1 carry register means; second radix register means for storing the radix bits of the second integer B; and second carry register means for storing the carry bits of the second integer B. , comprising feedback means for generating a first feedback number F_1,
Here, the first feedback number F_ is 2 of the fourth integer p.
, thereby F_1=2^n-p, and is connected to the first radix register means, the first carry register means, the second radix register means, and the second carry register means. said second integer B to generate a first sum having a radix bit and a carry bit in response to the least significant of said first integer A being shifted to the right from said first register means. an operation for adding the radix bit and carry bit of the first sum to each radix bit of the third integer C, and then adding the radix bit and carry bit of the first sum to each carry bit of the third integer C; means; accumulator radix means connected to said arithmetic means for storing the radix bits of said third integer C; and accumulator carry means connected to said arithmetic means for storing said third integer carry bits. , overflow means connected to said accumulator means for storing an overflow integer I; and said fourth integer p connected to said accumulator radix means in response to a third integer C greater than said fourth integer p. and means for converting the third integer C into a remainder modulo C. (30) The arithmetic means is connected to the second radix register means and the second carry register means to calculate the radix of the second integer B for generating a first sum having a radix bit and a carry bit. 30. The modulo arithmetic processor chip of claim 29, further comprising a plurality of full adders for simultaneously adding bits and carry bits to the radix bits of the third integer C. (31) The modulo arithmetic processor chip further converts the radix bit and carry bit of the first sum into the third
31. The modulo arithmetic processor chip of claim 30, further comprising multiplexer means for controlling a plurality of full adders to add to the carry bit of the integer C. (32) A modulo arithmetic processor chip for multiplying an n-bit first integer A by an n-bit second integer B, the chip comprising: a multiplication result of the first integer A and the second integer B; The remainder modulo the n-bit fourth integer p regarding the data is n
is equal to the third integer C of bits, and the base bit of the first integer A is: A_1=A_1[n-1]2^n^-^1+A1[n-
2] 2^n^-^2+A_1[n-3]2^n^-^3
+...+A_1[1]2+A_1[0], represented by the binary number {A_1[i]}, and the carry bit of the first integer A is A_2=A_2[n
-1]2^n^-^1+A_2[n-2]2^n^-^
2+A_2[n-3]2^n^-^3+...+A_2
[1] Binary number expressed as 2+A_2[0] {
A_2[i]}, and the radix bit of the second integer B is B_1=B_1[n-1]2^n^-^1
+B_1[n-2]2^n^-^2+B_1[n-3]
2^n^-^3+...+B_1[1]2+B_1[0
], and the carry bit of the second integer B is B_
2=B_2[n-1]2^n^-^1+B_2[n-2
]2^n^-^2+B_2[n-3]2^n^-^3+
...+B_2[1]2+B_2[0], represented by the binary number {B_2[i]}, and the radix bit of the third integer C is C_1=C_1[n-1]
2^n^-^1+C_1[n-2]2^n^-^2+C
_1[n-3]2^n^-^3+...+C_1[1]
Binary number in the representation consisting of 2+C_1[0] {C_1
[i]}, and the carry bit of the third integer C is C_2=C_2[n-1]2^n^-^1+
C_2[n-2]2^n^-^2+C_2[n-3]2
^n^-^3+...+C_2[1]2+C_2[0]
It is represented by a binary number {C_2[i]} in the representation, and the fourth integer p is expressed as p=P[n-1]2^n^-^1+P[n-2]2^n
^-^2+P[n-3]2^n^-^3+...+P[
1] Binary number in the representation consisting of 2+P[0] {P[i
]}, thereby C=A・B mod
p, and the modulo arithmetic processor chip comprises a first radix register means for storing a radix bit of the first integer A, and a first radix register means for storing a carry bit of the first integer A. carry register means; second radix register means for storing a radix bit of said second integer B; second carry register means for storing a carry bit of said second integer B; a feedback means for generating a feedback number F_1, a second feedback number F_2, a third feedback number F_3, and a fourth feedback number F_4, wherein the first feedback number F_1 is the fourth integer. It is the two's complement of p, which makes F_1=2^n-
p, and the second feedback number F_2 is equal to twice the first feedback number F_1, so that F_2=2F_1
mod p, and the third feedback number F_3 is equal to three times the first feedback number F_1, so that F_3
=3F_1 mod p, and the fourth feedback number F_
4 is four times the first feedback number F_1, so that F_4=4F_1 mod p, and is connected to the second radix register means, the second carry register means and the feedback means, moving the second integer B to the left in response to the most significant radix bit and carry bit of the second integer B being moved leftward from the radix register means of 2 and the second carry register means; adding the first, second, third, or fourth feedback number to the second integer B according to a preselected selection of the radix bit and carry bit, thereby
a first partial conversion means for converting a part of the integer B; the first radix register means, the first carry register means, the second radix register means and the second carry register; a plurality of full adders connected to said first register means, responsive to the least significant of said first integer A being shifted to the right from said first register means; After simultaneously adding the radix bit and carry bit of the second integer B to each radix bit of the third integer C using the plurality of full adders to generate a sum, the plurality of full adders arithmetic means for adding the radix bit and carry bit of the first sum to each carry bit of the third integer C using accumulator radix means for storing; accumulator carry means connected to said arithmetic means for storing a carry bit of said third integer C; and overflow means connected to said accumulator means for storing an overflow integer I. and is connected to the overflow means, the feedback means, the first radix register means, and the second radix register means, and is responsive to completion of the multiplication of the first integer A and the second integer B. transfers the overflow integer I to the first register means and transfers the first feedback number F_1 to the second register means.
the first register means for generating the product.
a second partial conversion means for multiplying the feedback number F_1 of by the overflow integer I and adding the product to the third integer C stored in the accumulator base means and the accumulator carry means; means connected to the radix means for converting the third integer C, which is larger than the fourth integer p, into a remainder of the third integer C modulo the fourth integer p; A modulo arithmetic processor chip. (33) A modulo arithmetic processor chip for multiplying an n-bit first integer A by an n-bit second integer B, the chip comprising: a multiplication result of the first integer A and the second integer B; The remainder modulo the n-bit fourth integer p regarding the data is n
equal to the third integer number C of bits, thereby making C=A・
B mod p, and the modulo arithmetic processor chip includes a first radix register means for storing a radix bit of the first integer A, and a first radix register means for storing a carry bit of the first integer A. 1 carry register means; second radix register means for storing the radix bits of the second integer B; and second carry register means for storing the carry bits of the second integer B. , feedback means for generating a first feedback number F_1, a second feedback number F_2, a third feedback number F_3, and a fourth feedback number F_4, wherein the first feedback number F_1 is the fourth feedback number F_4. is the two's complement of the integer p, which makes F_1=2^n-
p, and the second feedback number F_2 is equal to twice the first feedback number F_1, so that F_2=2F_1
mod p, and the third feedback number F_3 is equal to three times the first feedback number F_1, so that F_3
=3F_1 mod p, and the fourth feedback number F_
4 is four times said first feedback number F_1, thereby F_4=4F_1 mod p, said first radix register means, said first carry register means, said second radix register means and said for generating a first sum having a radix bit and a carry bit in response to the least significant of said first integer A being shifted to the right from said first register means connected to a second carry register means; After adding the radix bit and carry bit of the second integer B to each radix bit of the third integer C, the radix bit and carry bit of the first sum are added to each carry bit of the third integer C. arithmetic means for adding to bits; accumulator radix means connected to said arithmetic means for storing radix bits of said third integer C; and carry bits of said third integer C connected to said arithmetic means. accumulator carry means for storing an overflow integer I; overflow means connected to the accumulator means for storing an overflow integer I; the overflow means, the feedback means, the first radix register means and the second radix register. means for transferring said overflow integer I to said first register means in response to completion of the multiplication of said first integer A and said second integer B; 2, the first feedback number F_1 is multiplied by the overflow integer I to generate a product, and the product is transferred to a third integer C stored in the accumulator base means and the accumulator carry means. second partial conversion means connected to said accumulator base means for adding to said fourth integer p modulo said fourth integer p in response to a third integer C greater than said fourth integer p; A modulo arithmetic processor chip, characterized in that it comprises means for converting into a third integer C. (34) said arithmetic means is connected to said second radix register means and said second carry register means and said second integer B for generating a first sum having a radix bit and a carry bit; 34. The modulo arithmetic processor chip of claim 33, further comprising a plurality of full adders for adding a radix bit and a carry bit to the radix bit of the third integer C. (35) The modulo arithmetic processor chip further converts the radix bit and carry bit of the first sum into the third
35. The modulo arithmetic processor chip of claim 34, including multiplexer means for controlling a plurality of full adders to add to the carry bit of the integer C.