JPS63281140A - Focus detecting device - Google Patents

Abstract

PURPOSE:To contrive the exact detection of a focus by executing an operation for detecting a focus by switching an output signal of a first converting means to an output signal of a second converting means having compressibility in input and output signals, based on a result of deciding whether the output signal of the first converting means having linearity in the output signal is correct or not. CONSTITUTION:An image formed by a focus detecting optical system is converted photoelectrically, and this photoelectric converting signal is coded digitally by the first converting means 24 whose input/output characteristic has linearity. Subsequently, whether an output signal of the first converting means 24 is correct or not is decided, and when said signal has been decided to be correct, an operation for detecting a focus is executed, based on a digital output of the first converting means 24. When a result of decision to be incorrect has been obtained, the photoelectric converting signal is coded digitally by the second converting means 22 whose input/output characteristic has compressibility, and an operation for detecting a focus is executed, based on this digital output. In such a way, even with respect to an object to be photographed, whose luminance is varied greatly the focus can be detected exactly.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention photoelectrically converts an image formed by a focus detection device, more specifically, a focus detection optical system, and converts this photoelectric conversion value into an analog/digital (hereinafter referred to as , abbreviated as A/D) and performs focus detection calculations.

[Prior Art] As is well known, there are focus detection devices for cameras that use a phase difference method, a contrast method, etc.;
20053, etc.), its basic configuration is shown in FIG.

The pupil division optical system 2 divides the light beam from the exit pupil of the photographic lens 1 into two and guides images of the respective light beams to the A group sensor 3a and the 8 group sensor 3b of the focus detection light receiving element 3. These sensors 3a and 3b are composed of line sensors such as CCDs, and their outputs are connected to the A/C in the interface circuit 4.
After being digitally coded by a D converter (not shown), the signal is input to the CPU (Central Processing Unit) 5.

In the CPU 5, by performing a correlation calculation on this digital data, the image on the A group sensor 3a and the image on the 8 group sensor 3 are
The relative shift with respect to the image on b is calculated, and from this result, the amount and direction of shift of the image formed by the photographing lens 1 with respect to the focal plane are detected. By the way, in order to accurately match the result of the correlation calculation with the amount of deviation, the output of the A/D converter is the sensor 3a.

It is necessary to accurately convert the output of 3b. Since the outputs of the sensors 3a and 3b vary greatly depending on the brightness of the subject, they cannot be directly input to the A/D converter. Therefore, in general, the sensors 3a and 3b
It is required to control the output so that it falls within the dynamic range of the A/D converter. As a method of controlling the sensor output, a method generally used is to vary the integration time of the sensors 3a, 3b to fit within a dynamic range. Since the outputs of the sensors 3a and 3b correspond to the contrast of the subject, the data has a certain level width. Several methods of controlling the sensor output can be considered depending on which level of this data corresponds to which range of the A/D converter. The most commonly used method is a method (hereinafter referred to as an average control method) in which the integration time is varied so that the average value of the sensor output is located at the center of the range of the A/D converter.

Another method is to change the integration time so that the maximum value of the sensor output becomes the maximum value of the range (hereinafter referred to as the peak control method).

[Problems to be Solved by the Invention] Let us now consider a case where the subject contrast changes drastically and the sensor output level changes significantly. Assuming that a subject image with contrast as shown in FIG. 10(A) is formed on the sensors 3a and 3b, after changing the integration time using the peak control method,
After D conversion, the result of A/D conversion becomes as shown in FIG. 10(B). In this case, parts with high subject brightness can be converted accurately, but parts with low brightness cannot be converted accurately because their level is low compared to the resolution of the A/D converter, which reduces the amount of data that can be used for correlation calculations. . Also,
After changing the integration time using the average control method,
When A/D conversion is performed, the result of A/D conversion becomes as shown in FIG. 10(C).

In this case, control is performed based on the average value of the sensor output, so parts with high subject brightness exceed the dynamic range of the A/D converter, and for inputs exceeding this range, the A/D converter outputs is output as the maximum value of Therefore, regardless of the control method, the A/D
Since the converter output is not a partial accurate conversion of the sensor output, even if a correlation calculation is performed based on such data, the in-focus point cannot be detected accurately.

In this way, for subjects with sharp contrast changes, the output data of the sensors 3a and 3b can be accurately transmitted to the CPU.
It was difficult to convey this to 5.

Therefore, one possible method to solve this problem is to use the 8-bit A/D that is commonly used in cameras.
This is a method of expanding the dynamic range by using an A/D converter with a larger number of bits than the converter. However, this method is not preferable because it has problems such as a decrease in the conversion speed of the A/D converter and a decrease in the calculation speed caused by processing data of 8 bits or more with a commonly used 8-bit CPU. .

In view of the above-mentioned problems, the present invention enables accurate focus detection even for subjects with severe brightness reduction, without causing a decrease in the conversion speed of the A/D converter or a decrease in the calculation speed of the CPU. An object of the present invention is to provide a focus detection device.

[Means and effects for solving the problems] The focus detection device of the present invention photoelectrically converts an image formed by a focus detection optical system, and converts this photoelectric conversion signal into a first signal having linear input/output characteristics. It is converted into a digital code by a conversion means. Then, it is determined whether or not the output signal of the first conversion means is appropriate, and when it is determined that it is appropriate, a focus detection calculation is performed based on the digital output of the first conversion means, and if the output signal is determined to be inappropriate, If the determination result is obtained, the photoelectric conversion signal is converted into a digital code by the second conversion means having compressible input/output characteristics, and focus detection calculations are performed based on this digital output.

[Example] FIG. 1 shows a focus detection device showing one embodiment of the present invention.

In this focus detection device, an A group sensor 13a, an 8 group sensor 1, which is composed of a CCD line sensor,
3b, a buffer amplifier 13c, etc., the focus detection light receiving circuit 13 is controlled by a control signal from a control logic circuit 21 in the interface circuit 14.
The pupil division optical system 2 (see FIG. 9) is the A group sensor 13a.

These sensor outputs based on the image formed on the 8 group sensor 13b are transferred to the interface circuit 14. The interface circuit 14 connects both groups A and B sensors 13a.
, 13b (hereinafter simply referred to as sensor output), the compression circuit 22 has a multiplexer 23, an 8-bit A/D converter 24, and a control logic circuit 21. The multiplexer 23 is a circuit that switches the input of the A/D converter 24, and the control logic circuit 21 switches the input of the light receiving circuit 13. Multiplexer 23. A/D converter 2
This is a circuit that performs control of No. 4.

By sending a control signal to the control logic circuit 21, the CPU 15 inputs 8-bit data obtained by converting the sensor output into digital codes from the A/D converter 24 to the terminal DI-D8, and based on this data, it inputs the 8-bit data necessary for in-focus point detection. perform calculations.

Then, when this calculation result is inputted manually to the motor drive circuit 16, the motor 17 is driven, and the photographing lens 11 is moved to the in-focus position. Further, the CPU 15 initially controls the multiplexer 23 by the control logic circuit 21 so as to input the sensor output that does not pass through the compression circuit 22 to the A/D converter 24, but the input data is not suitable for calculation. If it is determined, the multiplexer 23 is controlled via the control logic circuit 21 so that the sensor output is compressed by the compression circuit 22, and the compressed data is sent to the A/D converter 24 manually. Note that the input data AA to the multiplexer 23...
. . ., AN is analog data from a photometry circuit, a battery check circuit, etc. other than the focus detection [° 2″ light receiving circuit 13], and these data are also A/D in this interface circuit 14. The data is converted and input to the CPU 15.

Here, the input/output characteristics of the compression circuit 22 are preferably nonlinear characteristics as shown in FIG. 2. That is, for example, when input data In is passed through an amplifier with such nonlinear input/output characteristics,
Output data Out is obtained by compressing this input data In according to the characteristics of the amplifier. As is clear from this input/output data waveform diagram, the output data Out
The peak control method amplifies low brightness areas where accurate values cannot be obtained, and the average control method amplifies high brightness areas that would exceed the range of the A/D converter within the range. It has been compressed to a level that fits within.

FIG. 3 shows a specific electric circuit configuration of the compression circuit 22. As shown in FIG. In the compression circuit 22 shown in FIG. 3, the amplifier having the characteristics shown in FIG. 2 is realized by a linear function approximation circuit using diodes. This compression circuit 22 includes operational amplifiers 31 to 33. Diodes 34-37
and resistors 38 to 47, and the non-inverting input terminals of operational amplifiers 31 to 33 have a reference voltage V rc4'
is applied, and resistors 3g and 41 are connected to the inverting input terminal, respectively.
．． An input voltage (sensor output) VIn is applied via 44. Further, a bias v1 is applied to the inverting input terminal of the operational amplifier 31 via a resistor 39, and a bias v2 is applied to the inverting input terminal of the operational amplifier 32 via a resistor 42.
is applied. A compressed output v out is obtained from the output terminal of the operational amplifier 33. A.

Since the CCD line sensors used in both group B sensors 13a and 13b output a negative potential with respect to the reference voltage V rer, in this compression circuit 22, the sensors inputted with a negative potential with respect to the reference voltage V rer are After compressing the output, it is assumed that the output is positive with respect to the reference voltage Vrcf'. The potentials in the circuit diagram, that is, the potentials of the input terminal V1n, the biases V t and V 2 , and the compressed output V out, are handled based on the reference voltage Vraf. It is assumed that the bias vv has the following relationship: vrer, Vl, V2. Therefore, in the circuit shown in FIG. 3 above, the resistance values of resistors 38 to 44 are set to R, and
5, 46.47 are respectively R1, R2, and R3, the relationship between the input voltage Van and the compressed output V out is as follows: The input voltage Vin is -V1 from the reference voltage V ref'.
When between, the following equation (1) is obtained.

Vout=−Vin−R3/R−・−−(1) Also,
When the input voltage V1n is between -V and -V2, the following equation (2) is obtained.

Vout=-Vin(/R-/R1)+V-”'/
RIR3R3 (2) Furthermore, when the input voltage Vin is lower than -22, the following equation (3) holds true.

Vout --Vln (R"/R-R3/R1-R3
/R2)R3R3 +V ・ /R1+V ・ /R2 ・・・・・・・・・・・・・・・(3) When the above formulas (1) to (3) are illustrated, it becomes as shown in Fig. 4, and the human output A characteristic line is formed by straight lines Sl, S2°S3. Straight line Sl, S2. Regarding the slope of S3, S
l;-”/R,S2;-(1/R-1/R1)
R3, S3; -(1/R-1/R1-1/R2)
R3, so the bias v1. v2 and resistance value R2
The input/output characteristics shown in FIG. 2 can be approximated depending on the selection method (old, R2, R1). In addition to the circuit configuration shown in FIG. 3, the compression circuit 22 may also include a semiconductor PN.
Another possible method is to use a logarithmic amplifier that takes advantage of the forward characteristics of the junction.

Next, the operation of the focus detection device shown in FIG. 1 will be explained using the flowchart shown in FIG.

When an autofocus (AF) routine is called in the camera, the CPU 15 sets an AF counter inside the CPU to "1". From then on, the AP counter increases by 1 degree each time the AF routine is executed. When the AP counter finishes counting, it is checked whether a flag is set. Depending on the presence or absence of this flag, the light receiving circuit It is determined whether to compress the CCD data that is the sensor output of 13 and perform A/D conversion, or to perform normal A/D conversion without compression.
5, the input of any predetermined multiplexer 23 is A/
A signal is sent to the control logic circuit 21 so as to be guided to the D converter 24.

Immediately after entering the AF routine, the state of the subject is still unknown, so the flag is not set, and A/D conversion of uncompressed normal data is set, but because the subject has too much contrast, When the flag is set, A/D conversion of compressed data continues to be selected until the AF routine ends. When the A/D conversion set is completed, the CPU 15 starts the control logic circuit 21.
Sends a CCD data integration start signal to. The control logic circuit 21 integrates the CCD data, and when it reaches a predetermined level, the A/D converter 24 converts the CCD output data into digital code and sends it to the CPU 15. When the data is sent, the CPU 15 first selects A from the CCD data.
It is determined whether sufficient conditions are met to perform the llll arithmetic operation. When the conditions for distance measurement calculation are not met, a flag is set, and when the conditions are met, distance measurement calculation is performed. If the distance measurement calculation result is not within the focus determination level, the photographing lens 11 is driven, and the process returns to the beginning of the AF routine to perform focus determination again. When the focus is within the focus determination level, the presence or absence of a flag is checked, and if the flag is not set, the AF counter is set to "θ", the flag is cleared, and the AP routine ends. If the flag is set, go to F
Check whether the count value of the counter is "lo", and if it is not "1", set the AF counter to "0", clear the flag, and end the AF routine.If the AF counter is "1", This is a case where the COD data is not suitable for calculation, but the distance measurement calculation is performed and the focus is determined, so the focus determination in this case is invalidated and the distance measurement is performed again. Return to the beginning of the AP routine to do this.

Although the focus detection device shown in FIG. 1 compresses the data before inputting it to the A/D converter 24, the A/D converter itself may be provided with a compression function.

FIG. 6 is an electrical circuit diagram of an example of a parallel A/D converter having a compression function. This A/D converter 50 is
(28-1) comparators CM1 to cM255 are provided with individual comparison voltages corresponding to each quantization level from zero to full scale, and are connected to the non-inverting input terminals of each of these comparators. Analog switch 5WI-5
W255, a first voltage dividing resistor with a resistance value R connected between the first contact terminals 8 of analog switches SWL to SW255, and analog switches SWI to 5W25.
5, and a coding logic circuit 51 that converts the output of the comparator into an 8-bit digital code. It is configured.

The output of the multiplexer 23 (see FIG. 1) is led to the inverting input terminal of the comparator CMI-CM255.

Above 1. One end of the second voltage dividing resistor string has a reference voltage V r
ef is applied, and the other end is connected to the power supply terminal 52 via a resistor having a resistance value RO. That is, comparator CM
The comparison voltage of the I-CM 255 is determined by the reference voltage V rcr and two rows of voltage dividing resistors.

When the analog switch 5WI-SW255 is connected to the contact terminal a of ml, the first voltage dividing resistors all have the same resistance value R, so the comparison voltages of the comparators CMI to CM255 are sequentially set at the same potential difference starting from the minimum voltage. The input voltage and the digitally encoded output voltage are linear. When the analog switch 5WI-SW255 is connected to the second contact terminal, the comparison voltage at this time is the second
It is determined by the resistance values R1 to R255 of the voltage dividing resistors.

The resistance values R1 to R255 of the second voltage dividing resistors are set, for example, in the following relationship.

Rn-old×K (n-1) where R1 is the initial resistance, the rate of increase in resistance is a value of 1 or more, and n is the number of the resistance.

If such a second voltage dividing resistor is used, the comparison voltage will increase exponentially, and as the number of input terminals increases, the comparators CMI to CM255 will become difficult to invert. The relationship with the converted output voltage is the relationship of the input/output characteristics shown in FIG. 2, and as a result, compressed data can be obtained.

Next, another embodiment of the present invention will be described.

In the embodiment shown in FIG. 1, compressed data and uncompressed data are A/D converted by one A/D converter, so a time delay occurs. Therefore, the focus detection device shown in FIG. 7 uses two A/D converters to simultaneously obtain compressed data and uncompressed data. That is, the focus detection device shown in FIG. 7 has an interface circuit 60 having a different configuration from that of the focus detection device shown in FIG. 1. The interface circuit 60 includes a control logic circuit 61 and a compression circuit 6 that compresses the output of the light receiving circuit 13.
2, a multiplexer 63 that allows the output of the light receiving circuit 13 to pass through without being compressed, and this multiplexer 63.
A first A/D converter 64 that A/D converts the output of the compression circuit 62, a second A/D converter 65 that A/D converts the output of the compression circuit 62, and an output of the second A/D converter 65. A memory 66 for temporarily storing the CP
It is composed of a switching circuit 67 for inputting to U6B.

The control logic circuit 61 operates based on a control signal from the CPU 6g, and the light receiving circuit 13. Multiplexer 63. A/D
Controls converters 64, 65 and switching circuit 67.

Next, the operation of the embodiment shown in FIG. 7 will be explained with reference to the flowchart shown in FIG. When the AF routine is called, the CPU 6g first sends a signal to start integrating CCD output data to the control logic circuit 61.

The control logic circuit 61 integrates the CCD output data, and when it reaches a predetermined level, it digitally encodes the COD output at the same time at the two A/D controllers (64° and 65°).The CPU 6g first performs compression. It reads the normal data that is not available, and determines whether the data is suitable for a calculation. If there is a problem such as the brightness of the subject being too high or low, the compressed data is read from the memory 66. Load. Then flP
Perform J distance calculation, and if the calculation result is within the focusing range, select A.
End the F routine.

If it is out of the focus range, the photographing lens 11 is driven and the process returns to the beginning of the AF routine to determine focus again.

□Although each of the embodiments described above is applied to a focus detection device using a phase difference method, it may also be applied to a focus detection device using a contrast method using a line sensor such as a COD.

[Effects of the Invention] As described above, according to the present invention, it is possible to accurately photograph objects with rapid brightness changes without increasing the number of bits of the A/D converter or slowing down the calculation speed of the CPU. Focus detection can be performed accurately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a focus detection device showing an embodiment of the present invention; FIG. 2 is a diagram showing ideal human output characteristics and input/output waveforms of the compression circuit shown in FIG. 1; 3 is an electric circuit diagram of an example of the compression circuit shown in FIG. 1, FIG. 4 is a characteristic diagram of input/output signals of the compression circuit shown in FIG. 3, and FIG. FIG. 6 is an electric circuit diagram showing an example of an A/D converter having a compression function. FIG. 7 is a flowchart explaining the AF routine of the focus detection device shown in the figure. 8 is a flowchart explaining the AP routine of the focus detection device shown in FIG. 7, and FIG. 9 is a basic configuration of an example of the focus detection device using the phase difference method. Figures 10 (A), (B) and (C) are block diagrams showing the sensor output when there is a large change in subject contrast and the A/D when the integration time of this sensor output is changed by the peak control method. This is an A/D conversion output changed by a conversion output and an average control method. 13a...A group sensor (photoelectric conversion means) 13b...8 group sensor (photoelectric conversion means) 21.61...Control logic Circuit (calculating means) 22.62...Compression circuit (second conversion means) 23.63...Multiplexer (first conversion means) 24.50.・・・・・・・・・A/D converter (first
．． second conversion means)

Claims (1)

[Scope of Claims] A means for photoelectrically converting an image formed by a focus detection optical system, and a first converter having linearity in an input signal and an output signal for converting the output of the photoelectric converter into a digital code. and a second conversion means that compresses the input signal and output signal for digitally encoding the output of the photoelectric conversion means, and means for determining whether the output signal of the first conversion means is appropriate. and calculation means for performing focus detection calculations by switching from the output signal of the first conversion means to the output signal of the second conversion means based on the determination result of the determination means. Focus detection device.