JPS63280557A - Power receiving circuit - Google Patents

Power receiving circuit

Info

Publication number
JPS63280557A
JPS63280557A JP11630487A JP11630487A JPS63280557A JP S63280557 A JPS63280557 A JP S63280557A JP 11630487 A JP11630487 A JP 11630487A JP 11630487 A JP11630487 A JP 11630487A JP S63280557 A JPS63280557 A JP S63280557A
Authority
JP
Japan
Prior art keywords
loop
receiving circuit
current
power receiving
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11630487A
Other languages
Japanese (ja)
Inventor
Makoto Ichikawa
誠 市川
Hirobumi Tsukagoshi
塚越 博文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11630487A priority Critical patent/JPS63280557A/en
Publication of JPS63280557A publication Critical patent/JPS63280557A/en
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To reduce the power consumption by inserting a current variable means varying a current flowing to a loop to the loop. CONSTITUTION:In a power reception circuit 20 where it consists of a loop comprising e switch 60 connecting to an exchange or a PCM multiplexer 10, receiving a signaling signal from a telephone set to apply on/off operation, a current variable means 70 varying the current flowing to the loop is inserted to the loop. When the switch 60 is turned on by a signaling signal, a current flows to a loop comprising the current variable means 70 in the power reception circuit 20 connecting to a transmission line and the switch 60 and the current depends on the resistance of the transmission line. The current variable means 70 readjusts the current value to be a prescribed value, then the power consumption in the power reception circuit 20 is reduced.

Description

【発明の詳細な説明】 〔概要〕 電話のダイヤリングやオン/オフ・フックする時発生す
る情報、いわゆるシグナリング信号を処理するPCM多
重化装置等の受電回路において、交換機と受電回路を伝
送線により接続して形成されるループに、1個以上の抵
抗と電子スイッチを直列又は並列に組み合わせて接続し
た回路を挿入する事により、受電回路内のループ抵抗を
変更出来るようにして受電回路における消費電力を低減
化するようにしたものである。
[Detailed Description of the Invention] [Summary] In a power receiving circuit such as a PCM multiplexer that processes information generated when dialing or on/off hooking a telephone, so-called signaling signals, an exchange and the power receiving circuit are connected via a transmission line. By inserting a circuit in which one or more resistors and electronic switches are connected in series or in parallel into the loop formed by the connection, the loop resistance in the power receiving circuit can be changed and the power consumption in the power receiving circuit can be reduced. It is designed to reduce the

(産業上の利用分野) 本発明はPCM多重化装置等でシグナリング信号の処理
を行う受電回路の改良に関するものである。
(Industrial Application Field) The present invention relates to an improvement in a power receiving circuit that processes signaling signals in a PCM multiplexer or the like.

第5図に示すように、交換機とPCM多重化装置の間は
、電話機からの音声信号と、電話機の送受話器を上げた
り下げたりする時、あるいはダイヤルする時発生するシ
グナリング信号を伝送する線で結ばれている。
As shown in Figure 5, there is a line between the exchange and the PCM multiplexer that transmits voice signals from telephones and signaling signals generated when the handset of the telephone is lifted or lowered or when dialing. tied together.

そして、シグナリング信号を交換機に伝送する受電回路
における消費電力をコスト等の点から出来るだけ少なく
出来る回路が、簡単な構成で出来る事が望ましい。
It is desirable to have a circuit with a simple configuration that can reduce the power consumption in the power receiving circuit that transmits the signaling signal to the exchange as much as possible from the viewpoint of cost and the like.

(従来の技術〕 第4図は従来例のPCM多重化装置内の受電回路の構成
を示すブロック図である。
(Prior Art) FIG. 4 is a block diagram showing the configuration of a power receiving circuit in a conventional PCM multiplexing device.

第4図において、加入者が電話機を持ち上げる(オフフ
ックする)と、第5図に示すようにシグナリング信号が
電話機から交換機5、PCM多重化装置4、伝送線を介
して、PCM多重化装置3内の受電回路2に送られ、電
子化したスイッチ6がオンとなる。
In FIG. 4, when the subscriber picks up the telephone (goes off-hook), a signaling signal is transmitted from the telephone to the exchange 5, the PCM multiplexer 4, and the transmission line to the PCM multiplexer 3 as shown in FIG. The power is sent to the power receiving circuit 2, and the electronic switch 6 is turned on.

その結果、交換機1内の電源と回線(その回線抵抗をR
LI 、RL2とする)、受電回路2内のループ抵抗R
o、及び電子化したスイッチ6とにより閉ループが形成
され、電流iが流れる。
As a result, the power supply and line in exchange 1 (the line resistance is R
LI, RL2), loop resistance R in the power receiving circuit 2
o and the electronic switch 6 form a closed loop, through which a current i flows.

上記の回線抵抗RLI 、RL2は回線線路長により変
化し、その最高値は装置の使用される条件によって定め
られており(例えば1.5にΩ)、最低値は0Ωである
。受電回路のループ抵抗Roが一定値の場合、Roの抵
抗値は回線抵抗RL1、RL2の抵抗値が最大の時一定
値(例えば20mA)以上の電流が流れるように選ばれ
る。
The above-mentioned line resistances RLI and RL2 vary depending on the length of the line, and their maximum value is determined by the conditions under which the device is used (for example, 1.5Ω), and the minimum value is 0Ω. When the loop resistance Ro of the power receiving circuit is a constant value, the resistance value of Ro is selected such that a current of a constant value (for example, 20 mA) or more flows when the resistance values of the line resistances RL1 and RL2 are maximum.

[発明が解決しようとする問題点] しかしながら上述の受電回路においては、設置する回線
線路長により回線抵抗の抵抗値が小さくなり、仮に0Ω
となるような場合を考えると、受電回路内のループに流
れる電流が大きくなり、その結果受電回路内の消費電力
が大きくなるという問題点があった。
[Problems to be Solved by the Invention] However, in the above-mentioned power receiving circuit, the resistance value of the line resistance decreases depending on the installed line line length, and even if it becomes 0Ω
Considering a case where the following occurs, there is a problem in that the current flowing through the loop in the power receiving circuit increases, and as a result, the power consumption in the power receiving circuit increases.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は第1図に示すように、伝送線を介して交換
機又はPCM多重化装置10に接続され、電話機からの
シグナリング信号を受信してオン/オフの動作を行うス
イッチ60を含むループから成る受電回路20において
、ループに流れる電流を可変出来る電流可変手段70を
、上記ループに挿入した本発明の受電回路によって解決
される。
As shown in FIG. 1, the above problem arises from a loop including a switch 60 that is connected to an exchange or PCM multiplexer 10 via a transmission line and performs on/off operations by receiving signaling signals from telephones. This problem is solved by the power receiving circuit of the present invention, in which a current variable means 70 capable of varying the current flowing through the loop is inserted into the power receiving circuit 20 of the present invention.

〔作用〕[Effect]

第1図において、シグナリング信号によりスイッチ60
がオンになった時、伝送線に接続された受電−回路20
内の電流可変手段70、及びスイッチ60により形成さ
れるループに電流が流れる。そして、この電流値は伝送
線の抵抗の値によって変わる。
In FIG. 1, a signaling signal causes switch 60 to
When turned on, the power receiving circuit 20 connected to the transmission line
A current flows through a loop formed by the current variable means 70 and the switch 60 inside. This current value changes depending on the resistance value of the transmission line.

今、交換機10.PCM多重化装置30等の設置の変更
等によって伝送線の抵抗の値が0Ωになったとすると、
このループには大きい電流が流れる。
Now switchboard 10. Assuming that the resistance value of the transmission line becomes 0Ω due to changes in the installation of the PCM multiplexing device 30, etc.
A large current flows through this loop.

そして、受電回路20内のループで消費される消費電力
は、流れる電流の2乗に比例する。
The power consumed in the loop within the power receiving circuit 20 is proportional to the square of the flowing current.

このため、電流可変手段7oによりこの電流値を所定の
値になるように設定し直す事で、受電回路20内の消費
電力を小さくする事が出来る。
Therefore, by resetting this current value to a predetermined value using the current variable means 7o, the power consumption in the power receiving circuit 20 can be reduced.

〔実施例〕〔Example〕

第2図は本発明の第一の実施例の受電回路図である。 FIG. 2 is a power receiving circuit diagram of the first embodiment of the present invention.

第3図は本発明の第二の実施例の受電回路図である。FIG. 3 is a power receiving circuit diagram of a second embodiment of the present invention.

企図を通じて同一符号は同一対象物を示す。The same reference numerals refer to the same objects throughout the design.

まず、第2図において第一の実施例について説明する。First, a first embodiment will be described with reference to FIG.

交換機」と受電回路2を結ぶ回線の回線抵抗RL3 、
RL4の値が共に450Ωであったとする。又、Ro−
100Ω、R1= 300Ω、 R2= 600Ωとす
る。
The line resistance RL3 of the line connecting the exchanger and the power receiving circuit 2,
Assume that the values of RL4 are both 450Ω. Also, Ro-
100Ω, R1=300Ω, R2=600Ω.

又、交換機1内に設けたこのループへの供給電源を一5
0V とする。
In addition, the power supply to this loop provided in the exchange 1 is
Set it to 0V.

最初、R1、R2の両端に設けた電子スイッチSWI、
SW2をオンにしてR1,R2の両端を短絡すると、受
電回路2のループに流れる電流lは、 i =50V/(2x450  +100)Ω−50m
Aとなり、Roで消費される電力Poは、Po= i”
 ・Ro= (50・ICf″’)2X100 =0.
25ワツトとなる。
First, the electronic switch SWI provided at both ends of R1 and R2,
When SW2 is turned on and both ends of R1 and R2 are shorted, the current l flowing through the loop of power receiving circuit 2 is: i = 50V/(2x450 +100)Ω-50m
A, and the power Po consumed by Ro is Po= i”
・Ro= (50・ICf'')2X100 =0.
It becomes 25 watts.

今、伝送システムの再構築等により交換機1とPCM多
重化装置3の間の距離が短くなり、その回線抵抗が仮に
OΩ近くになったとする。この時受電回路2のループに
流れる電流iは、i =50V/100Ω=0.5Am
p。
Now, suppose that the distance between the exchange 1 and the PCM multiplexer 3 has been shortened due to reconstruction of the transmission system, and the line resistance has become close to 0Ω. At this time, the current i flowing in the loop of the power receiving circuit 2 is i = 50V/100Ω = 0.5Am
p.

となる。したがって、Roで消費される電力POは、P
o= i” ・Ro= (0,5)’ ・100 =2
5ワットとなり、100倍も大きくなる。
becomes. Therefore, the power PO consumed by Ro is P
o= i" ・Ro= (0,5)' ・100 = 2
5 watts, which is 100 times larger.

このため、電子スイッチSWI 、SW2をオフにする
と、ループの全抵抗値は100 +300 +600 
=1000Ωとなる。この時ループに流れる電流iは、
i =50V/1000Ω−50m八となり、ループの
全抵抗Rで消費される電力Poは、Po= i’ ・R
= (50・1O−3)”  X 1000=2.5ワ
ツトとなり、せいぜい10倍程度に抑えられる。
Therefore, when electronic switches SWI and SW2 are turned off, the total resistance of the loop is 100 + 300 + 600
=1000Ω. At this time, the current i flowing in the loop is
i = 50V/1000Ω-50m8, and the power Po consumed by the total resistance R of the loop is Po = i' ・R
= (50·1O-3)" x 1000 = 2.5 watts, which can be suppressed to about 10 times at most.

次に、第3図に示す第二の実施例について説明する。Next, a second embodiment shown in FIG. 3 will be described.

第3図においてもRo = 100Ω、RL3 、RL
4は共に450Ωとする。又、R3、R4は共に2にΩ
とする。
Also in Fig. 3, Ro = 100Ω, RL3, RL
4 are both 450Ω. Also, R3 and R4 are both 2Ω
shall be.

第一の実施例の場合と同様に、回線抵抗RL3 、RL
4が共に0Ωに変化したとする。この時、今までオンに
していた電子スイッチSW5をオフにし、同時にSW3
 、SW4を共にオンにする。
As in the case of the first embodiment, the line resistances RL3, RL
Suppose that both 4 and 4 change to 0Ω. At this time, turn off the electronic switch SW5 that was on until now, and at the same time turn off the electronic switch SW3.
, SW4 are both turned on.

この結果、回線抵抗値が変化する前にループに流れてい
た電流iは、第一の実施例の場合と同様に i =50V/1000Ω= 50mAとなり、変化後
のSW3 、SW4をオンにした後のループの電流iは
、 i =50V/ (100+ 1000)Ω=45.5
mAとなり、ループの全抵抗Rで消費される電力Poは
、Po=(45,5・10°”)’  ・100 +(
45,5/2  ・10°1)1  ・2000X2=
2.3ワツトとなり、変化前の10倍程度に抑えられる
As a result, the current i that was flowing in the loop before the line resistance value changed becomes i = 50V/1000Ω = 50mA, as in the case of the first embodiment, and after turning on SW3 and SW4 after the change. The current i in the loop is: i =50V/(100+1000)Ω=45.5
mA, and the power Po consumed by the total resistance R of the loop is Po = (45,5・10°")' ・100 + (
45,5/2 ・10°1) 1 ・2000X2=
It becomes 2.3 watts, which is about 10 times lower than before the change.

〔発明の効果] 以上説明のように本発明によれば、簡単な回路構成によ
り受電回路内の消費電力を低減化出来る。
[Effects of the Invention] As described above, according to the present invention, power consumption in the power receiving circuit can be reduced with a simple circuit configuration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理図、 第2図は本発明の第一の実施例の受電回路図、第3図は
本発明の第二の実施例の受電回路図、第4図は従来例の
PCM多重化装置内の受電回路の構成を示すブロック図
、 第5図は一例の電話通信システムの構成を示すブロック
図である。 図において 10は交換機又はPCM多重化装置、 20は受電回路、 30はPCM多重化装置又は交換機、 60はスイッチ、70は電流可変手段 を示す。 第2図 第3図
Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a power receiving circuit diagram of the first embodiment of the present invention, Fig. 3 is a power receiving circuit diagram of the second embodiment of the present invention, and Fig. 4 is a conventional example. FIG. 5 is a block diagram showing the configuration of an example telephone communication system. In the figure, 10 is an exchange or a PCM multiplexer, 20 is a power receiving circuit, 30 is a PCM multiplexer or exchange, 60 is a switch, and 70 is a current variable means. Figure 2 Figure 3

Claims (3)

【特許請求の範囲】[Claims] (1)伝送線を介して交換機又はPCM多重化装置(1
0)に接続され、電話機からのシグナリング信号を受信
してオン/オフの動作を行うスイッチ(60)を含むル
ープから成る受電回路(20)において、該ループに流
れる電流を可変出来る電流可変手段(70)を、該ルー
プに挿入した事を特徴とする受電回路。
(1) A switch or a PCM multiplexer (1) via a transmission line.
0), and includes a switch (60) that receives a signaling signal from a telephone and performs an on/off operation. 70) is inserted into the loop.
(2)前記電流可変手段(70)を、1個以上の直列に
接続した抵抗と、該抵抗のそれぞれに並列に接続したオ
ン/オフの切り替えが可能なスイッチの接点とで構成し
た事を特徴とする特許請求の範囲第1項記載の受電回路
(2) The current variable means (70) is characterized by comprising one or more resistors connected in series and contacts of switches connected in parallel to each of the resistors and capable of switching on/off. A power receiving circuit according to claim 1.
(3)前記電流可変手段(70)を、一個以上の抵抗と
該抵抗に直列に接続したオン/オフの切り替えが可能な
スイッチの接点の組を並列に接続した構成にした事を特
徴とする特許請求の範囲第1項記載の受電回路。
(3) The current variable means (70) is characterized by having a configuration in which one or more resistors and a set of contacts of a switch connected in series to the resistors and capable of switching on/off are connected in parallel. A power receiving circuit according to claim 1.
JP11630487A 1987-05-13 1987-05-13 Power receiving circuit Pending JPS63280557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11630487A JPS63280557A (en) 1987-05-13 1987-05-13 Power receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11630487A JPS63280557A (en) 1987-05-13 1987-05-13 Power receiving circuit

Publications (1)

Publication Number Publication Date
JPS63280557A true JPS63280557A (en) 1988-11-17

Family

ID=14683699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11630487A Pending JPS63280557A (en) 1987-05-13 1987-05-13 Power receiving circuit

Country Status (1)

Country Link
JP (1) JPS63280557A (en)

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