JPS63280475A - Josephson probing method - Google Patents

Josephson probing method

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Publication number
JPS63280475A
JPS63280475A JP62115305A JP11530587A JPS63280475A JP S63280475 A JPS63280475 A JP S63280475A JP 62115305 A JP62115305 A JP 62115305A JP 11530587 A JP11530587 A JP 11530587A JP S63280475 A JPS63280475 A JP S63280475A
Authority
JP
Japan
Prior art keywords
insulating layer
circuit
josephson
layer
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62115305A
Other languages
Japanese (ja)
Inventor
Masatake Kotani
誠剛 小谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62115305A priority Critical patent/JPS63280475A/en
Publication of JPS63280475A publication Critical patent/JPS63280475A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To measure any operational state transmitting high speed signals in an integrated circuit by a method wherein a Josephson sampler circuit using a quantum interference element with a magnetic field-coupling or directly coupling sensor is provided on a specified position in the integrated circuit through the intermediary of an insulating layer. CONSTITUTION:A sensor electrode 4, a bias terminal 5 and an output terminal 6 are formed on an insulating layer 3 by patterning process; these three elements 4, 5, 6 are coated with another insulating layer 7; an opening is made in the insulating layer 7 in a JJ forming part to be coated with an aluminum layer of several nm in thickness by sputtering process; the surface is oxidized at room temperature and pressure-reduced to form an alumina layer to be JJ 8, 8' on the aluminum layer. A substrate 1 covered with JJ is coated with an Nb layer to form an opposite electrode 9 by patterning process. The current flowing in a wiring to be observed in an IC made on the substrate 1 is probed by the SQID opposite electrode 9 which is magnetic field-coupled with the wiring and then its output and the sampling pulse of Josephson sampler circuit are combined with each other to be outputted from the output terminal 6. Consequently, any operational state accompanied by feeble high speed signals can be measured.

Description

【発明の詳細な説明】 〔概要〕 集積回路(IC)の所望の位置に磁界結合、または直接
結合するセンサをもつ量子干渉素子(SQ 10)を設
け、 5QIDを用いたジョセフソンサンプリング法に
より回路内の動作状態をプロービングする方法を提起し
、ジョセフソン接合と超伝導線により形成される閉回路
をもつS旧りの高速、高感度特性を利用して回路内の微
小、高速信号を測定できるようにする。
[Detailed Description of the Invention] [Summary] A quantum interference device (SQ 10) having a sensor that is magnetically coupled or directly coupled is provided at a desired position of an integrated circuit (IC), and the circuit is created using the Josephson sampling method using 5QID. We proposed a method for probing the operating state of circuits, and can measure small, high-speed signals in circuits by utilizing the old high-speed, high-sensitivity characteristics of S, which has a closed circuit formed by Josephson junctions and superconducting wires. do it like this.

プロービング後、必要に応じてジョセフソンサンプラー
回路を除去する。
After probing, remove the Josephson sampler circuit if necessary.

〔産業上の利用分野〕[Industrial application field]

本発明は5QIDを用いたICのプロービング方法に係
り、とくに高速、高感度のブロービング方法に関する。
The present invention relates to an IC probing method using 5QID, and particularly to a high-speed, high-sensitivity probing method.

半導体素子、ジョセフソン素子、または両者混合の素子
からなるICの開発において2回路設計の最適化のため
、または新規開発のため完成した回路内の任意の場所の
動作状態を高速、高感度にプロービングして観測するこ
とが重要である。
High-speed, high-sensitivity probing of the operating status of any location within a completed circuit for optimization of two-circuit design or for new development in the development of ICs consisting of semiconductor elements, Josephson elements, or a mixture of both. It is important to observe the

〔従来の技術〕[Conventional technology]

ICは高集積化に伴い取り扱う信号も微小化、高速化す
る傾向にあるため2回路内の動作状態を観測する方法、
特に微細信号、高速信号を伴う動作状態を観測する方法
を確立する必要がある。
As ICs become more highly integrated, the signals handled by them tend to become smaller and faster.
In particular, it is necessary to establish a method for observing operating conditions involving minute signals and high-speed signals.

また1回路設計の最適化1回路機能の高度化のためには
1回路のシュミレーションだけでは不十分で9回路の実
際の動作状態を観測することがますます重要となってき
た。
Furthermore, in order to optimize the design of a single circuit and improve the functionality of a single circuit, it is not enough to simply simulate one circuit, and it has become increasingly important to observe the actual operating states of nine circuits.

このため1回路内の任意の点・の微小、高速信号を直接
観測する方法が必要とされる。
Therefore, a method is required to directly observe minute, high-speed signals at arbitrary points within a circuit.

従来、 ICの動作状態を直接観測する方法として。Conventionally, as a method to directly observe the operating status of an IC.

つぎのような方法がとられていた。The following method was used.

■ 回路上にニードルを立てて測定する。■ Measure by standing the needle on the circuit.

■ 回路上に電子ビームを絞って照射、し、2次反射波
を測定し、それからその照射点の電位を計算する。
■ Focus and irradiate the electron beam onto the circuit, measure the secondary reflected waves, and then calculate the potential at the irradiation point.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来法によると。 According to the conventional method.

■では2回路上にニードルを立てることにより。■By placing a needle on the 2nd circuit.

回路を破壊することがある。またニードルの先端は有限
の大きさをもつため微小領域の測定が困難である。さら
に、高速信号の観測が困難である。
It may destroy the circuit. Furthermore, since the tip of the needle has a finite size, it is difficult to measure minute areas. Furthermore, it is difficult to observe high-speed signals.

■では、電子ビームを用い、高真空中で測定するため、
操作が困難である。また入射電子ビームのパワーが大き
いため、微小信号の測定が困難で高速信号には追随しな
い等の欠点がある。
■In order to measure in high vacuum using an electron beam,
Difficult to operate. Furthermore, since the power of the incident electron beam is large, it is difficult to measure small signals and cannot follow high-speed signals.

従って、微小、高速信号を取り扱う回路に対しては使用
が制限されるという問題があった。
Therefore, there is a problem in that its use is restricted for circuits that handle minute and high-speed signals.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

上記問題点の解決は、集積回路が形成された基板上の該
集積回路の所望の位置に、該集積回路と  。
The solution to the above problem is to place the integrated circuit at a desired position on the substrate on which the integrated circuit is formed.

絶縁層を介して磁界結合、または直接結合するセンサを
もつ量子干渉素子を用いたジョセフソンサンプラー回路
を設けて、該ジョセフソンサンプラー回路により該集積
回路内の動作状態を測定する本発明によるジョセフソン
ブロービング方法により達成される。
A Josephson sampler circuit according to the present invention includes a Josephson sampler circuit using a quantum interference element having a sensor magnetically coupled or directly coupled through an insulating layer, and the operating state in the integrated circuit is measured by the Josephson sampler circuit. This is accomplished by a blobbing method.

〔作用〕[Effect]

本発明はブロービングセンサをもつ5QIDを用いたジ
ョセフソンサンプラー回路を、ウェハに形成されたIC
内の任意のブロービング位置につくりっけ、 5QID
の高速、高怒度を利用してブロービング位置の微小、高
速信号を伴う動作状態を測定するようにしたものである
The present invention incorporates a Josephson sampler circuit using a 5QID with a probing sensor into an IC formed on a wafer.
Create any blobbing position within the 5QID
This method uses the high speed and high intensity of the brobbing to measure the operating state accompanied by minute and high speed signals at the probing position.

上記のように、 ICと、その上に重ねて作製されるジ
ョセフソンサンプラー回路は、その相対位置に任意性が
あるため、 IC内の観測点は自由に選ぶことができる
As mentioned above, the relative positions of the IC and the Josephson sampler circuit fabricated on top of it are arbitrary, so the observation point within the IC can be freely selected.

〔実施例〕〔Example〕

第1図(11,(2)は本発明の一実施例を説明する基
板の断面図と平面図である。
FIGS. 1(11, 2) are a sectional view and a plan view of a substrate illustrating an embodiment of the present invention.

図にいて、1はICを作製するための基板、2はICの
一部である配線、3はICとジョセフソンサンプラー回
路を分離する絶縁層、4はジョセフソンサンプラー回路
のセンサとなる5QIDの電極、5は5QIDのバイア
ス端子、6は5QIDの出力端子、7は5QrD内の絶
縁層、8.8’はジョセフソン接合(JJ)、  9は
5QIDの対向電極である。
In the figure, 1 is the substrate for manufacturing the IC, 2 is the wiring that is part of the IC, 3 is the insulating layer that separates the IC and the Josephson sampler circuit, and 4 is the 5QID that is the sensor of the Josephson sampler circuit. Electrodes: 5 is a bias terminal of 5QID, 6 is an output terminal of 5QID, 7 is an insulating layer within 5QrD, 8.8' is a Josephson junction (JJ), and 9 is a counter electrode of 5QID.

上記の電極、端子等を構成する各層は1例えばつぎのよ
うに形成する。
Each layer constituting the above electrodes, terminals, etc. is formed, for example, as follows.

図番 名称   物質名     厚さくnm) 3 絶縁層   Si0□      2004  セ
ンサ 電極     Nb             
2005  バイアス端子     Nb      
        2006 出力端子  Nb    
   2007 絶縁層   SiO,SiO□   
 2008  JJ     Nb/A1zO3/Nb
9 対向電極  Nb   、     200上記の
超伝導物質ニオブ(Nb)はDC,またはrfマグネト
ロンスパッタ法により被着する。
Drawing number Name Material name Thickness (nm) 3 Insulating layer Si0□ 2004 Sensor Electrode Nb
2005 Bias terminal Nb
2006 Output terminal Nb
2007 Insulating layer SiO, SiO□
2008 JJ Nb/A1zO3/Nb
9 Counter electrode Nb, 200 The above superconducting material niobium (Nb) is deposited by DC or RF magnetron sputtering.

まず、絶縁層3上に厚さ200 nm0Nb層を被着し
、バターニングしてセンサ電極4.バイアス端子5.出
力端子6を形成し、この上に絶縁層7を被着し、 JJ
形成部の絶縁層7を開口して、開口部に露出したNb層
をアルゴン(Ar)クリーニングした後、スパッタ法に
より厚さ数nunのアルミニウム(AI)層を被着し、
その表面を減圧下で常温酸化してJJ8,8’となるア
ルミナ(八1203)層をへ1層上に形成する。
First, a 200 nm thick Nb layer is deposited on the insulating layer 3 and patterned to form the sensor electrode 4. Bias terminal 5. An output terminal 6 is formed, an insulating layer 7 is deposited thereon, and JJ
After opening the insulating layer 7 in the formation part and cleaning the Nb layer exposed in the opening with argon (Ar), an aluminum (AI) layer several nanometers thick is deposited by sputtering.
The surface is oxidized at room temperature under reduced pressure to form an alumina (81203) layer, which becomes JJ8,8', one layer above.

JJの作製法としては、 Nb/AlO,/Nbを連続
的に作製した後、必要な大きさにエツチング等により加
工する方法もある。
As a method for manufacturing JJ, there is also a method of continuously manufacturing Nb/AlO,/Nb and then processing it to a required size by etching or the like.

ついで、 JJを覆って基板上にNb層を被着し、パタ
ーニングして対向電極9を形成する。
Next, a Nb layer is deposited on the substrate, covering the JJs, and patterned to form the counter electrode 9.

これにより、センサ電極4−バイアス端子5−JJ8一
対向電極9−JJ8’−出力端子6−センサ電極4の超
伝導閉回路をもつ5QIDが形成される。
As a result, a 5QID having a superconducting closed circuit of sensor electrode 4, bias terminal 5, JJ8, counter electrode 9, JJ8', output terminal 6, and sensor electrode 4 is formed.

この実施例によれば、基板上に作製されたIC内の、あ
る観測したい配線に流れる電流は、その配線に磁界結合
した5QIDによって測定される。
According to this embodiment, a current flowing through a certain wiring to be observed in an IC fabricated on a substrate is measured by a 5QID magnetically coupled to the wiring.

第2図はジョセフソンサンプラー回路の一例を示す回路
図である。
FIG. 2 is a circuit diagram showing an example of a Josephson sampler circuit.

図の左側の回路はサンプリングパルス発生器で。The circuit on the left side of the diagram is a sampling pulse generator.

コントロール回路21にトリガがかかると電源Eに接続
されたJJ22は抵抗23を介してステップ関数の電流
波形をJJ24に入力する。JJ24の出力はJJのラ
ンチング特性により半値幅が2〜5 psのシャープな
サンプリングパルスが得られる。
When the control circuit 21 is triggered, the JJ 22 connected to the power source E inputs a step function current waveform to the JJ 24 via the resistor 23. The output of JJ24 provides a sharp sampling pulse with a half width of 2 to 5 ps due to the launching characteristics of JJ.

一方被測定ICの配線2の電流波形は磁界結合により5
QIDにブロービングされて、その出力とサンプリング
パルスとが合成されて出力端子6より出力される。
On the other hand, the current waveform of wiring 2 of the IC to be measured changes to 5 due to magnetic field coupling.
The QID is blown, and its output and sampling pulse are combined and output from the output terminal 6.

ここで、被測定ICの配線2の電流波形のトリガは、可
変遅延器25によりサンプリングパルスのトリガより種
々の値に遅延させて配線2の電流波形をカバーしてサン
プリングすることができる。
Here, the trigger of the current waveform of the wiring 2 of the IC to be measured is delayed by various values from the trigger of the sampling pulse by the variable delay device 25, so that the current waveform of the wiring 2 can be covered and sampled.

実施例の測定精度は9時間分解能が2 pS、電流分解
能は5μ八へ度であった。
The measurement accuracy of the example was as follows: 9-hour resolution was 2 pS, and current resolution was 5μ8 degrees.

これは従来例のEBプローバの時間分解能が数10pS
、電圧分解能は数V程度に比較すると、格段に向上して
いることが分かる。
This means that the time resolution of the conventional EB prober is several tens of pS.
, it can be seen that the voltage resolution is significantly improved when compared to about several volts.

ICとジョセフソンサンプラー回路の結合は、磁界結合
の他に直接結合、すなわち直接電流を導き出してセンス
する方法がある。この場合は感度はよいが、ICとジョ
セフソンサンプラー回路の直接結合による相互干渉のた
め測定結果の解析が困難であるという欠点がある。
In addition to magnetic field coupling, there is a method of coupling the IC and the Josephson sampler circuit by direct coupling, that is, directly drawing and sensing a current. In this case, although the sensitivity is good, there is a drawback that it is difficult to analyze the measurement results due to mutual interference due to direct coupling between the IC and the Josephson sampler circuit.

また、電圧デバイスのICの場合は抵抗を用いて電圧を
電流に変換して結合させることができる。
Further, in the case of a voltage device IC, a resistor can be used to convert a voltage into a current and couple the voltage with the current.

実施例においては、 ICとジョセフソンサンプラー回
路は絶縁層3により分離されているため、ブロービング
後必要に応じてエツチング等によりジョセフソンサンプ
ラー回路を除去し、 ICをもとどおりに戻すことは容
易にできる。
In the embodiment, the IC and the Josephson sampler circuit are separated by the insulating layer 3, so it is easy to remove the Josephson sampler circuit by etching or the like after blowing and return the IC to its original state. Can be done.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、基板上に形成した
ICの任意の場所における微小、高速信号を伴う動作状
態を測定することができる。
As described above, according to the present invention, it is possible to measure the operating state accompanied by minute and high-speed signals at any location of an IC formed on a substrate.

さらに、ジョセフソンサンプラー回路を除去ずることに
より、ICをもと状態に戻すことができるため、プロー
ビングによる損傷は生じない。
Furthermore, by removing the Josephson sampler circuit, the IC can be returned to its original state so that no damage is caused by probing.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(1)、 (21は本発明の一実施例を説明する
基板の断面図と平面図。 第2図はジョセフソンサンプラー回路の一例を示す回路
図である。 図において。 1はrcを作製するための基板。 2はICの一部である配線。 3はICとサンプラー回路を分離する絶縁層。 4はサンプラー回路のセンサとなる5QtDの電極。 5は5QIDのバイアス端子。 6は5QIDの出力端子。 7は5QID内の絶縁層。 8はジョセフソン接合(JJ) 。 9は5QIDの対向電極 (2)″f面図 91 クビ 99 )1図 トリ力゛ ジヨtフソンーツ°ニルーR011トQ  −伊J12
Figures 1 (1) and 21 are a cross-sectional view and a plan view of a substrate explaining an embodiment of the present invention. Figure 2 is a circuit diagram showing an example of a Josephson sampler circuit. In the figure, 1 is a rc 2 is a wiring that is part of the IC. 3 is an insulating layer that separates the IC and the sampler circuit. 4 is a 5QtD electrode that serves as a sensor for the sampler circuit. 5 is a 5QID bias terminal. 6 is a Output terminal of 5QID. 7 is the insulating layer inside 5QID. 8 is Josephson junction (JJ). 9 is the counter electrode of 5QID (2)"F-plane view 91 (99) To Q - Italy J12
figure

Claims (1)

【特許請求の範囲】[Claims]  集積回路が形成された基板上の該集積回路の所望の位
置に、該集積回路と絶縁層を介して磁界結合、または直
接結合するセンサをもつ量子干渉素子を用いたジョセフ
ソンサンプラー回路を設けて、該ジョセフソンサンプラ
ー回路により該集積回路内の動作状態を測定することを
特徴とするジョセフソンプロービング方法。
A Josephson sampler circuit using a quantum interference element having a sensor magnetically coupled or directly coupled to the integrated circuit via an insulating layer is provided at a desired position of the integrated circuit on the substrate on which the integrated circuit is formed. . A Josephson probing method, characterized in that an operating state within the integrated circuit is measured by the Josephson sampler circuit.
JP62115305A 1987-05-12 1987-05-12 Josephson probing method Pending JPS63280475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62115305A JPS63280475A (en) 1987-05-12 1987-05-12 Josephson probing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62115305A JPS63280475A (en) 1987-05-12 1987-05-12 Josephson probing method

Publications (1)

Publication Number Publication Date
JPS63280475A true JPS63280475A (en) 1988-11-17

Family

ID=14659338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62115305A Pending JPS63280475A (en) 1987-05-12 1987-05-12 Josephson probing method

Country Status (1)

Country Link
JP (1) JPS63280475A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6857180B2 (en) * 2002-03-22 2005-02-22 Headway Technologies, Inc. Method for fabricating a patterned synthetic longitudinal exchange biased GMR sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6857180B2 (en) * 2002-03-22 2005-02-22 Headway Technologies, Inc. Method for fabricating a patterned synthetic longitudinal exchange biased GMR sensor

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